Coincidence Counters versions log ======================================== Started Alan Stummer, 16 Jan 2009 FPGA, VERILOG ----------------------------------------------------------- ver 2.3 17 Aug 2010 Dylan Mahler (POF CS: 0673AAF5) -added latch of delay line taken from version 2.01 -accidentals unusually low [Alan: what are accidentals?] -different channels have different singles rates even when same signal going to both -also, seems like delay window isn't being set properly (accidentals unaffected by change) -FOUND ERROR, re-wired the asynchronous part [Alan: block diagram] and it works!!! Ver 2.2 11 Aug 2010 A.S. POF CS: - unknown Ver 2.1 11 Aug 2010 A.S. - major overhaul of state machine. Removed several states. - does not work! can't read APDs. -after changing state machine to go back to state 0 after last state (instead of state 1), APDs are read, but the counts are unstable (they jump around almost an order of magnitude from second to vsecond) ver2.01 17 Aug 2010 -suspect this is the same as ver2.00??, it works but still has that coincicdence revival Ver 2.00 ?? POF CS:06736F21 (from working unit) - works but: -as coincidence goes into dead time, signal comes back with coincidences. Ver 1.2 2009 A.S. - first attempt at latching APDs, for when delay is longer than APDs' pulse width. - does not appear to work, unknown details. - possibly does work but issue swamped by newer and improved APDs with lower output voltage (~2.25V into 50 Ohm). Ver 1.1 Nov 2009 A.S. - unknown details, not used. Ver 1.0 16 Jan 2009 A.S. - initial release to Krister for testing. - now includes command 0x06 to read FPGA version:revision. - possible problem wth >~7nS delays, unknown cause, possible artifact of newer and improved APDs with lower output voltage (~2.25V into 50 Ohm). RABBIT, DYNAMIC C ----------------------------------------------------------- ver 1.0.2 18 Nov 2011 A.S. - bug fix: could not read requested number of packets because was in ASCII, always defaulted to 8. - removed (commented out) rate display while running, slowed down too much for short cycles. - removed (commented out) display saying it is running, slowed down too much for short cycles. - now only displays when connected to host and when not. Ver 1.0.1 16 March 2010 A.S. - added display of IP address and port at startup. Ver 1.0.0 16 Jan 2009 A.S. - added display of FPGA version:revision at cold boot. - reduced coincidence counting down time when reading counters by reading all counters into Rabbit then immediately restarting FPGA running before sending packets to host. - cleaned up displays when connecting and losing host when running or not. - added unit's IP:port display to monitor posting when starting. - allowed long unit names, but only displays first 16 digits locally. Ver 0.9.3 15 Jan 2009 A.S. - initial release to Krister for testing. GUI, VB6 ----------------------------------------------------------- ver 1.1.5 8 Nov 2011 A.S. - added error handler to auto update feature (would error if not connected to unit). - added option to not display data (for testing speed). Ver 1.1.4 16 March 2010 A.S. - bug: now reads IP address from IP text window when latter changes (such as at boot). Ver 1.1.3 19 Nov 2009 A.S. - bug fix to saving data to file; was not reading data correctly. Ver 1.1.2 12 Feb 2009 A.S. - bug fix: would not run if no registry entries. ver 1.1.1 16 Jan 2009 A.S. - bug fix to big counter display, now limited by packet count. - various minor changes. ver 1.1.0 15 Jan 2009 A.S. - major overhaul for interum use in experiment including: - added option of rate display to four big counter displays. - added labels to display of counters 0 to 15. - added saving and recall in registry of all parameters. - added user setting of auto counter retrieval time. - added option to run for fixed time and then optionally save data to file. Ver 1.0.1 14 Jan 2009 A.S. - removed writing to file of some counters. - added commas to large numbers in big counter displays. ver 1.0.0 14 Jan 2009 A.S. - initial release to Krister Shalm