Analysis & Synthesis report for Coincidence_Detector
Wed Jun 25 08:40:46 2008
Quartus II Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Registers Removed During Synthesis
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (No Restructuring Performed)
 10. Parameter Settings for User Entity Instance: Counters_Serializers:main
 11. Analysis & Synthesis Messages
 12. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Jun 25 08:40:46 2008         ;
; Quartus II Version          ; 7.2 Build 203 02/05/2008 SP 2 SJ Full Version ;
; Revision Name               ; Coincidence_Detector                          ;
; Top-level Entity Name       ; Coincidence_Detector                          ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 1,759                                         ;
; Total pins                  ; 24                                            ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 0                                             ;
; DSP block 9-bit elements    ; 0                                             ;
; Total PLLs                  ; 0                                             ;
; Total DLLs                  ; 0                                             ;
+-----------------------------+-----------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                                ;
+--------------------------------------------------------------------------------+----------------------+----------------------+
; Option                                                                         ; Setting              ; Default Value        ;
+--------------------------------------------------------------------------------+----------------------+----------------------+
; Device                                                                         ; EP1C12Q240C6         ;                      ;
; Top-level entity name                                                          ; Coincidence_Detector ; Coincidence_Detector ;
; Family name                                                                    ; Cyclone              ; Stratix              ;
; Use smart compilation                                                          ; On                   ; Off                  ;
; Optimization Technique -- Cyclone                                              ; Speed                ; Balanced             ;
; Maximum processors allowed for parallel compilation                            ; 1                    ; 1                    ;
; Restructure Multiplexers                                                       ; Auto                 ; Auto                 ;
; Create Debugging Nodes for IP Cores                                            ; Off                  ; Off                  ;
; Preserve fewer node names                                                      ; On                   ; On                   ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                  ; Off                  ;
; Verilog Version                                                                ; Verilog_2001         ; Verilog_2001         ;
; VHDL Version                                                                   ; VHDL93               ; VHDL93               ;
; State Machine Processing                                                       ; Auto                 ; Auto                 ;
; Safe State Machine                                                             ; Off                  ; Off                  ;
; Extract Verilog State Machines                                                 ; On                   ; On                   ;
; Extract VHDL State Machines                                                    ; On                   ; On                   ;
; Ignore Verilog initial constructs                                              ; Off                  ; Off                  ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                   ; On                   ;
; Parallel Synthesis                                                             ; Off                  ; Off                  ;
; NOT Gate Push-Back                                                             ; On                   ; On                   ;
; Power-Up Don't Care                                                            ; On                   ; On                   ;
; Remove Redundant Logic Cells                                                   ; Off                  ; Off                  ;
; Remove Duplicate Registers                                                     ; On                   ; On                   ;
; Ignore CARRY Buffers                                                           ; Off                  ; Off                  ;
; Ignore CASCADE Buffers                                                         ; Off                  ; Off                  ;
; Ignore GLOBAL Buffers                                                          ; Off                  ; Off                  ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                  ; Off                  ;
; Ignore LCELL Buffers                                                           ; Off                  ; Off                  ;
; Ignore SOFT Buffers                                                            ; On                   ; On                   ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                  ; Off                  ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                   ; 70                   ;
; Auto Carry Chains                                                              ; On                   ; On                   ;
; Auto Open-Drain Pins                                                           ; On                   ; On                   ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                  ; Off                  ;
; Perform gate-level register retiming                                           ; Off                  ; Off                  ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                   ; On                   ;
; Auto ROM Replacement                                                           ; On                   ; On                   ;
; Auto RAM Replacement                                                           ; On                   ; On                   ;
; Auto Shift Register Replacement                                                ; Auto                 ; Auto                 ;
; Auto Clock Enable Replacement                                                  ; On                   ; On                   ;
; Allow Synchronous Control Signals                                              ; On                   ; On                   ;
; Force Use of Synchronous Clear Signals                                         ; Off                  ; Off                  ;
; Auto RAM Block Balancing                                                       ; On                   ; On                   ;
; Auto RAM to Logic Cell Conversion                                              ; Off                  ; Off                  ;
; Auto Resource Sharing                                                          ; Off                  ; Off                  ;
; Allow Any RAM Size For Recognition                                             ; Off                  ; Off                  ;
; Allow Any ROM Size For Recognition                                             ; Off                  ; Off                  ;
; Allow Any Shift Register Size For Recognition                                  ; Off                  ; Off                  ;
; Maximum Number of M512 Memory Blocks                                           ; Unlimited            ; Unlimited            ;
; Maximum Number of M4K/M9K Memory Blocks                                        ; Unlimited            ; Unlimited            ;
; Maximum Number of M-RAM/M144K Memory Blocks                                    ; Unlimited            ; Unlimited            ;
; Ignore translate_off and synthesis_off directives                              ; Off                  ; Off                  ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                   ; On                   ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                  ; Off                  ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                    ; 2                    ;
; PowerPlay Power Optimization                                                   ; Normal compilation   ; Normal compilation   ;
; HDL message level                                                              ; Level2               ; Level2               ;
; Suppress Register Optimization Related Messages                                ; Off                  ; Off                  ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                  ; 100                  ;
; Clock MUX Protection                                                           ; On                   ; On                   ;
; Block Design Naming                                                            ; Auto                 ; Auto                 ;
+--------------------------------------------------------------------------------+----------------------+----------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                             ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                             ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------+
; Coincidence_Detector.bdf         ; yes             ; User Block Diagram/Schematic File  ; C:/Projects/Archives/Coincident Detector/Altera/Coincidence_Detector.bdf ;
; Counters_Serializers.v           ; yes             ; User Verilog HDL File              ; C:/Projects/Archives/Coincident Detector/Altera/Counters_Serializers.v   ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 1759  ;
;     -- Combinational with no register       ; 1053  ;
;     -- Register only                        ; 645   ;
;     -- Combinational with a register        ; 61    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 873   ;
;     -- 3 input functions                    ; 79    ;
;     -- 2 input functions                    ; 156   ;
;     -- 1 input functions                    ; 6     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 1677  ;
;     -- arithmetic mode                      ; 82    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 52    ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 706   ;
; Total logic cells in carry chains           ; 85    ;
; I/O pins                                    ; 24    ;
; Maximum fan-out node                        ; Laser ;
; Maximum fan-out                             ; 706   ;
; Total fan-out                               ; 6184  ;
; Average fan-out                             ; 3.47  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                    ;
+--------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------+--------------+
; Compilation Hierarchy Node     ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                             ; Library Name ;
+--------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------+--------------+
; |Coincidence_Detector          ; 1759 (0)    ; 706          ; 0           ; 0            ; 0       ; 0         ; 0         ; 24   ; 0            ; 1053 (0)     ; 645 (0)           ; 61 (0)           ; 85 (0)          ; 0 (0)      ; |Coincidence_Detector                           ; work         ;
;    |Counters_Serializers:main| ; 1759 (1759) ; 706          ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1053 (1053)  ; 645 (645)         ; 61 (61)          ; 85 (85)         ; 0 (0)      ; |Coincidence_Detector|Counters_Serializers:main ; work         ;
+--------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------+
; Registers Removed During Synthesis                          ;
+----------------------------------------+--------------------+
; Register name                          ; Reason for Removal ;
+----------------------------------------+--------------------+
; Counters_Serializers:main|PtrCtr[5..7] ; Lost fanout        ;
; Total Number of Removed Registers = 3  ;                    ;
+----------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 706   ;
; Number of registers using Synchronous Clear  ; 36    ;
; Number of registers using Synchronous Load   ; 21    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 697   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed)                                                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------+
; 12:1               ; 8 bits    ; 64 LEs        ; 8 LEs                ; 56 LEs                 ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|PtrCtr[5]       ;
; 33:1               ; 8 bits    ; 176 LEs       ; 16 LEs               ; 160 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[16][39] ;
; 33:1               ; 8 bits    ; 176 LEs       ; 16 LEs               ; 160 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[16][25] ;
; 33:1               ; 8 bits    ; 176 LEs       ; 16 LEs               ; 160 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[16][19] ;
; 33:1               ; 8 bits    ; 176 LEs       ; 16 LEs               ; 160 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[16][14] ;
; 33:1               ; 8 bits    ; 176 LEs       ; 16 LEs               ; 160 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[16][6]  ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[15][12] ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[14][12] ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[13][12] ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[12][12] ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[11][12] ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[10][12] ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[9][12]  ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[8][20]  ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[7][34]  ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[6][22]  ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[5][8]   ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[4][17]  ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[3][8]   ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[2][4]   ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[1][33]  ;
; 34:1               ; 40 bits   ; 880 LEs       ; 40 LEs               ; 840 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|Counter[0][34]  ;
; 13:1               ; 3 bits    ; 24 LEs        ; 3 LEs                ; 21 LEs                 ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|PtrByte[1]      ;
; 119:1              ; 7 bits    ; 553 LEs       ; 406 LEs              ; 147 LEs                ; Yes        ; |Coincidence_Detector|Counters_Serializers:main|DataOut[4]      ;
; 16:1               ; 40 bits   ; 400 LEs       ; 400 LEs              ; 0 LEs                  ; No         ; |Coincidence_Detector|Counters_Serializers:main|Mux7            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Counters_Serializers:main ;
+----------------+----------+--------------------------------------------+
; Parameter Name ; Value    ; Type                                       ;
+----------------+----------+--------------------------------------------+
; NumAPD         ; 4        ; Signed Integer                             ;
; FirmRev        ; 00000010 ; Unsigned Binary                            ;
+----------------+----------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
    Info: Processing started: Wed Jun 25 08:40:21 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Coincidence_Detector -c Coincidence_Detector
Info: Found 1 design units, including 1 entities, in source file Coincidence_Detector.bdf
    Info: Found entity 1: Coincidence_Detector
Info: Found 1 design units, including 1 entities, in source file Counters_Serializers.v
    Info: Found entity 1: Counters_Serializers
Info: Elaborating entity "Coincidence_Detector" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "Coincidence_Detector" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "Counters_Serializers" for hierarchy "Counters_Serializers:main"
Warning (10230): Verilog HDL assignment warning at Counters_Serializers.v(79): truncated value with size 6 to match size of target (4)
Warning (10027): Verilog HDL or VHDL warning at the Counters_Serializers.v(94): index expression is not wide enough to address all of the elements in the array
Warning (10230): Verilog HDL assignment warning at Counters_Serializers.v(128): truncated value with size 32 to match size of target (8)
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
    Info: Register "Counters_Serializers:main|PtrCtr[5]" lost all its fanouts during netlist optimizations.
    Info: Register "Counters_Serializers:main|PtrCtr[6]" lost all its fanouts during netlist optimizations.
    Info: Register "Counters_Serializers:main|PtrCtr[7]" lost all its fanouts during netlist optimizations.
Warning: Design contains 6 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "APD_E"
    Warning (15610): No output dependent on input pin "APD_F"
    Warning (15610): No output dependent on input pin "Clk"
    Warning (15610): No output dependent on input pin "USBctrl[7]"
    Warning (15610): No output dependent on input pin "USBctrl[6]"
    Warning (15610): No output dependent on input pin "USBctrl[5]"
Info: Implemented 1783 device resources after synthesis - the final resource count might be different
    Info: Implemented 16 input pins
    Info: Implemented 0 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 1759 logic cells
Info: Generated suppressed messages file C:/Projects/Archives/Coincident Detector/Altera/Coincidence_Detector.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Allocated 158 megabytes of memory during processing
    Info: Processing ended: Wed Jun 25 08:40:47 2008
    Info: Elapsed time: 00:00:26


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Projects/Archives/Coincident Detector/Altera/Coincidence_Detector.map.smsg.


