Analysis & Synthesis report for BarrierShaper
Wed Sep 28 15:27:28 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Parameter Settings for User Entity Instance: lpm_ram_dq3:Black|altsyncram:altsyncram_component
 11. Parameter Settings for User Entity Instance: lpm_ram_dq3:Black2|altsyncram:altsyncram_component
 12. Parameter Settings for User Entity Instance: lpm_ram_dq4:Silver|altsyncram:altsyncram_component
 13. Parameter Settings for User Entity Instance: lpm_ram_dq4:Silver2|altsyncram:altsyncram_component
 14. Parameter Settings for User Entity Instance: lpm_rom1:Sin|altsyncram:altsyncram_component
 15. Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_0
 16. Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_1
 17. Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_2
 18. Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_3
 19. Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_4
 20. Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_divide:mod_rtl_5
 21. Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_divide:mod_rtl_6
 22. lpm_mult Parameter Settings by Entity Instance
 23. Analysis & Synthesis Equations
 24. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
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Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                               ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Sep 28 15:27:28 2005        ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition ;
; Revision Name               ; BarrierShaper                                ;
; Top-level Entity Name       ; BarrierShaper                                ;
; Family                      ; Cyclone                                      ;
; Total logic elements        ; 2,817                                        ;
; Total pins                  ; 45                                           ;
; Total virtual pins          ; 0                                            ;
; Total memory bits           ; 36,864                                       ;
; Total PLLs                  ; 0                                            ;
+-----------------------------+----------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                      ;
+--------------------------------------------------------------------+---------------+---------------+
; Option                                                             ; Setting       ; Default Value ;
+--------------------------------------------------------------------+---------------+---------------+
; Device                                                             ; EP1C3T100C6   ;               ;
; Top-level entity name                                              ; BarrierShaper ; BarrierShaper ;
; Family name                                                        ; Cyclone       ; Stratix       ;
; Use smart compilation                                              ; On            ; Off           ;
; Restructure Multiplexers                                           ; On            ; Auto          ;
; Optimization Technique -- Cyclone                                  ; Area          ; Balanced      ;
; Perform WYSIWYG Primitive Resynthesis                              ; On            ; Off           ;
; Create Debugging Nodes for IP Cores                                ; off           ; off           ;
; Preserve fewer node names                                          ; On            ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off           ; Off           ;
; Verilog Version                                                    ; Verilog_2001  ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93        ; VHDL93        ;
; State Machine Processing                                           ; Auto          ; Auto          ;
; Extract Verilog State Machines                                     ; On            ; On            ;
; Extract VHDL State Machines                                        ; On            ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On            ; On            ;
; NOT Gate Push-Back                                                 ; On            ; On            ;
; Power-Up Don't Care                                                ; On            ; On            ;
; Remove Redundant Logic Cells                                       ; Off           ; Off           ;
; Remove Duplicate Registers                                         ; On            ; On            ;
; Ignore CARRY Buffers                                               ; Off           ; Off           ;
; Ignore CASCADE Buffers                                             ; Off           ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off           ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off           ; Off           ;
; Ignore LCELL Buffers                                               ; Off           ; Off           ;
; Ignore SOFT Buffers                                                ; On            ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off           ; Off           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70            ; 70            ;
; Auto Carry Chains                                                  ; On            ; On            ;
; Auto Open-Drain Pins                                               ; On            ; On            ;
; Remove Duplicate Logic                                             ; On            ; On            ;
; Perform gate-level register retiming                               ; Off           ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On            ; On            ;
; Auto ROM Replacement                                               ; On            ; On            ;
; Auto RAM Replacement                                               ; On            ; On            ;
; Auto Shift Register Replacement                                    ; On            ; On            ;
; Auto Clock Enable Replacement                                      ; On            ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On            ; On            ;
; Auto RAM Block Balancing                                           ; On            ; On            ;
; Auto Resource Sharing                                              ; Off           ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off           ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off           ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off           ; Off           ;
; Maximum Number of M512 Memory Blocks                               ; -1            ; -1            ;
; Maximum Number of M4K Memory Blocks                                ; -1            ; -1            ;
; Maximum Number of M-RAM Memory Blocks                              ; -1            ; -1            ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off           ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                 ; On            ; On            ;
+--------------------------------------------------------------------+---------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                 ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                 ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+
; BarrierShaper.bdf                ; yes             ; User Block Diagram/Schematic File  ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/BarrierShaper.bdf          ;
; BSblock.v                        ; yes             ; User Verilog HDL File              ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/BSblock.v                  ;
; BS2.v                            ; yes             ; User Verilog HDL File              ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/BS2.v                      ;
; BS Slow DACs.v                   ; yes             ; User Verilog HDL File              ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/BS Slow DACs.v             ;
; TwosComp.v                       ; yes             ; User Verilog HDL File              ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/TwosComp.v                 ;
; increment.v                      ; yes             ; User Verilog HDL File              ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/increment.v                ;
; altsyncram.inc                   ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/altsyncram.inc                                ;
; lpm_ram_dq3.v                    ; yes             ; Other                              ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/lpm_ram_dq3.v              ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/altsyncram.tdf                                ;
; stratix_ram_block.inc            ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/stratix_ram_block.inc                         ;
; lpm_mux.inc                      ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/lpm_mux.inc                                   ;
; lpm_decode.inc                   ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/lpm_decode.inc                                ;
; aglobal50.inc                    ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/aglobal50.inc                                 ;
; a_rdenreg.inc                    ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/a_rdenreg.inc                                 ;
; altrom.inc                       ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/altrom.inc                                    ;
; altram.inc                       ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/altram.inc                                    ;
; altdpram.inc                     ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/altdpram.inc                                  ;
; altqpram.inc                     ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/altqpram.inc                                  ;
; db/altsyncram_9731.tdf           ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/altsyncram_9731.tdf     ;
; lpm_ram_dq4.v                    ; yes             ; Other                              ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/lpm_ram_dq4.v              ;
; lpm_rom1.tdf                     ; yes             ; Other                              ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/lpm_rom1.tdf               ;
; db/altsyncram_slp.tdf            ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/altsyncram_slp.tdf      ;
; lpm_mult.tdf                     ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/lpm_mult.tdf                                  ;
; lpm_add_sub.inc                  ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/lpm_add_sub.inc                               ;
; multcore.inc                     ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/multcore.inc                                  ;
; bypassff.inc                     ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/bypassff.inc                                  ;
; altshift.inc                     ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/altshift.inc                                  ;
; multcore.tdf                     ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/multcore.tdf                                  ;
; csa_add.inc                      ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/csa_add.inc                                   ;
; mpar_add.inc                     ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/mpar_add.inc                                  ;
; muleabz.inc                      ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/muleabz.inc                                   ;
; mul_lfrg.inc                     ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/mul_lfrg.inc                                  ;
; mul_boothc.inc                   ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/mul_boothc.inc                                ;
; alt_ded_mult.inc                 ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/alt_ded_mult.inc                              ;
; alt_ded_mult_y.inc               ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/alt_ded_mult_y.inc                            ;
; dffpipe.inc                      ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/dffpipe.inc                                   ;
; mul_boothc.tdf                   ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/mul_boothc.tdf                                ;
; mpar_add.tdf                     ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/mpar_add.tdf                                  ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/lpm_add_sub.tdf                               ;
; addcore.inc                      ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/addcore.inc                                   ;
; look_add.inc                     ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/look_add.inc                                  ;
; alt_stratix_add_sub.inc          ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/alt_stratix_add_sub.inc                       ;
; alt_mercury_add_sub.inc          ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/alt_mercury_add_sub.inc                       ;
; addcore.tdf                      ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/addcore.tdf                                   ;
; a_csnbuffer.inc                  ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/a_csnbuffer.inc                               ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf                               ;
; altshift.tdf                     ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/altshift.tdf                                  ;
; lpm_divide.tdf                   ; yes             ; Megafunction                       ; c:/altera/quartus50sp1/libraries/megafunctions/lpm_divide.tdf                                ;
; abs_divider.inc                  ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/abs_divider.inc                               ;
; sign_div_unsign.inc              ; yes             ; Other                              ; c:/altera/quartus50sp1/libraries/megafunctions/sign_div_unsign.inc                           ;
; db/lpm_divide_odf.tdf            ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/lpm_divide_odf.tdf      ;
; db/sign_div_unsign_nhg.tdf       ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/sign_div_unsign_nhg.tdf ;
; db/alt_u_div_nld.tdf             ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/alt_u_div_nld.tdf       ;
; db/add_sub_ke8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_ke8.tdf         ;
; db/add_sub_le8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_le8.tdf         ;
; db/add_sub_me8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_me8.tdf         ;
; db/add_sub_ne8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_ne8.tdf         ;
; db/add_sub_oe8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_oe8.tdf         ;
; db/add_sub_pe8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_pe8.tdf         ;
; db/add_sub_qe8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_qe8.tdf         ;
; db/add_sub_re8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_re8.tdf         ;
; db/add_sub_se8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_se8.tdf         ;
; db/add_sub_qa8.tdf               ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/add_sub_qa8.tdf         ;
; db/lpm_divide_ndf.tdf            ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/lpm_divide_ndf.tdf      ;
; db/sign_div_unsign_mhg.tdf       ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/sign_div_unsign_mhg.tdf ;
; db/alt_u_div_lld.tdf             ; yes             ; Auto-Generated Megafunction        ; E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/db/alt_u_div_lld.tdf       ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 2817    ;
; Total combinational functions     ; 2729    ;
;     -- Total 4-input functions    ; 994     ;
;     -- Total 3-input functions    ; 207     ;
;     -- Total 2-input functions    ; 1349    ;
;     -- Total 1-input functions    ; 161     ;
;     -- Total 0-input functions    ; 18      ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 226     ;
; Total logic cells in carry chains ; 1412    ;
; I/O pins                          ; 45      ;
; Total memory bits                 ; 36864   ;
; Maximum fan-out node              ; Clk     ;
; Maximum fan-out                   ; 259     ;
; Total fan-out                     ; 10238   ;
; Average fan-out                   ; 3.48    ;
+-----------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                           ;
+------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                 ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                                                                                                                                                                                     ;
+------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |BarrierShaper                                             ; 2817 (0)    ; 226          ; 36864       ; 45   ; 0            ; 2591 (0)     ; 88 (0)            ; 138 (0)          ; 1412 (0)        ; |BarrierShaper                                                                                                                                                                                                                          ;
;    |BS2:ADChandler|                                        ; 140 (140)   ; 48           ; 0           ; 0    ; 0            ; 92 (92)      ; 33 (33)           ; 15 (15)          ; 10 (10)         ; |BarrierShaper|BS2:ADChandler                                                                                                                                                                                                           ;
;    |BSSlow:inst|                                           ; 74 (74)     ; 14           ; 0           ; 0    ; 0            ; 60 (60)      ; 9 (9)             ; 5 (5)            ; 12 (12)         ; |BarrierShaper|BSSlow:inst                                                                                                                                                                                                              ;
;    |BSblock:ChrisBS|                                       ; 2578 (556)  ; 164          ; 0           ; 0    ; 0            ; 2414 (392)   ; 46 (46)           ; 118 (118)        ; 1365 (196)      ; |BarrierShaper|BSblock:ChrisBS                                                                                                                                                                                                          ;
;       |lpm_divide:mod_rtl_5|                               ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 19 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_5                                                                                                                                                                                     ;
;          |lpm_divide_odf:auto_generated|                   ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 19 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_5|lpm_divide_odf:auto_generated                                                                                                                                                       ;
;             |sign_div_unsign_nhg:divider|                  ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 19 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_5|lpm_divide_odf:auto_generated|sign_div_unsign_nhg:divider                                                                                                                           ;
;                |alt_u_div_nld:divider|                     ; 32 (13)     ; 0            ; 0           ; 0    ; 0            ; 32 (13)      ; 0 (0)             ; 0 (0)            ; 19 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_5|lpm_divide_odf:auto_generated|sign_div_unsign_nhg:divider|alt_u_div_nld:divider                                                                                                     ;
;                   |add_sub_re8:add_sub_7|                  ; 9 (9)       ; 0            ; 0           ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 9 (9)           ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_5|lpm_divide_odf:auto_generated|sign_div_unsign_nhg:divider|alt_u_div_nld:divider|add_sub_re8:add_sub_7                                                                               ;
;                   |add_sub_se8:add_sub_8|                  ; 10 (10)     ; 0            ; 0           ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; 10 (10)         ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_5|lpm_divide_odf:auto_generated|sign_div_unsign_nhg:divider|alt_u_div_nld:divider|add_sub_se8:add_sub_8                                                                               ;
;       |lpm_divide:mod_rtl_6|                               ; 8 (0)       ; 0            ; 0           ; 0    ; 0            ; 8 (0)        ; 0 (0)             ; 0 (0)            ; 8 (0)           ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_6                                                                                                                                                                                     ;
;          |lpm_divide_ndf:auto_generated|                   ; 8 (0)       ; 0            ; 0           ; 0    ; 0            ; 8 (0)        ; 0 (0)             ; 0 (0)            ; 8 (0)           ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_6|lpm_divide_ndf:auto_generated                                                                                                                                                       ;
;             |sign_div_unsign_mhg:divider|                  ; 8 (0)       ; 0            ; 0           ; 0    ; 0            ; 8 (0)        ; 0 (0)             ; 0 (0)            ; 8 (0)           ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_6|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider                                                                                                                           ;
;                |alt_u_div_lld:divider|                     ; 8 (0)       ; 0            ; 0           ; 0    ; 0            ; 8 (0)        ; 0 (0)             ; 0 (0)            ; 8 (0)           ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_6|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_lld:divider                                                                                                     ;
;                   |add_sub_re8:add_sub_7|                  ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 8 (8)           ; |BarrierShaper|BSblock:ChrisBS|lpm_divide:mod_rtl_6|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_lld:divider|add_sub_re8:add_sub_7                                                                               ;
;       |lpm_mult:mult_rtl_0|                                ; 342 (0)     ; 0            ; 0           ; 0    ; 0            ; 342 (0)      ; 0 (0)             ; 0 (0)            ; 178 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0                                                                                                                                                                                      ;
;          |multcore:mult_core|                              ; 342 (162)   ; 0            ; 0           ; 0    ; 0            ; 342 (162)    ; 0 (0)             ; 0 (0)            ; 178 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core                                                                                                                                                                   ;
;             |mpar_add:padder|                              ; 155 (0)     ; 0            ; 0           ; 0    ; 0            ; 155 (0)      ; 0 (0)             ; 0 (0)            ; 155 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder                                                                                                                                                   ;
;                |lpm_add_sub:adder[0]|                      ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                                                                                              ;
;                   |addcore:adder|                          ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 22 (22)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[1]|                      ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]                                                                                                                              ;
;                   |addcore:adder|                          ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 22 (22)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[2]|                      ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]                                                                                                                              ;
;                   |addcore:adder|                          ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 22 (22)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[3]|                      ; 19 (0)      ; 0            ; 0           ; 0    ; 0            ; 19 (0)       ; 0 (0)             ; 0 (0)            ; 19 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]                                                                                                                              ;
;                   |addcore:adder|                          ; 19 (0)      ; 0            ; 0           ; 0    ; 0            ; 19 (0)       ; 0 (0)             ; 0 (0)            ; 19 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 19 (19)     ; 0            ; 0           ; 0    ; 0            ; 19 (19)      ; 0 (0)             ; 0 (0)            ; 19 (19)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |mpar_add:sub_par_add|                      ; 70 (0)      ; 0            ; 0           ; 0    ; 0            ; 70 (0)       ; 0 (0)             ; 0 (0)            ; 70 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                                                                                              ;
;                   |lpm_add_sub:adder[0]|                   ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                                         ;
;                      |addcore:adder|                       ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 24 (24)     ; 0            ; 0           ; 0    ; 0            ; 24 (24)      ; 0 (0)             ; 0 (0)            ; 24 (24)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |lpm_add_sub:adder[1]|                   ; 21 (0)      ; 0            ; 0           ; 0    ; 0            ; 21 (0)       ; 0 (0)             ; 0 (0)            ; 21 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]                                                                                                         ;
;                      |addcore:adder|                       ; 21 (0)      ; 0            ; 0           ; 0    ; 0            ; 21 (0)       ; 0 (0)             ; 0 (0)            ; 21 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 21 (21)     ; 0            ; 0           ; 0    ; 0            ; 21 (21)      ; 0 (0)             ; 0 (0)            ; 21 (21)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |mpar_add:sub_par_add|                   ; 25 (0)      ; 0            ; 0           ; 0    ; 0            ; 25 (0)       ; 0 (0)             ; 0 (0)            ; 25 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                                         ;
;                      |lpm_add_sub:adder[0]|                ; 25 (0)      ; 0            ; 0           ; 0    ; 0            ; 25 (0)       ; 0 (0)             ; 0 (0)            ; 25 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                    ;
;                         |addcore:adder|                    ; 25 (0)      ; 0            ; 0           ; 0    ; 0            ; 25 (0)       ; 0 (0)             ; 0 (0)            ; 25 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                      ;
;                            |a_csnbuffer:result_node|       ; 25 (25)     ; 0            ; 0           ; 0    ; 0            ; 25 (25)      ; 0 (0)             ; 0 (0)            ; 25 (25)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                              ;
;             |mul_boothc:booth_enc|                         ; 25 (25)     ; 0            ; 0           ; 0    ; 0            ; 25 (25)      ; 0 (0)             ; 0 (0)            ; 23 (23)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mul_boothc:booth_enc                                                                                                                                              ;
;       |lpm_mult:mult_rtl_1|                                ; 410 (0)     ; 0            ; 0           ; 0    ; 0            ; 410 (0)      ; 0 (0)             ; 0 (0)            ; 241 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1                                                                                                                                                                                      ;
;          |multcore:mult_core|                              ; 410 (169)   ; 0            ; 0           ; 0    ; 0            ; 410 (169)    ; 0 (0)             ; 0 (0)            ; 241 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core                                                                                                                                                                   ;
;             |mpar_add:padder|                              ; 216 (0)     ; 0            ; 0           ; 0    ; 0            ; 216 (0)      ; 0 (0)             ; 0 (0)            ; 216 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder                                                                                                                                                   ;
;                |lpm_add_sub:adder[0]|                      ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 32 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                                                                                              ;
;                   |addcore:adder|                          ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 32 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 32 (32)     ; 0            ; 0           ; 0    ; 0            ; 32 (32)      ; 0 (0)             ; 0 (0)            ; 32 (32)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[1]|                      ; 28 (0)      ; 0            ; 0           ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; 28 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]                                                                                                                              ;
;                   |addcore:adder|                          ; 28 (0)      ; 0            ; 0           ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; 28 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 28 (28)     ; 0            ; 0           ; 0    ; 0            ; 28 (28)      ; 0 (0)             ; 0 (0)            ; 28 (28)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[2]|                      ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]                                                                                                                              ;
;                   |addcore:adder|                          ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 24 (24)     ; 0            ; 0           ; 0    ; 0            ; 24 (24)      ; 0 (0)             ; 0 (0)            ; 24 (24)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[3]|                      ; 20 (0)      ; 0            ; 0           ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 20 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]                                                                                                                              ;
;                   |addcore:adder|                          ; 20 (0)      ; 0            ; 0           ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 20 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 20 (20)     ; 0            ; 0           ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 0 (0)            ; 20 (20)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[4]|                      ; 16 (0)      ; 0            ; 0           ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 16 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]                                                                                                                              ;
;                   |addcore:adder|                          ; 16 (0)      ; 0            ; 0           ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 16 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 16 (16)     ; 0            ; 0           ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 0 (0)            ; 16 (16)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |mpar_add:sub_par_add|                      ; 96 (0)      ; 0            ; 0           ; 0    ; 0            ; 96 (0)       ; 0 (0)             ; 0 (0)            ; 96 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                                                                                              ;
;                   |lpm_add_sub:adder[0]|                   ; 30 (0)      ; 0            ; 0           ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; 30 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                                         ;
;                      |addcore:adder|                       ; 30 (0)      ; 0            ; 0           ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; 30 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 30 (30)     ; 0            ; 0           ; 0    ; 0            ; 30 (30)      ; 0 (0)             ; 0 (0)            ; 30 (30)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |lpm_add_sub:adder[1]|                   ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]                                                                                                         ;
;                      |addcore:adder|                       ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 22 (22)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |mpar_add:sub_par_add|                   ; 44 (0)      ; 0            ; 0           ; 0    ; 0            ; 44 (0)       ; 0 (0)             ; 0 (0)            ; 44 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                                         ;
;                      |lpm_add_sub:adder[0]|                ; 26 (0)      ; 0            ; 0           ; 0    ; 0            ; 26 (0)       ; 0 (0)             ; 0 (0)            ; 26 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                    ;
;                         |addcore:adder|                    ; 26 (0)      ; 0            ; 0           ; 0    ; 0            ; 26 (0)       ; 0 (0)             ; 0 (0)            ; 26 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                      ;
;                            |a_csnbuffer:result_node|       ; 26 (26)     ; 0            ; 0           ; 0    ; 0            ; 26 (26)      ; 0 (0)             ; 0 (0)            ; 26 (26)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                              ;
;                      |mpar_add:sub_par_add|                ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                    ;
;                         |lpm_add_sub:adder[0]|             ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                               ;
;                            |addcore:adder|                 ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                 ;
;                               |addcore:first_seg_adder|    ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|addcore:first_seg_adder                         ;
;                                  |a_csnbuffer:result_node| ; 18 (18)     ; 0            ; 0           ; 0    ; 0            ; 18 (18)      ; 0 (0)             ; 0 (0)            ; 18 (18)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|addcore:first_seg_adder|a_csnbuffer:result_node ;
;             |mul_boothc:booth_enc|                         ; 25 (25)     ; 0            ; 0           ; 0    ; 0            ; 25 (25)      ; 0 (0)             ; 0 (0)            ; 25 (25)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_1|multcore:mult_core|mul_boothc:booth_enc                                                                                                                                              ;
;       |lpm_mult:mult_rtl_2|                                ; 410 (0)     ; 0            ; 0           ; 0    ; 0            ; 410 (0)      ; 0 (0)             ; 0 (0)            ; 241 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2                                                                                                                                                                                      ;
;          |multcore:mult_core|                              ; 410 (169)   ; 0            ; 0           ; 0    ; 0            ; 410 (169)    ; 0 (0)             ; 0 (0)            ; 241 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core                                                                                                                                                                   ;
;             |mpar_add:padder|                              ; 216 (0)     ; 0            ; 0           ; 0    ; 0            ; 216 (0)      ; 0 (0)             ; 0 (0)            ; 216 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder                                                                                                                                                   ;
;                |lpm_add_sub:adder[0]|                      ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 32 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                                                                                              ;
;                   |addcore:adder|                          ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 32 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 32 (32)     ; 0            ; 0           ; 0    ; 0            ; 32 (32)      ; 0 (0)             ; 0 (0)            ; 32 (32)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[1]|                      ; 28 (0)      ; 0            ; 0           ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; 28 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]                                                                                                                              ;
;                   |addcore:adder|                          ; 28 (0)      ; 0            ; 0           ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; 28 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 28 (28)     ; 0            ; 0           ; 0    ; 0            ; 28 (28)      ; 0 (0)             ; 0 (0)            ; 28 (28)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[2]|                      ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]                                                                                                                              ;
;                   |addcore:adder|                          ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 24 (24)     ; 0            ; 0           ; 0    ; 0            ; 24 (24)      ; 0 (0)             ; 0 (0)            ; 24 (24)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[3]|                      ; 20 (0)      ; 0            ; 0           ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 20 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]                                                                                                                              ;
;                   |addcore:adder|                          ; 20 (0)      ; 0            ; 0           ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 20 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 20 (20)     ; 0            ; 0           ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 0 (0)            ; 20 (20)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[4]|                      ; 16 (0)      ; 0            ; 0           ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 16 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]                                                                                                                              ;
;                   |addcore:adder|                          ; 16 (0)      ; 0            ; 0           ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 16 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 16 (16)     ; 0            ; 0           ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 0 (0)            ; 16 (16)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |mpar_add:sub_par_add|                      ; 96 (0)      ; 0            ; 0           ; 0    ; 0            ; 96 (0)       ; 0 (0)             ; 0 (0)            ; 96 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                                                                                              ;
;                   |lpm_add_sub:adder[0]|                   ; 30 (0)      ; 0            ; 0           ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; 30 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                                         ;
;                      |addcore:adder|                       ; 30 (0)      ; 0            ; 0           ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; 30 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 30 (30)     ; 0            ; 0           ; 0    ; 0            ; 30 (30)      ; 0 (0)             ; 0 (0)            ; 30 (30)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |lpm_add_sub:adder[1]|                   ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]                                                                                                         ;
;                      |addcore:adder|                       ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 22 (22)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |mpar_add:sub_par_add|                   ; 44 (0)      ; 0            ; 0           ; 0    ; 0            ; 44 (0)       ; 0 (0)             ; 0 (0)            ; 44 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                                         ;
;                      |lpm_add_sub:adder[0]|                ; 26 (0)      ; 0            ; 0           ; 0    ; 0            ; 26 (0)       ; 0 (0)             ; 0 (0)            ; 26 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                    ;
;                         |addcore:adder|                    ; 26 (0)      ; 0            ; 0           ; 0    ; 0            ; 26 (0)       ; 0 (0)             ; 0 (0)            ; 26 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                      ;
;                            |a_csnbuffer:result_node|       ; 26 (26)     ; 0            ; 0           ; 0    ; 0            ; 26 (26)      ; 0 (0)             ; 0 (0)            ; 26 (26)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                              ;
;                      |mpar_add:sub_par_add|                ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                    ;
;                         |lpm_add_sub:adder[0]|             ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                               ;
;                            |addcore:adder|                 ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                 ;
;                               |addcore:first_seg_adder|    ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|addcore:first_seg_adder                         ;
;                                  |a_csnbuffer:result_node| ; 18 (18)     ; 0            ; 0           ; 0    ; 0            ; 18 (18)      ; 0 (0)             ; 0 (0)            ; 18 (18)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|addcore:first_seg_adder|a_csnbuffer:result_node ;
;             |mul_boothc:booth_enc|                         ; 25 (25)     ; 0            ; 0           ; 0    ; 0            ; 25 (25)      ; 0 (0)             ; 0 (0)            ; 25 (25)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_2|multcore:mult_core|mul_boothc:booth_enc                                                                                                                                              ;
;       |lpm_mult:mult_rtl_3|                                ; 410 (0)     ; 0            ; 0           ; 0    ; 0            ; 410 (0)      ; 0 (0)             ; 0 (0)            ; 241 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3                                                                                                                                                                                      ;
;          |multcore:mult_core|                              ; 410 (169)   ; 0            ; 0           ; 0    ; 0            ; 410 (169)    ; 0 (0)             ; 0 (0)            ; 241 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core                                                                                                                                                                   ;
;             |mpar_add:padder|                              ; 216 (0)     ; 0            ; 0           ; 0    ; 0            ; 216 (0)      ; 0 (0)             ; 0 (0)            ; 216 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder                                                                                                                                                   ;
;                |lpm_add_sub:adder[0]|                      ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 32 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                                                                                              ;
;                   |addcore:adder|                          ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 32 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 32 (32)     ; 0            ; 0           ; 0    ; 0            ; 32 (32)      ; 0 (0)             ; 0 (0)            ; 32 (32)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[1]|                      ; 28 (0)      ; 0            ; 0           ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; 28 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]                                                                                                                              ;
;                   |addcore:adder|                          ; 28 (0)      ; 0            ; 0           ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; 28 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 28 (28)     ; 0            ; 0           ; 0    ; 0            ; 28 (28)      ; 0 (0)             ; 0 (0)            ; 28 (28)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[2]|                      ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]                                                                                                                              ;
;                   |addcore:adder|                          ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 24 (24)     ; 0            ; 0           ; 0    ; 0            ; 24 (24)      ; 0 (0)             ; 0 (0)            ; 24 (24)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[3]|                      ; 20 (0)      ; 0            ; 0           ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 20 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]                                                                                                                              ;
;                   |addcore:adder|                          ; 20 (0)      ; 0            ; 0           ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 20 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 20 (20)     ; 0            ; 0           ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 0 (0)            ; 20 (20)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[4]|                      ; 16 (0)      ; 0            ; 0           ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 16 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]                                                                                                                              ;
;                   |addcore:adder|                          ; 16 (0)      ; 0            ; 0           ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 16 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 16 (16)     ; 0            ; 0           ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 0 (0)            ; 16 (16)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |mpar_add:sub_par_add|                      ; 96 (0)      ; 0            ; 0           ; 0    ; 0            ; 96 (0)       ; 0 (0)             ; 0 (0)            ; 96 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                                                                                              ;
;                   |lpm_add_sub:adder[0]|                   ; 30 (0)      ; 0            ; 0           ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; 30 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                                         ;
;                      |addcore:adder|                       ; 30 (0)      ; 0            ; 0           ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; 30 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 30 (30)     ; 0            ; 0           ; 0    ; 0            ; 30 (30)      ; 0 (0)             ; 0 (0)            ; 30 (30)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |lpm_add_sub:adder[1]|                   ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]                                                                                                         ;
;                      |addcore:adder|                       ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 22 (22)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |mpar_add:sub_par_add|                   ; 44 (0)      ; 0            ; 0           ; 0    ; 0            ; 44 (0)       ; 0 (0)             ; 0 (0)            ; 44 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                                         ;
;                      |lpm_add_sub:adder[0]|                ; 26 (0)      ; 0            ; 0           ; 0    ; 0            ; 26 (0)       ; 0 (0)             ; 0 (0)            ; 26 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                    ;
;                         |addcore:adder|                    ; 26 (0)      ; 0            ; 0           ; 0    ; 0            ; 26 (0)       ; 0 (0)             ; 0 (0)            ; 26 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                      ;
;                            |a_csnbuffer:result_node|       ; 26 (26)     ; 0            ; 0           ; 0    ; 0            ; 26 (26)      ; 0 (0)             ; 0 (0)            ; 26 (26)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                              ;
;                      |mpar_add:sub_par_add|                ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                    ;
;                         |lpm_add_sub:adder[0]|             ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                               ;
;                            |addcore:adder|                 ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                 ;
;                               |addcore:first_seg_adder|    ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|addcore:first_seg_adder                         ;
;                                  |a_csnbuffer:result_node| ; 18 (18)     ; 0            ; 0           ; 0    ; 0            ; 18 (18)      ; 0 (0)             ; 0 (0)            ; 18 (18)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|addcore:first_seg_adder|a_csnbuffer:result_node ;
;             |mul_boothc:booth_enc|                         ; 25 (25)     ; 0            ; 0           ; 0    ; 0            ; 25 (25)      ; 0 (0)             ; 0 (0)            ; 25 (25)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_3|multcore:mult_core|mul_boothc:booth_enc                                                                                                                                              ;
;       |lpm_mult:mult_rtl_4|                                ; 410 (0)     ; 0            ; 0           ; 0    ; 0            ; 410 (0)      ; 0 (0)             ; 0 (0)            ; 241 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4                                                                                                                                                                                      ;
;          |multcore:mult_core|                              ; 410 (169)   ; 0            ; 0           ; 0    ; 0            ; 410 (169)    ; 0 (0)             ; 0 (0)            ; 241 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core                                                                                                                                                                   ;
;             |mpar_add:padder|                              ; 216 (0)     ; 0            ; 0           ; 0    ; 0            ; 216 (0)      ; 0 (0)             ; 0 (0)            ; 216 (0)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder                                                                                                                                                   ;
;                |lpm_add_sub:adder[0]|                      ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 32 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                                                                                              ;
;                   |addcore:adder|                          ; 32 (0)      ; 0            ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 0 (0)            ; 32 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 32 (32)     ; 0            ; 0           ; 0    ; 0            ; 32 (32)      ; 0 (0)             ; 0 (0)            ; 32 (32)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[1]|                      ; 28 (0)      ; 0            ; 0           ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; 28 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]                                                                                                                              ;
;                   |addcore:adder|                          ; 28 (0)      ; 0            ; 0           ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; 28 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 28 (28)     ; 0            ; 0           ; 0    ; 0            ; 28 (28)      ; 0 (0)             ; 0 (0)            ; 28 (28)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[2]|                      ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]                                                                                                                              ;
;                   |addcore:adder|                          ; 24 (0)      ; 0            ; 0           ; 0    ; 0            ; 24 (0)       ; 0 (0)             ; 0 (0)            ; 24 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 24 (24)     ; 0            ; 0           ; 0    ; 0            ; 24 (24)      ; 0 (0)             ; 0 (0)            ; 24 (24)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[3]|                      ; 20 (0)      ; 0            ; 0           ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 20 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]                                                                                                                              ;
;                   |addcore:adder|                          ; 20 (0)      ; 0            ; 0           ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 0 (0)            ; 20 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 20 (20)     ; 0            ; 0           ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 0 (0)            ; 20 (20)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |lpm_add_sub:adder[4]|                      ; 16 (0)      ; 0            ; 0           ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 16 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]                                                                                                                              ;
;                   |addcore:adder|                          ; 16 (0)      ; 0            ; 0           ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 16 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]|addcore:adder                                                                                                                ;
;                      |a_csnbuffer:result_node|             ; 16 (16)     ; 0            ; 0           ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 0 (0)            ; 16 (16)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[4]|addcore:adder|a_csnbuffer:result_node                                                                                        ;
;                |mpar_add:sub_par_add|                      ; 96 (0)      ; 0            ; 0           ; 0    ; 0            ; 96 (0)       ; 0 (0)             ; 0 (0)            ; 96 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                                                                                              ;
;                   |lpm_add_sub:adder[0]|                   ; 30 (0)      ; 0            ; 0           ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; 30 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                                         ;
;                      |addcore:adder|                       ; 30 (0)      ; 0            ; 0           ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; 30 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 30 (30)     ; 0            ; 0           ; 0    ; 0            ; 30 (30)      ; 0 (0)             ; 0 (0)            ; 30 (30)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |lpm_add_sub:adder[1]|                   ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]                                                                                                         ;
;                      |addcore:adder|                       ; 22 (0)      ; 0            ; 0           ; 0    ; 0            ; 22 (0)       ; 0 (0)             ; 0 (0)            ; 22 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder                                                                                           ;
;                         |a_csnbuffer:result_node|          ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 22 (22)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node                                                                   ;
;                   |mpar_add:sub_par_add|                   ; 44 (0)      ; 0            ; 0           ; 0    ; 0            ; 44 (0)       ; 0 (0)             ; 0 (0)            ; 44 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                                         ;
;                      |lpm_add_sub:adder[0]|                ; 26 (0)      ; 0            ; 0           ; 0    ; 0            ; 26 (0)       ; 0 (0)             ; 0 (0)            ; 26 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                                                    ;
;                         |addcore:adder|                    ; 26 (0)      ; 0            ; 0           ; 0    ; 0            ; 26 (0)       ; 0 (0)             ; 0 (0)            ; 26 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                                      ;
;                            |a_csnbuffer:result_node|       ; 26 (26)     ; 0            ; 0           ; 0    ; 0            ; 26 (26)      ; 0 (0)             ; 0 (0)            ; 26 (26)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node                                              ;
;                      |mpar_add:sub_par_add|                ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add                                                                                    ;
;                         |lpm_add_sub:adder[0]|             ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]                                                               ;
;                            |addcore:adder|                 ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder                                                 ;
;                               |addcore:first_seg_adder|    ; 18 (0)      ; 0            ; 0           ; 0    ; 0            ; 18 (0)       ; 0 (0)             ; 0 (0)            ; 18 (0)          ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|addcore:first_seg_adder                         ;
;                                  |a_csnbuffer:result_node| ; 18 (18)     ; 0            ; 0           ; 0    ; 0            ; 18 (18)      ; 0 (0)             ; 0 (0)            ; 18 (18)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|addcore:first_seg_adder|a_csnbuffer:result_node ;
;             |mul_boothc:booth_enc|                         ; 25 (25)     ; 0            ; 0           ; 0    ; 0            ; 25 (25)      ; 0 (0)             ; 0 (0)            ; 25 (25)         ; |BarrierShaper|BSblock:ChrisBS|lpm_mult:mult_rtl_4|multcore:mult_core|mul_boothc:booth_enc                                                                                                                                              ;
;    |TwosComp:inst3|                                        ; 25 (25)     ; 0            ; 0           ; 0    ; 0            ; 25 (25)      ; 0 (0)             ; 0 (0)            ; 25 (25)         ; |BarrierShaper|TwosComp:inst3                                                                                                                                                                                                           ;
;    |lpm_ram_dq3:Black2|                                    ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq3:Black2                                                                                                                                                                                                       ;
;       |altsyncram:altsyncram_component|                    ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq3:Black2|altsyncram:altsyncram_component                                                                                                                                                                       ;
;          |altsyncram_9731:auto_generated|                  ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq3:Black2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated                                                                                                                                        ;
;    |lpm_ram_dq3:Black|                                     ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq3:Black                                                                                                                                                                                                        ;
;       |altsyncram:altsyncram_component|                    ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq3:Black|altsyncram:altsyncram_component                                                                                                                                                                        ;
;          |altsyncram_9731:auto_generated|                  ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated                                                                                                                                         ;
;    |lpm_ram_dq4:Silver2|                                   ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq4:Silver2                                                                                                                                                                                                      ;
;       |altsyncram:altsyncram_component|                    ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq4:Silver2|altsyncram:altsyncram_component                                                                                                                                                                      ;
;          |altsyncram_9731:auto_generated|                  ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq4:Silver2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated                                                                                                                                       ;
;    |lpm_ram_dq4:Silver|                                    ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq4:Silver                                                                                                                                                                                                       ;
;       |altsyncram:altsyncram_component|                    ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq4:Silver|altsyncram:altsyncram_component                                                                                                                                                                       ;
;          |altsyncram_9731:auto_generated|                  ; 0 (0)       ; 0            ; 8192        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated                                                                                                                                        ;
;    |lpm_rom1:Sin|                                          ; 0 (0)       ; 0            ; 4096        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_rom1:Sin                                                                                                                                                                                                             ;
;       |altsyncram:altsyncram_component|                    ; 0 (0)       ; 0            ; 4096        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_rom1:Sin|altsyncram:altsyncram_component                                                                                                                                                                             ;
;          |altsyncram_slp:auto_generated|                   ; 0 (0)       ; 0            ; 4096        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |BarrierShaper|lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated                                                                                                                                               ;
+------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                   ;
+-----------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------+
; Name                                                                                          ; Type ; Mode        ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF        ;
+-----------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------+
; lpm_ram_dq3:Black2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ALTSYNCRAM  ; AUTO ; Single Port ; 512          ; 16           ; --           ; --           ; 8192 ; silver.mif ;
; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ALTSYNCRAM   ; AUTO ; Single Port ; 512          ; 16           ; --           ; --           ; 8192 ; silver.mif ;
; lpm_ram_dq4:Silver2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 512          ; 16           ; --           ; --           ; 8192 ; silver.mif ;
; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ALTSYNCRAM  ; AUTO ; Single Port ; 512          ; 16           ; --           ; --           ; 8192 ; silver.mif ;
; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|ALTSYNCRAM         ; AUTO ; ROM         ; 512          ; 16           ; --           ; --           ; 8192 ; sin.mif    ;
+-----------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 226   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 2     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 197   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |BarrierShaper|BSblock:ChrisBS|sinPtr2[4]       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |BarrierShaper|BSblock:ChrisBS|Dig[7]           ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |BarrierShaper|BSblock:ChrisBS|DACsAddHolder[0] ;
; 4:1                ; 32 bits   ; 64 LEs        ; 0 LEs                ; 64 LEs                 ; Yes        ; |BarrierShaper|BSblock:ChrisBS|ArbRampHold2[31] ;
; 16:1               ; 2 bits    ; 20 LEs        ; 2 LEs                ; 18 LEs                 ; Yes        ; |BarrierShaper|BSblock:ChrisBS|DACsAddress[0]   ;
; 6:1                ; 24 bits   ; 96 LEs        ; 48 LEs               ; 48 LEs                 ; Yes        ; |BarrierShaper|BSblock:ChrisBS|HugeCtr[32]      ;
; 17:1               ; 12 bits   ; 132 LEs       ; 12 LEs               ; 120 LEs                ; Yes        ; |BarrierShaper|BSblock:ChrisBS|DACsDWHolder[10] ;
; 16:1               ; 8 bits    ; 80 LEs        ; 24 LEs               ; 56 LEs                 ; Yes        ; |BarrierShaper|BSblock:ChrisBS|DataOut[7]       ;
; 22:1               ; 8 bits    ; 112 LEs       ; 32 LEs               ; 80 LEs                 ; Yes        ; |BarrierShaper|BSblock:ChrisBS|HugeCtr[24]      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_ram_dq3:Black|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-----------------------------------------+
; Parameter Name                     ; Value           ; Type                                    ;
+------------------------------------+-----------------+-----------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                 ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                          ;
; OPERATION_MODE                     ; SINGLE_PORT     ; Untyped                                 ;
; WIDTH_A                            ; 16              ; Integer                                 ;
; WIDTHAD_A                          ; 9               ; Integer                                 ;
; NUMWORDS_A                         ; 512             ; Integer                                 ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                 ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                 ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                 ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                 ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                 ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                 ;
; WIDTH_B                            ; 1               ; Untyped                                 ;
; WIDTHAD_B                          ; 1               ; Untyped                                 ;
; NUMWORDS_B                         ; 1               ; Untyped                                 ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                 ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                 ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                 ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                 ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                 ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                 ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                 ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                 ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                 ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                 ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                                 ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                 ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                 ;
; BYTE_SIZE                          ; 8               ; Untyped                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                 ;
; INIT_FILE                          ; silver.mif      ; Untyped                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                 ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                 ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                                 ;
; CBXI_PARAMETER                     ; altsyncram_9731 ; Untyped                                 ;
+------------------------------------+-----------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_ram_dq3:Black2|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+------------------------------------------+
; Parameter Name                     ; Value           ; Type                                     ;
+------------------------------------+-----------------+------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                  ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                               ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                             ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                             ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                           ;
; OPERATION_MODE                     ; SINGLE_PORT     ; Untyped                                  ;
; WIDTH_A                            ; 16              ; Integer                                  ;
; WIDTHAD_A                          ; 9               ; Integer                                  ;
; NUMWORDS_A                         ; 512             ; Integer                                  ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                  ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                  ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                  ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                  ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                  ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                  ;
; WIDTH_B                            ; 1               ; Untyped                                  ;
; WIDTHAD_B                          ; 1               ; Untyped                                  ;
; NUMWORDS_B                         ; 1               ; Untyped                                  ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                  ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                  ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                  ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                  ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                  ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                  ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                  ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                  ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                  ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                  ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                  ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                  ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                                  ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                  ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                  ;
; BYTE_SIZE                          ; 8               ; Untyped                                  ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                  ;
; INIT_FILE                          ; silver.mif      ; Untyped                                  ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                  ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                  ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                  ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                  ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                  ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                  ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                                  ;
; CBXI_PARAMETER                     ; altsyncram_9731 ; Untyped                                  ;
+------------------------------------+-----------------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_ram_dq4:Silver|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+------------------------------------------+
; Parameter Name                     ; Value           ; Type                                     ;
+------------------------------------+-----------------+------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                  ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                               ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                             ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                             ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                           ;
; OPERATION_MODE                     ; SINGLE_PORT     ; Untyped                                  ;
; WIDTH_A                            ; 16              ; Integer                                  ;
; WIDTHAD_A                          ; 9               ; Integer                                  ;
; NUMWORDS_A                         ; 512             ; Integer                                  ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                  ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                  ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                  ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                  ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                  ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                  ;
; WIDTH_B                            ; 1               ; Untyped                                  ;
; WIDTHAD_B                          ; 1               ; Untyped                                  ;
; NUMWORDS_B                         ; 1               ; Untyped                                  ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                  ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                  ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                  ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                  ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                  ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                  ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                  ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                  ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                  ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                  ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                  ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                  ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                                  ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                  ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                  ;
; BYTE_SIZE                          ; 8               ; Untyped                                  ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                  ;
; INIT_FILE                          ; silver.mif      ; Untyped                                  ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                  ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                  ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                  ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                  ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                  ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                  ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                                  ;
; CBXI_PARAMETER                     ; altsyncram_9731 ; Untyped                                  ;
+------------------------------------+-----------------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_ram_dq4:Silver2|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-------------------------------------------+
; Parameter Name                     ; Value           ; Type                                      ;
+------------------------------------+-----------------+-------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                   ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                              ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                              ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                            ;
; OPERATION_MODE                     ; SINGLE_PORT     ; Untyped                                   ;
; WIDTH_A                            ; 16              ; Integer                                   ;
; WIDTHAD_A                          ; 9               ; Integer                                   ;
; NUMWORDS_A                         ; 512             ; Integer                                   ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                   ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                   ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                   ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                   ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                   ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                   ;
; WIDTH_B                            ; 1               ; Untyped                                   ;
; WIDTHAD_B                          ; 1               ; Untyped                                   ;
; NUMWORDS_B                         ; 1               ; Untyped                                   ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                   ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                   ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                   ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                   ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                   ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                   ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                   ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                   ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                   ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                   ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                   ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                   ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                                   ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                   ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                   ;
; BYTE_SIZE                          ; 8               ; Untyped                                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                   ;
; INIT_FILE                          ; silver.mif      ; Untyped                                   ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                   ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                   ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                   ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                   ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                   ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                                   ;
; CBXI_PARAMETER                     ; altsyncram_9731 ; Untyped                                   ;
+------------------------------------+-----------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom1:Sin|altsyncram:altsyncram_component ;
+------------------------------------+----------------+-------------------------------------+
; Parameter Name                     ; Value          ; Type                                ;
+------------------------------------+----------------+-------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8              ; Untyped                             ;
; AUTO_CARRY_CHAINS                  ; ON             ; AUTO_CARRY                          ;
; IGNORE_CARRY_BUFFERS               ; OFF            ; IGNORE_CARRY                        ;
; AUTO_CASCADE_CHAINS                ; ON             ; AUTO_CASCADE                        ;
; IGNORE_CASCADE_BUFFERS             ; OFF            ; IGNORE_CASCADE                      ;
; OPERATION_MODE                     ; ROM            ; Untyped                             ;
; WIDTH_A                            ; 16             ; Untyped                             ;
; WIDTHAD_A                          ; 9              ; Untyped                             ;
; NUMWORDS_A                         ; 512            ; Untyped                             ;
; OUTDATA_REG_A                      ; CLOCK0         ; Untyped                             ;
; ADDRESS_ACLR_A                     ; NONE           ; Untyped                             ;
; OUTDATA_ACLR_A                     ; NONE           ; Untyped                             ;
; WRCONTROL_ACLR_A                   ; NONE           ; Untyped                             ;
; INDATA_ACLR_A                      ; NONE           ; Untyped                             ;
; BYTEENA_ACLR_A                     ; NONE           ; Untyped                             ;
; WIDTH_B                            ; 1              ; Untyped                             ;
; WIDTHAD_B                          ; 1              ; Untyped                             ;
; NUMWORDS_B                         ; 1              ; Untyped                             ;
; INDATA_REG_B                       ; CLOCK1         ; Untyped                             ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1         ; Untyped                             ;
; RDCONTROL_REG_B                    ; CLOCK1         ; Untyped                             ;
; ADDRESS_REG_B                      ; CLOCK1         ; Untyped                             ;
; OUTDATA_REG_B                      ; UNREGISTERED   ; Untyped                             ;
; BYTEENA_REG_B                      ; CLOCK1         ; Untyped                             ;
; INDATA_ACLR_B                      ; NONE           ; Untyped                             ;
; WRCONTROL_ACLR_B                   ; NONE           ; Untyped                             ;
; ADDRESS_ACLR_B                     ; NONE           ; Untyped                             ;
; OUTDATA_ACLR_B                     ; NONE           ; Untyped                             ;
; RDCONTROL_ACLR_B                   ; NONE           ; Untyped                             ;
; BYTEENA_ACLR_B                     ; NONE           ; Untyped                             ;
; WIDTH_BYTEENA_A                    ; 1              ; Untyped                             ;
; WIDTH_BYTEENA_B                    ; 1              ; Untyped                             ;
; RAM_BLOCK_TYPE                     ; AUTO           ; Untyped                             ;
; BYTE_SIZE                          ; 8              ; Untyped                             ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE      ; Untyped                             ;
; INIT_FILE                          ; sin.mif        ; Untyped                             ;
; INIT_FILE_LAYOUT                   ; PORT_A         ; Untyped                             ;
; MAXIMUM_DEPTH                      ; 0              ; Untyped                             ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL         ; Untyped                             ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL         ; Untyped                             ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL         ; Untyped                             ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL         ; Untyped                             ;
; DEVICE_FAMILY                      ; Cyclone        ; Untyped                             ;
; CBXI_PARAMETER                     ; altsyncram_slp ; Untyped                             ;
+------------------------------------+----------------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_0 ;
+------------------------------------------------+----------+--------------------------+
; Parameter Name                                 ; Value    ; Type                     ;
+------------------------------------------------+----------+--------------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY               ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY             ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE             ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE           ;
; LPM_WIDTHA                                     ; 15       ; Untyped                  ;
; LPM_WIDTHB                                     ; 16       ; Untyped                  ;
; LPM_WIDTHP                                     ; 31       ; Untyped                  ;
; LPM_WIDTHR                                     ; 31       ; Untyped                  ;
; LPM_WIDTHS                                     ; 1        ; Untyped                  ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped                  ;
; LPM_PIPELINE                                   ; 0        ; Untyped                  ;
; LATENCY                                        ; 0        ; Untyped                  ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped                  ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped                  ;
; USE_EAB                                        ; OFF      ; Untyped                  ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped                  ;
; DEVICE_FAMILY                                  ; Cyclone  ; Untyped                  ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped                  ;
; APEX20K_TECHNOLOGY_MAPPER                      ; Lut      ; TECH_MAPPER_APEX20K      ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped                  ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped                  ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped                  ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped                  ;
+------------------------------------------------+----------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_1 ;
+------------------------------------------------+----------+--------------------------+
; Parameter Name                                 ; Value    ; Type                     ;
+------------------------------------------------+----------+--------------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY               ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY             ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE             ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE           ;
; LPM_WIDTHA                                     ; 32       ; Untyped                  ;
; LPM_WIDTHB                                     ; 16       ; Untyped                  ;
; LPM_WIDTHP                                     ; 48       ; Untyped                  ;
; LPM_WIDTHR                                     ; 48       ; Untyped                  ;
; LPM_WIDTHS                                     ; 1        ; Untyped                  ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped                  ;
; LPM_PIPELINE                                   ; 0        ; Untyped                  ;
; LATENCY                                        ; 0        ; Untyped                  ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped                  ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped                  ;
; USE_EAB                                        ; OFF      ; Untyped                  ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped                  ;
; DEVICE_FAMILY                                  ; Cyclone  ; Untyped                  ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped                  ;
; APEX20K_TECHNOLOGY_MAPPER                      ; Lut      ; TECH_MAPPER_APEX20K      ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped                  ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped                  ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped                  ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped                  ;
+------------------------------------------------+----------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_2 ;
+------------------------------------------------+----------+--------------------------+
; Parameter Name                                 ; Value    ; Type                     ;
+------------------------------------------------+----------+--------------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY               ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY             ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE             ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE           ;
; LPM_WIDTHA                                     ; 32       ; Untyped                  ;
; LPM_WIDTHB                                     ; 16       ; Untyped                  ;
; LPM_WIDTHP                                     ; 48       ; Untyped                  ;
; LPM_WIDTHR                                     ; 48       ; Untyped                  ;
; LPM_WIDTHS                                     ; 1        ; Untyped                  ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped                  ;
; LPM_PIPELINE                                   ; 0        ; Untyped                  ;
; LATENCY                                        ; 0        ; Untyped                  ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped                  ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped                  ;
; USE_EAB                                        ; OFF      ; Untyped                  ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped                  ;
; DEVICE_FAMILY                                  ; Cyclone  ; Untyped                  ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped                  ;
; APEX20K_TECHNOLOGY_MAPPER                      ; Lut      ; TECH_MAPPER_APEX20K      ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped                  ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped                  ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped                  ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped                  ;
+------------------------------------------------+----------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_3 ;
+------------------------------------------------+----------+--------------------------+
; Parameter Name                                 ; Value    ; Type                     ;
+------------------------------------------------+----------+--------------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY               ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY             ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE             ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE           ;
; LPM_WIDTHA                                     ; 32       ; Untyped                  ;
; LPM_WIDTHB                                     ; 16       ; Untyped                  ;
; LPM_WIDTHP                                     ; 48       ; Untyped                  ;
; LPM_WIDTHR                                     ; 48       ; Untyped                  ;
; LPM_WIDTHS                                     ; 1        ; Untyped                  ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped                  ;
; LPM_PIPELINE                                   ; 0        ; Untyped                  ;
; LATENCY                                        ; 0        ; Untyped                  ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped                  ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped                  ;
; USE_EAB                                        ; OFF      ; Untyped                  ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped                  ;
; DEVICE_FAMILY                                  ; Cyclone  ; Untyped                  ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped                  ;
; APEX20K_TECHNOLOGY_MAPPER                      ; Lut      ; TECH_MAPPER_APEX20K      ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped                  ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped                  ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped                  ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped                  ;
+------------------------------------------------+----------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_mult:mult_rtl_4 ;
+------------------------------------------------+----------+--------------------------+
; Parameter Name                                 ; Value    ; Type                     ;
+------------------------------------------------+----------+--------------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY               ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY             ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE             ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE           ;
; LPM_WIDTHA                                     ; 32       ; Untyped                  ;
; LPM_WIDTHB                                     ; 16       ; Untyped                  ;
; LPM_WIDTHP                                     ; 48       ; Untyped                  ;
; LPM_WIDTHR                                     ; 48       ; Untyped                  ;
; LPM_WIDTHS                                     ; 1        ; Untyped                  ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped                  ;
; LPM_PIPELINE                                   ; 0        ; Untyped                  ;
; LATENCY                                        ; 0        ; Untyped                  ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped                  ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped                  ;
; USE_EAB                                        ; OFF      ; Untyped                  ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped                  ;
; DEVICE_FAMILY                                  ; Cyclone  ; Untyped                  ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped                  ;
; APEX20K_TECHNOLOGY_MAPPER                      ; Lut      ; TECH_MAPPER_APEX20K      ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped                  ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped                  ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped                  ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped                  ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped                  ;
+------------------------------------------------+----------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_divide:mod_rtl_5 ;
+------------------------+----------------+---------------------------------------------+
; Parameter Name         ; Value          ; Type                                        ;
+------------------------+----------------+---------------------------------------------+
; LPM_WIDTHN             ; 9              ; Untyped                                     ;
; LPM_WIDTHD             ; 8              ; Untyped                                     ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                     ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                     ;
; LPM_PIPELINE           ; 0              ; Untyped                                     ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                     ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                     ;
; CBXI_PARAMETER         ; lpm_divide_odf ; Untyped                                     ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                     ;
; OPTIMIZE_FOR_SPEED     ; 1              ; Untyped                                     ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                              ;
+------------------------+----------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: BSblock:ChrisBS|lpm_divide:mod_rtl_6 ;
+------------------------+----------------+---------------------------------------------+
; Parameter Name         ; Value          ; Type                                        ;
+------------------------+----------------+---------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                     ;
; LPM_WIDTHD             ; 8              ; Untyped                                     ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                     ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                     ;
; LPM_PIPELINE           ; 0              ; Untyped                                     ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                     ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                     ;
; CBXI_PARAMETER         ; lpm_divide_ndf ; Untyped                                     ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                     ;
; OPTIMIZE_FOR_SPEED     ; 1              ; Untyped                                     ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                              ;
+------------------------+----------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                              ;
+---------------------------------------+-------------------------------------+
; Name                                  ; Value                               ;
+---------------------------------------+-------------------------------------+
; Number of entity instances            ; 5                                   ;
; Entity Instance                       ; BSblock:ChrisBS|lpm_mult:mult_rtl_0 ;
;     -- LPM_WIDTHA                     ; 15                                  ;
;     -- LPM_WIDTHB                     ; 16                                  ;
;     -- LPM_WIDTHP                     ; 31                                  ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                  ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                  ;
;     -- USE_EAB                        ; OFF                                 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                  ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                  ;
; Entity Instance                       ; BSblock:ChrisBS|lpm_mult:mult_rtl_1 ;
;     -- LPM_WIDTHA                     ; 32                                  ;
;     -- LPM_WIDTHB                     ; 16                                  ;
;     -- LPM_WIDTHP                     ; 48                                  ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                  ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                  ;
;     -- USE_EAB                        ; OFF                                 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                  ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                  ;
; Entity Instance                       ; BSblock:ChrisBS|lpm_mult:mult_rtl_2 ;
;     -- LPM_WIDTHA                     ; 32                                  ;
;     -- LPM_WIDTHB                     ; 16                                  ;
;     -- LPM_WIDTHP                     ; 48                                  ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                  ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                  ;
;     -- USE_EAB                        ; OFF                                 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                  ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                  ;
; Entity Instance                       ; BSblock:ChrisBS|lpm_mult:mult_rtl_3 ;
;     -- LPM_WIDTHA                     ; 32                                  ;
;     -- LPM_WIDTHB                     ; 16                                  ;
;     -- LPM_WIDTHP                     ; 48                                  ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                  ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                  ;
;     -- USE_EAB                        ; OFF                                 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                  ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                  ;
; Entity Instance                       ; BSblock:ChrisBS|lpm_mult:mult_rtl_4 ;
;     -- LPM_WIDTHA                     ; 32                                  ;
;     -- LPM_WIDTHB                     ; 16                                  ;
;     -- LPM_WIDTHP                     ; 48                                  ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                  ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                  ;
;     -- USE_EAB                        ; OFF                                 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                  ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                  ;
+---------------------------------------+-------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Chris/FPGA Thing/ADCs Rock/Board 2 (TOP)/Board 2 (TOP)/Project/BarrierShaper.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
    Info: Processing started: Wed Sep 28 15:26:35 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BarrierShaper -c BarrierShaper
Info: Found 1 design units, including 1 entities, in source file BarrierShaper.bdf
    Info: Found entity 1: BarrierShaper
Warning: (10273) Verilog HDL warning at BSblock.v(63): extended using "x" or "z"
Info: Found 1 design units, including 1 entities, in source file BSblock.v
    Info: Found entity 1: BSblock
Info: Found 1 design units, including 1 entities, in source file BS2.v
    Info: Found entity 1: BS2
Info: Found 1 design units, including 1 entities, in source file BS Slow DACs.v
    Info: Found entity 1: BSSlow
Info: Found 1 design units, including 1 entities, in source file TwosComp.v
    Info: Found entity 1: TwosComp
Info: Found 1 design units, including 1 entities, in source file lpm_ram_dq1.tdf
    Info: Found entity 1: lpm_ram_dq1
Info: Found 1 design units, including 1 entities, in source file lpm_ram_dq2.tdf
    Info: Found entity 1: lpm_ram_dq2
Info: Found 1 design units, including 1 entities, in source file increment.v
    Info: Found entity 1: increment
Info: Found 1 design units, including 1 entities, in source file Scale.v
    Info: Found entity 1: Scale
Info: Elaborating entity "BarrierShaper" for the top level hierarchy
Info: Elaborating entity "BSSlow" for hierarchy "BSSlow:inst"
Info: Elaborating entity "BSblock" for hierarchy "BSblock:ChrisBS"
Info: (10035) Verilog HDL or VHDL information at BSblock.v(35): object "DACSingleOut" declared but not used
Warning: Verilog HDL assignment warning at BSblock.v(116): truncated value with size 8 to match size of target (1)
Warning: (10270) Verilog HDL statement warning at BSblock.v(115): incomplete Case Statement has no default case item
Warning: (10270) Verilog HDL statement warning at BSblock.v(128): incomplete Case Statement has no default case item
Warning: (10270) Verilog HDL statement warning at BSblock.v(141): incomplete Case Statement has no default case item
Warning: Output port "DACfClk" at BSblock.v(16) has no driver
Warning: Output port "DACf[11]" at BSblock.v(18) has no driver
Warning: Output port "DACf[10]" at BSblock.v(18) has no driver
Warning: Output port "DACf[9]" at BSblock.v(18) has no driver
Warning: Output port "DACf[8]" at BSblock.v(18) has no driver
Warning: Output port "DACf[7]" at BSblock.v(18) has no driver
Warning: Output port "DACf[6]" at BSblock.v(18) has no driver
Warning: Output port "DACf[5]" at BSblock.v(18) has no driver
Warning: Output port "DACf[4]" at BSblock.v(18) has no driver
Warning: Output port "DACf[3]" at BSblock.v(18) has no driver
Warning: Output port "DACf[2]" at BSblock.v(18) has no driver
Warning: Output port "DACf[1]" at BSblock.v(18) has no driver
Warning: Output port "DACf[0]" at BSblock.v(18) has no driver
Warning: Output port "Dig[6]" at BSblock.v(20) has no driver
Warning: Output port "Dig[5]" at BSblock.v(20) has no driver
Warning: Output port "Dig[4]" at BSblock.v(20) has no driver
Warning: Output port "Dig[3]" at BSblock.v(20) has no driver
Warning: Output port "Dig[2]" at BSblock.v(20) has no driver
Warning: Output port "Dig[1]" at BSblock.v(20) has no driver
Warning: Output port "Dig[0]" at BSblock.v(20) has no driver
Info: Using design file lpm_ram_dq3.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_ram_dq3
Info: Elaborating entity "lpm_ram_dq3" for hierarchy "lpm_ram_dq3:Black"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Warning: Ignoring archived or saved clearbox file altsyncram_h231.tdf for for hierarchy |BarrierShaper|lpm_ram_dq3:Black|altsyncram:altsyncram_component, because it has different set of parameters than the current elaboration.
Info: Elaborating entity "altsyncram" for hierarchy "lpm_ram_dq3:Black|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9731.tdf
    Info: Found entity 1: altsyncram_9731
Info: Elaborating entity "altsyncram_9731" for hierarchy "lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated"
Info: Elaborating entity "increment" for hierarchy "increment:inst1"
Warning: Verilog HDL assignment warning at increment.v(4): truncated value with size 16 to match size of target (9)
Info: Using design file lpm_ram_dq4.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_ram_dq4
Info: Elaborating entity "lpm_ram_dq4" for hierarchy "lpm_ram_dq4:Silver"
Info: Elaborating entity "BS2" for hierarchy "BS2:ADChandler"
Info: (10035) Verilog HDL or VHDL information at BS2.v(24): object "UpdateCt" declared but not used
Warning: (10270) Verilog HDL statement warning at BS2.v(55): incomplete Case Statement has no default case item
Warning: (10270) Verilog HDL statement warning at BS2.v(342): incomplete Case Statement has no default case item
Warning: (10270) Verilog HDL statement warning at BS2.v(53): incomplete Case Statement has no default case item
Warning: Output port "Port2[15]" at BS2.v(18) has no driver
Warning: Output port "Port2[14]" at BS2.v(18) has no driver
Warning: Output port "Port2[13]" at BS2.v(18) has no driver
Warning: Output port "Port2[12]" at BS2.v(18) has no driver
Warning: Output port "Port2[11]" at BS2.v(18) has no driver
Warning: Output port "Port2[10]" at BS2.v(18) has no driver
Warning: Output port "Port2[9]" at BS2.v(18) has no driver
Warning: Output port "Port2[8]" at BS2.v(18) has no driver
Warning: Output port "Port2[7]" at BS2.v(18) has no driver
Warning: Output port "Port2[6]" at BS2.v(18) has no driver
Warning: Output port "Port2[5]" at BS2.v(18) has no driver
Warning: Output port "Port2[4]" at BS2.v(18) has no driver
Warning: Output port "Port2[3]" at BS2.v(18) has no driver
Warning: Output port "Port2[2]" at BS2.v(18) has no driver
Warning: Output port "Port2[1]" at BS2.v(18) has no driver
Warning: Output port "Port2[0]" at BS2.v(18) has no driver
Warning: Output port "Port3[15]" at BS2.v(18) has no driver
Warning: Output port "Port3[14]" at BS2.v(18) has no driver
Warning: Output port "Port3[13]" at BS2.v(18) has no driver
Warning: Output port "Port3[12]" at BS2.v(18) has no driver
Warning: Output port "Port3[11]" at BS2.v(18) has no driver
Warning: Output port "Port3[10]" at BS2.v(18) has no driver
Warning: Output port "Port3[9]" at BS2.v(18) has no driver
Warning: Output port "Port3[8]" at BS2.v(18) has no driver
Warning: Output port "Port3[7]" at BS2.v(18) has no driver
Warning: Output port "Port3[6]" at BS2.v(18) has no driver
Warning: Output port "Port3[5]" at BS2.v(18) has no driver
Warning: Output port "Port3[4]" at BS2.v(18) has no driver
Warning: Output port "Port3[3]" at BS2.v(18) has no driver
Warning: Output port "Port3[2]" at BS2.v(18) has no driver
Warning: Output port "Port3[1]" at BS2.v(18) has no driver
Warning: Output port "Port3[0]" at BS2.v(18) has no driver
Warning: Output port "Port4[15]" at BS2.v(18) has no driver
Warning: Output port "Port4[14]" at BS2.v(18) has no driver
Warning: Output port "Port4[13]" at BS2.v(18) has no driver
Warning: Output port "Port4[12]" at BS2.v(18) has no driver
Warning: Output port "Port4[11]" at BS2.v(18) has no driver
Warning: Output port "Port4[10]" at BS2.v(18) has no driver
Warning: Output port "Port4[9]" at BS2.v(18) has no driver
Warning: Output port "Port4[8]" at BS2.v(18) has no driver
Warning: Output port "Port4[7]" at BS2.v(18) has no driver
Warning: Output port "Port4[6]" at BS2.v(18) has no driver
Warning: Output port "Port4[5]" at BS2.v(18) has no driver
Warning: Output port "Port4[4]" at BS2.v(18) has no driver
Warning: Output port "Port4[3]" at BS2.v(18) has no driver
Warning: Output port "Port4[2]" at BS2.v(18) has no driver
Warning: Output port "Port4[1]" at BS2.v(18) has no driver
Warning: Output port "Port4[0]" at BS2.v(18) has no driver
Warning: Output port "Port5[15]" at BS2.v(18) has no driver
Warning: Output port "Port5[14]" at BS2.v(18) has no driver
Warning: Output port "Port5[13]" at BS2.v(18) has no driver
Warning: Output port "Port5[12]" at BS2.v(18) has no driver
Warning: Output port "Port5[11]" at BS2.v(18) has no driver
Warning: Output port "Port5[10]" at BS2.v(18) has no driver
Warning: Output port "Port5[9]" at BS2.v(18) has no driver
Warning: Output port "Port5[8]" at BS2.v(18) has no driver
Warning: Output port "Port5[7]" at BS2.v(18) has no driver
Warning: Output port "Port5[6]" at BS2.v(18) has no driver
Warning: Output port "Port5[5]" at BS2.v(18) has no driver
Warning: Output port "Port5[4]" at BS2.v(18) has no driver
Warning: Output port "Port5[3]" at BS2.v(18) has no driver
Warning: Output port "Port5[2]" at BS2.v(18) has no driver
Warning: Output port "Port5[1]" at BS2.v(18) has no driver
Warning: Output port "Port5[0]" at BS2.v(18) has no driver
Warning: Output port "Port6[15]" at BS2.v(18) has no driver
Warning: Output port "Port6[14]" at BS2.v(18) has no driver
Warning: Output port "Port6[13]" at BS2.v(18) has no driver
Warning: Output port "Port6[12]" at BS2.v(18) has no driver
Warning: Output port "Port6[11]" at BS2.v(18) has no driver
Warning: Output port "Port6[10]" at BS2.v(18) has no driver
Warning: Output port "Port6[9]" at BS2.v(18) has no driver
Warning: Output port "Port6[8]" at BS2.v(18) has no driver
Warning: Output port "Port6[7]" at BS2.v(18) has no driver
Warning: Output port "Port6[6]" at BS2.v(18) has no driver
Warning: Output port "Port6[5]" at BS2.v(18) has no driver
Warning: Output port "Port6[4]" at BS2.v(18) has no driver
Warning: Output port "Port6[3]" at BS2.v(18) has no driver
Warning: Output port "Port6[2]" at BS2.v(18) has no driver
Warning: Output port "Port6[1]" at BS2.v(18) has no driver
Warning: Output port "Port6[0]" at BS2.v(18) has no driver
Warning: Output port "Port7[15]" at BS2.v(18) has no driver
Warning: Output port "Port7[14]" at BS2.v(18) has no driver
Warning: Output port "Port7[13]" at BS2.v(18) has no driver
Warning: Output port "Port7[12]" at BS2.v(18) has no driver
Warning: Output port "Port7[11]" at BS2.v(18) has no driver
Warning: Output port "Port7[10]" at BS2.v(18) has no driver
Warning: Output port "Port7[9]" at BS2.v(18) has no driver
Warning: Output port "Port7[8]" at BS2.v(18) has no driver
Warning: Output port "Port7[7]" at BS2.v(18) has no driver
Warning: Output port "Port7[6]" at BS2.v(18) has no driver
Warning: Output port "Port7[5]" at BS2.v(18) has no driver
Warning: Output port "Port7[4]" at BS2.v(18) has no driver
Warning: Output port "Port7[3]" at BS2.v(18) has no driver
Warning: Output port "Port7[2]" at BS2.v(18) has no driver
Warning: Output port "Port7[1]" at BS2.v(18) has no driver
Warning: Output port "Port7[0]" at BS2.v(18) has no driver
Info: Using design file lpm_rom1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_rom1
Info: Elaborating entity "lpm_rom1" for hierarchy "lpm_rom1:Sin"
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom1:Sin|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_slp.tdf
    Info: Found entity 1: altsyncram_slp
Info: Elaborating entity "altsyncram_slp" for hierarchy "lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated"
Info: Elaborating entity "TwosComp" for hierarchy "TwosComp:inst3"
Warning: Reduced register "BSblock:ChrisBS|DACsCommand[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "BSblock:ChrisBS|DACsCommand[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "BSblock:ChrisBS|DACsCommand[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "BSblock:ChrisBS|sinPtr2[0]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "BSblock:ChrisBS|DACsAddress[2]" merged to single register "BSblock:ChrisBS|DACsAddress[3]"
    Info: Duplicate register "BSblock:ChrisBS|DACsDWHolder[2]" merged to single register "BSblock:ChrisBS|DACsDWHolder[3]"
    Info: Duplicate register "BSblock:ChrisBS|DACsDWHolder[1]" merged to single register "BSblock:ChrisBS|DACsDWHolder[3]"
    Info: Duplicate register "BSblock:ChrisBS|DACsDWHolder[0]" merged to single register "BSblock:ChrisBS|DACsDWHolder[3]"
Warning: Reduced register "BSblock:ChrisBS|DACsDWHolder[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "BSblock:ChrisBS|sinPtr1[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "BS2:ADChandler|Ct[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "BS2:ADChandler|Ct[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "BSblock:ChrisBS|DACsAddHolder[8]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "BSblock:ChrisBS|NoStop" merged to single register "BSblock:ChrisBS|Dig[7]", power-up level changed
Warning: Reduced register "BSblock:ChrisBS|DACsAddress[3]" with stuck data_in port to stuck value GND
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/multcore.tdf
    Info: Found entity 1: multcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/mul_boothc.tdf
    Info: Found entity 1: mul_boothc
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/mpar_add.tdf
    Info: Found entity 1: mpar_add
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50sp1/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_odf.tdf
    Info: Found entity 1: lpm_divide_odf
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_nhg.tdf
    Info: Found entity 1: sign_div_unsign_nhg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_nld.tdf
    Info: Found entity 1: alt_u_div_nld
Info: Found 1 design units, including 1 entities, in source file db/add_sub_ke8.tdf
    Info: Found entity 1: add_sub_ke8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_le8.tdf
    Info: Found entity 1: add_sub_le8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_me8.tdf
    Info: Found entity 1: add_sub_me8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_ne8.tdf
    Info: Found entity 1: add_sub_ne8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_oe8.tdf
    Info: Found entity 1: add_sub_oe8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_pe8.tdf
    Info: Found entity 1: add_sub_pe8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_qe8.tdf
    Info: Found entity 1: add_sub_qe8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_re8.tdf
    Info: Found entity 1: add_sub_re8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_se8.tdf
    Info: Found entity 1: add_sub_se8
Info: Found 1 design units, including 1 entities, in source file db/add_sub_qa8.tdf
    Info: Found entity 1: add_sub_qa8
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ndf.tdf
    Info: Found entity 1: lpm_divide_ndf
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_mhg.tdf
    Info: Found entity 1: sign_div_unsign_mhg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_lld.tdf
    Info: Found entity 1: alt_u_div_lld
Info: Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 1285 WYSIWYG logic cells and I/Os untouched
Info: Ignored 72 buffer(s)
    Info: Ignored 72 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "DACfClk" stuck at GND
    Warning: Pin "DACf[11]" stuck at GND
    Warning: Pin "DACf[10]" stuck at GND
    Warning: Pin "DACf[9]" stuck at GND
    Warning: Pin "DACf[8]" stuck at GND
    Warning: Pin "DACf[7]" stuck at GND
    Warning: Pin "DACf[6]" stuck at GND
    Warning: Pin "DACf[5]" stuck at GND
    Warning: Pin "DACf[4]" stuck at GND
    Warning: Pin "DACf[3]" stuck at GND
    Warning: Pin "DACf[2]" stuck at GND
    Warning: Pin "DACf[1]" stuck at GND
    Warning: Pin "DACf[0]" stuck at GND
    Warning: Pin "Dig[6]" stuck at GND
    Warning: Pin "Dig[5]" stuck at GND
    Warning: Pin "Dig[4]" stuck at GND
    Warning: Pin "Dig[3]" stuck at GND
    Warning: Pin "Dig[2]" stuck at GND
    Warning: Pin "Dig[1]" stuck at GND
    Warning: Pin "Dig[0]" stuck at GND
Info: Removed 1 MSB VCC or GND address nodes from RAM block "lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|ALTSYNCRAM"
Info: Implemented 2942 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 27 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 2817 logic cells
    Info: Implemented 80 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 157 warnings
    Info: Processing ended: Wed Sep 28 15:27:27 2005
    Info: Elapsed time: 00:00:52


