Timing Analyzer report for BarrierShaper
Wed Sep 28 15:29:06 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'Clk'
  6. Clock Hold: 'Clk'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                     ;
+------------------------------+------------+-----------------------------------+----------------------------------+-----------------------------------------------------------------------------------+-------------------------------+------------+----------+--------------+
; Type                         ; Slack      ; Required Time                     ; Actual Time                      ; From                                                                              ; To                            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------+-----------------------------------+----------------------------------+-----------------------------------------------------------------------------------+-------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A        ; None                              ; 13.690 ns                        ; USB[14]                                                                           ; BSSlow:inst|DACsData          ;            ; Clk      ; 0            ;
; Worst-case tco               ; N/A        ; None                              ; 10.213 ns                        ; BS2:ADChandler|ADCsCS                                                             ; ADCsCS                        ; Clk        ;          ; 0            ;
; Worst-case tpd               ; N/A        ; None                              ; 11.078 ns                        ; USB[14]                                                                           ; USB[0]                        ;            ;          ; 0            ;
; Worst-case th                ; N/A        ; None                              ; -0.985 ns                        ; ADCsSDO                                                                           ; BS2:ADChandler|Port8[1]       ;            ; Clk      ; 0            ;
; Clock Setup: 'Clk'           ; -12.486 ns ; 100.00 MHz ( period = 10.000 ns ) ; 28.59 MHz ( period = 34.972 ns ) ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[6] ; BSSlow:inst|DACsData          ; Clk        ; Clk      ; 2304         ;
; Clock Hold: 'Clk'            ; 0.633 ns   ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; BS2:ADChandler|CurrentPort[2]                                                     ; BS2:ADChandler|CurrentPort[2] ; Clk        ; Clk      ; 0            ;
; Total number of failed paths ;            ;                                   ;                                  ;                                                                                   ;                               ;            ;          ; 2304         ;
+------------------------------+------------+-----------------------------------+----------------------------------+-----------------------------------------------------------------------------------+-------------------------------+------------+----------+--------------+


+-------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                              ;
+-------------------------------------------------------+--------------------+------+-----+-------------+
; Option                                                ; Setting            ; From ; To  ; Entity Name ;
+-------------------------------------------------------+--------------------+------+-----+-------------+
; Device Name                                           ; EP1C3T100C6        ;      ;     ;             ;
; Timing Models                                         ; Final              ;      ;     ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;     ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;     ;             ;
; Number of paths to report                             ; 100                ;      ;     ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;     ;             ;
; Use Fast Timing Models                                ; Off                ;      ;     ;             ;
; Report IO Paths Separately                            ; Off                ;      ;     ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;     ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;     ;             ;
; Cut off read during write signal paths                ; On                 ;      ;     ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;     ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;     ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;     ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;     ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;     ;             ;
; Enable Clock Latency                                  ; Off                ;      ;     ;             ;
; Clock Settings                                        ; Clk                ;      ; Clk ;             ;
+-------------------------------------------------------+--------------------+------+-----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clk             ; Clk                ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clk'                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                               ; To                               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; -12.486 ns                              ; 28.59 MHz ( period = 34.972 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[6]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.931 ns               ;
; -12.474 ns                              ; 28.61 MHz ( period = 34.948 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[8]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.919 ns               ;
; -12.434 ns                              ; 28.68 MHz ( period = 34.868 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[4]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.879 ns               ;
; -12.429 ns                              ; 28.69 MHz ( period = 34.858 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[1]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.874 ns               ;
; -12.405 ns                              ; 28.73 MHz ( period = 34.810 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[2]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.850 ns               ;
; -12.399 ns                              ; 28.74 MHz ( period = 34.798 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[10] ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.844 ns               ;
; -12.362 ns                              ; 28.80 MHz ( period = 34.724 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[7]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.807 ns               ;
; -12.353 ns                              ; 28.81 MHz ( period = 34.706 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[12] ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.798 ns               ;
; -12.302 ns                              ; 28.90 MHz ( period = 34.604 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[0]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.747 ns               ;
; -12.288 ns                              ; 28.92 MHz ( period = 34.576 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[5]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.733 ns               ;
; -12.266 ns                              ; 28.96 MHz ( period = 34.532 ns )                    ; BSblock:ChrisBS|sinCtr[5]                                                          ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 17.036 ns               ;
; -12.266 ns                              ; 28.96 MHz ( period = 34.532 ns )                    ; BSblock:ChrisBS|sinCtr[7]                                                          ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 17.036 ns               ;
; -12.258 ns                              ; 28.97 MHz ( period = 34.516 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[13] ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.703 ns               ;
; -12.256 ns                              ; 28.98 MHz ( period = 34.512 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[3]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.701 ns               ;
; -12.170 ns                              ; 29.12 MHz ( period = 34.340 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[11] ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.615 ns               ;
; -12.165 ns                              ; 29.13 MHz ( period = 34.330 ns )                    ; BSblock:ChrisBS|sinCtr[0]                                                          ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.935 ns               ;
; -12.123 ns                              ; 29.20 MHz ( period = 34.246 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[9]  ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 16.568 ns               ;
; -12.072 ns                              ; 29.29 MHz ( period = 34.144 ns )                    ; BSblock:ChrisBS|sinCtr[2]                                                          ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.842 ns               ;
; -12.033 ns                              ; 29.35 MHz ( period = 34.066 ns )                    ; BSblock:ChrisBS|sinCtr[6]                                                          ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.803 ns               ;
; -11.979 ns                              ; 29.45 MHz ( period = 33.958 ns )                    ; BSblock:ChrisBS|ArbRampHold2[17]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.749 ns               ;
; -11.941 ns                              ; 29.51 MHz ( period = 33.882 ns )                    ; BSblock:ChrisBS|ArbRampHold1[24]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.711 ns               ;
; -11.934 ns                              ; 29.53 MHz ( period = 33.868 ns )                    ; BSblock:ChrisBS|sinCtr[3]                                                          ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.704 ns               ;
; -11.915 ns                              ; 29.56 MHz ( period = 33.830 ns )                    ; BSblock:ChrisBS|sinCtr[1]                                                          ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.685 ns               ;
; -11.855 ns                              ; 29.66 MHz ( period = 33.710 ns )                    ; BSblock:ChrisBS|ArbRampHold2[27]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.625 ns               ;
; -11.840 ns                              ; 29.69 MHz ( period = 33.680 ns )                    ; BSblock:ChrisBS|ArbRampHold2[21]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.610 ns               ;
; -11.838 ns                              ; 29.69 MHz ( period = 33.676 ns )                    ; BSblock:ChrisBS|sinCtr[4]                                                          ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.608 ns               ;
; -11.791 ns                              ; 29.78 MHz ( period = 33.582 ns )                    ; BSblock:ChrisBS|ArbRampHold1[17]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.561 ns               ;
; -11.784 ns                              ; 29.79 MHz ( period = 33.568 ns )                    ; BSblock:ChrisBS|ArbRampHold1[27]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.554 ns               ;
; -11.695 ns                              ; 29.95 MHz ( period = 33.390 ns )                    ; BSblock:ChrisBS|ArbRampHold1[19]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.465 ns               ;
; -11.683 ns                              ; 29.97 MHz ( period = 33.366 ns )                    ; BSblock:ChrisBS|ArbRampHold2[25]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.453 ns               ;
; -11.670 ns                              ; 29.99 MHz ( period = 33.340 ns )                    ; BSblock:ChrisBS|ArbRampHold2[18]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.440 ns               ;
; -11.667 ns                              ; 30.00 MHz ( period = 33.334 ns )                    ; BSblock:ChrisBS|ArbRampHold1[21]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.437 ns               ;
; -11.643 ns                              ; 30.04 MHz ( period = 33.286 ns )                    ; BSblock:ChrisBS|ArbRampHold2[16]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.413 ns               ;
; -11.615 ns                              ; 30.09 MHz ( period = 33.230 ns )                    ; BSblock:ChrisBS|ArbRampHold1[16]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.385 ns               ;
; -11.591 ns                              ; 30.14 MHz ( period = 33.182 ns )                    ; BSblock:ChrisBS|ArbRampHold1[20]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.361 ns               ;
; -11.546 ns                              ; 30.22 MHz ( period = 33.092 ns )                    ; BSblock:ChrisBS|ArbRampHold2[19]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.316 ns               ;
; -11.536 ns                              ; 30.24 MHz ( period = 33.072 ns )                    ; BSblock:ChrisBS|ArbRampHold2[29]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.306 ns               ;
; -11.530 ns                              ; 30.25 MHz ( period = 33.060 ns )                    ; BSblock:ChrisBS|ArbRampHold1[18]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.300 ns               ;
; -11.488 ns                              ; 30.33 MHz ( period = 32.976 ns )                    ; BSblock:ChrisBS|ArbRampHold2[24]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.258 ns               ;
; -11.461 ns                              ; 30.37 MHz ( period = 32.922 ns )                    ; BSblock:ChrisBS|ArbRampHold2[28]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.231 ns               ;
; -11.458 ns                              ; 30.38 MHz ( period = 32.916 ns )                    ; BSblock:ChrisBS|ArbRampHold2[20]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.228 ns               ;
; -11.234 ns                              ; 30.80 MHz ( period = 32.468 ns )                    ; BSblock:ChrisBS|ArbRampHold1[29]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 16.004 ns               ;
; -11.191 ns                              ; 30.88 MHz ( period = 32.382 ns )                    ; BSblock:ChrisBS|ArbRampHold1[25]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.961 ns               ;
; -11.172 ns                              ; 30.92 MHz ( period = 32.344 ns )                    ; BSblock:ChrisBS|ArbRampHold2[23]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.942 ns               ;
; -11.107 ns                              ; 31.04 MHz ( period = 32.214 ns )                    ; lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[14] ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.445 ns                  ; 15.552 ns               ;
; -11.083 ns                              ; 31.09 MHz ( period = 32.166 ns )                    ; BSblock:ChrisBS|ArbRampHold1[30]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.853 ns               ;
; -11.063 ns                              ; 31.13 MHz ( period = 32.126 ns )                    ; BSblock:ChrisBS|ArbRampHold2[22]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.833 ns               ;
; -11.046 ns                              ; 31.16 MHz ( period = 32.092 ns )                    ; BSblock:ChrisBS|ArbRampHold2[31]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.816 ns               ;
; -10.926 ns                              ; 31.40 MHz ( period = 31.852 ns )                    ; BSblock:ChrisBS|ArbRampHold1[23]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.696 ns               ;
; -10.912 ns                              ; 31.42 MHz ( period = 31.824 ns )                    ; BSblock:ChrisBS|ArbRampHold2[30]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.682 ns               ;
; -10.866 ns                              ; 31.51 MHz ( period = 31.732 ns )                    ; BSblock:ChrisBS|ArbRampHold1[22]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.636 ns               ;
; -10.852 ns                              ; 31.54 MHz ( period = 31.704 ns )                    ; BSblock:ChrisBS|ArbRampHold1[28]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.622 ns               ;
; -10.740 ns                              ; 31.77 MHz ( period = 31.480 ns )                    ; BSblock:ChrisBS|ArbRampHold2[26]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.510 ns               ;
; -10.641 ns                              ; 31.97 MHz ( period = 31.282 ns )                    ; BSblock:ChrisBS|ArbRampHold1[26]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.411 ns               ;
; -10.445 ns                              ; 32.37 MHz ( period = 30.890 ns )                    ; BSblock:ChrisBS|ArbRampHold1[31]                                                   ; BSSlow:inst|DACsData             ; Clk        ; Clk      ; 5.000 ns                    ; 4.770 ns                  ; 15.215 ns               ;
; -9.132 ns                               ; 52.27 MHz ( period = 19.132 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold1[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.969 ns               ;
; -9.099 ns                               ; 52.36 MHz ( period = 19.099 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.936 ns               ;
; -9.072 ns                               ; 52.43 MHz ( period = 19.072 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold1[29] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.909 ns               ;
; -9.072 ns                               ; 52.43 MHz ( period = 19.072 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold1[30] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.909 ns               ;
; -9.072 ns                               ; 52.43 MHz ( period = 19.072 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold1[28] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.909 ns               ;
; -9.072 ns                               ; 52.43 MHz ( period = 19.072 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold1[27] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.909 ns               ;
; -9.072 ns                               ; 52.43 MHz ( period = 19.072 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold1[26] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.909 ns               ;
; -9.054 ns                               ; 52.48 MHz ( period = 19.054 ns )                    ; BSblock:ChrisBS|HugeCtr[7]                                                         ; BSblock:ChrisBS|ArbRampHold1[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.891 ns               ;
; -9.048 ns                               ; 52.50 MHz ( period = 19.048 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold1[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.885 ns               ;
; -9.042 ns                               ; 52.52 MHz ( period = 19.042 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.879 ns               ;
; -8.994 ns                               ; 52.65 MHz ( period = 18.994 ns )                    ; BSblock:ChrisBS|HugeCtr[7]                                                         ; BSblock:ChrisBS|ArbRampHold1[29] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.831 ns               ;
; -8.994 ns                               ; 52.65 MHz ( period = 18.994 ns )                    ; BSblock:ChrisBS|HugeCtr[7]                                                         ; BSblock:ChrisBS|ArbRampHold1[30] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.831 ns               ;
; -8.994 ns                               ; 52.65 MHz ( period = 18.994 ns )                    ; BSblock:ChrisBS|HugeCtr[7]                                                         ; BSblock:ChrisBS|ArbRampHold1[28] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.831 ns               ;
; -8.994 ns                               ; 52.65 MHz ( period = 18.994 ns )                    ; BSblock:ChrisBS|HugeCtr[7]                                                         ; BSblock:ChrisBS|ArbRampHold1[27] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.831 ns               ;
; -8.994 ns                               ; 52.65 MHz ( period = 18.994 ns )                    ; BSblock:ChrisBS|HugeCtr[7]                                                         ; BSblock:ChrisBS|ArbRampHold1[26] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.831 ns               ;
; -8.993 ns                               ; 52.65 MHz ( period = 18.993 ns )                    ; BSblock:ChrisBS|HugeCtr[7]                                                         ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.830 ns               ;
; -8.988 ns                               ; 52.66 MHz ( period = 18.988 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold1[29] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.825 ns               ;
; -8.988 ns                               ; 52.66 MHz ( period = 18.988 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold1[30] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.825 ns               ;
; -8.988 ns                               ; 52.66 MHz ( period = 18.988 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold1[28] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.825 ns               ;
; -8.988 ns                               ; 52.66 MHz ( period = 18.988 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold1[27] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.825 ns               ;
; -8.988 ns                               ; 52.66 MHz ( period = 18.988 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold1[26] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.825 ns               ;
; -8.931 ns                               ; 52.82 MHz ( period = 18.931 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold2[30] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.768 ns               ;
; -8.921 ns                               ; 52.85 MHz ( period = 18.921 ns )                    ; BSblock:ChrisBS|HugeCtr[14]                                                        ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.758 ns               ;
; -8.913 ns                               ; 52.87 MHz ( period = 18.913 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold2[29] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.750 ns               ;
; -8.913 ns                               ; 52.87 MHz ( period = 18.913 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold2[28] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.750 ns               ;
; -8.913 ns                               ; 52.87 MHz ( period = 18.913 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold2[27] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.750 ns               ;
; -8.913 ns                               ; 52.87 MHz ( period = 18.913 ns )                    ; BSblock:ChrisBS|HugeCtr[11]                                                        ; BSblock:ChrisBS|ArbRampHold2[26] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.750 ns               ;
; -8.911 ns                               ; 52.88 MHz ( period = 18.911 ns )                    ; BSblock:ChrisBS|HugeCtr[12]                                                        ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.830 ns                  ; 18.741 ns               ;
; -8.910 ns                               ; 52.88 MHz ( period = 18.910 ns )                    ; BSblock:ChrisBS|HugeCtr[15]                                                        ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.747 ns               ;
; -8.898 ns                               ; 52.92 MHz ( period = 18.898 ns )                    ; BSblock:ChrisBS|HugeCtr[9]                                                         ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.735 ns               ;
; -8.874 ns                               ; 52.98 MHz ( period = 18.874 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold2[30] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.711 ns               ;
; -8.866 ns                               ; 53.01 MHz ( period = 18.866 ns )                    ; BSblock:ChrisBS|HugeCtr[10]                                                        ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.703 ns               ;
; -8.863 ns                               ; 53.01 MHz ( period = 18.863 ns )                    ; BSblock:ChrisBS|HugeCtr[15]                                                        ; BSblock:ChrisBS|ArbRampHold1[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.700 ns               ;
; -8.859 ns                               ; 53.03 MHz ( period = 18.859 ns )                    ; BSblock:ChrisBS|HugeCtr[14]                                                        ; BSblock:ChrisBS|ArbRampHold1[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.696 ns               ;
; -8.856 ns                               ; 53.03 MHz ( period = 18.856 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold2[29] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.693 ns               ;
; -8.856 ns                               ; 53.03 MHz ( period = 18.856 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold2[28] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.693 ns               ;
; -8.856 ns                               ; 53.03 MHz ( period = 18.856 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold2[27] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.693 ns               ;
; -8.856 ns                               ; 53.03 MHz ( period = 18.856 ns )                    ; BSblock:ChrisBS|HugeCtr[6]                                                         ; BSblock:ChrisBS|ArbRampHold2[26] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.693 ns               ;
; -8.856 ns                               ; 53.03 MHz ( period = 18.856 ns )                    ; BSblock:ChrisBS|HugeCtr[13]                                                        ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.693 ns               ;
; -8.845 ns                               ; 53.06 MHz ( period = 18.845 ns )                    ; BSblock:ChrisBS|HugeCtr[8]                                                         ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.682 ns               ;
; -8.843 ns                               ; 53.07 MHz ( period = 18.843 ns )                    ; BSblock:ChrisBS|HugeCtr[1]                                                         ; BSblock:ChrisBS|ArbRampHold2[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.830 ns                  ; 18.673 ns               ;
; -8.842 ns                               ; 53.07 MHz ( period = 18.842 ns )                    ; BSblock:ChrisBS|HugeCtr[12]                                                        ; BSblock:ChrisBS|ArbRampHold1[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.830 ns                  ; 18.672 ns               ;
; -8.833 ns                               ; 53.10 MHz ( period = 18.833 ns )                    ; BSblock:ChrisBS|HugeCtr[9]                                                         ; BSblock:ChrisBS|ArbRampHold1[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.670 ns               ;
; -8.825 ns                               ; 53.12 MHz ( period = 18.825 ns )                    ; BSblock:ChrisBS|HugeCtr[7]                                                         ; BSblock:ChrisBS|ArbRampHold2[30] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.662 ns               ;
; -8.810 ns                               ; 53.16 MHz ( period = 18.810 ns )                    ; BSblock:ChrisBS|HugeCtr[10]                                                        ; BSblock:ChrisBS|ArbRampHold1[31] ; Clk        ; Clk      ; 10.000 ns                   ; 9.837 ns                  ; 18.647 ns               ;
; Timing analysis restricted to 100 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                    ;                                  ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'Clk'                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                           ; From                                                ; To                                                                                                                 ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; 0.633 ns                                ; BS2:ADChandler|CurrentPort[2]                       ; BS2:ADChandler|CurrentPort[2]                                                                                      ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.472 ns                 ;
; 0.633 ns                                ; BSblock:ChrisBS|sinPtr1[5]                          ; BSblock:ChrisBS|sinPtr1[5]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.472 ns                 ;
; 0.633 ns                                ; BSblock:ChrisBS|sinPtr1[4]                          ; BSblock:ChrisBS|sinPtr1[4]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.472 ns                 ;
; 0.633 ns                                ; BSblock:ChrisBS|sinPtr1[2]                          ; BSblock:ChrisBS|sinPtr1[2]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.472 ns                 ;
; 0.633 ns                                ; BSblock:ChrisBS|sinPtr1[0]                          ; BSblock:ChrisBS|sinPtr1[0]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.472 ns                 ;
; 0.799 ns                                ; BSblock:ChrisBS|ADCClk                              ; BSblock:ChrisBS|ADCClk                                                                                             ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.638 ns                 ;
; 0.805 ns                                ; BS2:ADChandler|ADCsClk                              ; BS2:ADChandler|ADCsClk                                                                                             ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.644 ns                 ;
; 0.810 ns                                ; BSblock:ChrisBS|PhaseOffset[1]                      ; BSblock:ChrisBS|sinPtr2[7]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.649 ns                 ;
; 0.831 ns                                ; BS2:ADChandler|CurrentPort[1]                       ; BS2:ADChandler|CurrentPort[1]                                                                                      ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.670 ns                 ;
; 0.834 ns                                ; BS2:ADChandler|CurrentPort[1]                       ; BS2:ADChandler|CurrentPort[2]                                                                                      ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.673 ns                 ;
; 0.941 ns                                ; BSblock:ChrisBS|WriteTOP                            ; BSblock:ChrisBS|WriteTOP                                                                                           ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.780 ns                 ;
; 0.942 ns                                ; BSblock:ChrisBS|sinPtr2[5]                          ; BSblock:ChrisBS|DACsAddHolder[3]                                                                                   ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.781 ns                 ;
; 0.944 ns                                ; BSSlow:inst|DACsSync                                ; BSSlow:inst|DACsSync                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.783 ns                 ;
; 0.945 ns                                ; BSblock:ChrisBS|sinPtr2[4]                          ; BSblock:ChrisBS|DACsAddHolder[4]                                                                                   ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.784 ns                 ;
; 0.950 ns                                ; BS2:ADChandler|ADCsCS                               ; BS2:ADChandler|ADCsCS                                                                                              ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.789 ns                 ;
; 0.964 ns                                ; BSblock:ChrisBS|sinPtr1[3]                          ; BSblock:ChrisBS|sinPtr1[3]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.803 ns                 ;
; 0.985 ns                                ; BS2:ADChandler|CurrentPort[0]                       ; BS2:ADChandler|CurrentPort[0]                                                                                      ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.824 ns                 ;
; 0.987 ns                                ; BS2:ADChandler|CurrentPort[0]                       ; BS2:ADChandler|CurrentPort[1]                                                                                      ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.826 ns                 ;
; 1.010 ns                                ; BSblock:ChrisBS|DACsCommand[1]                      ; BSblock:ChrisBS|DACsCommand[1]                                                                                     ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.849 ns                 ;
; 1.016 ns                                ; BSblock:ChrisBS|sinPtr2[6]                          ; BSblock:ChrisBS|DACsAddHolder[2]                                                                                   ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.855 ns                 ;
; 1.018 ns                                ; BS2:ADChandler|Ct[4]                                ; BS2:ADChandler|Ct[4]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.857 ns                 ;
; 1.018 ns                                ; BS2:ADChandler|Ct[8]                                ; BS2:ADChandler|Ct[8]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.857 ns                 ;
; 1.019 ns                                ; BSblock:ChrisBS|sinPtr1[7]                          ; BSblock:ChrisBS|sinPtr1[7]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.858 ns                 ;
; 1.020 ns                                ; BS2:ADChandler|Ct[5]                                ; BS2:ADChandler|Ct[5]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.859 ns                 ;
; 1.020 ns                                ; BS2:ADChandler|Ct[0]                                ; BS2:ADChandler|Ct[0]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.859 ns                 ;
; 1.021 ns                                ; BSblock:ChrisBS|DACsAddress[0]                      ; BSblock:ChrisBS|DACsAddress[0]                                                                                     ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.860 ns                 ;
; 1.022 ns                                ; BSblock:ChrisBS|sinCtr[4]                           ; BSblock:ChrisBS|sinCtr[4]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.861 ns                 ;
; 1.023 ns                                ; BSblock:ChrisBS|DACsAddress[1]                      ; BSblock:ChrisBS|DACsAddress[1]                                                                                     ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.862 ns                 ;
; 1.023 ns                                ; BS2:ADChandler|Ct[3]                                ; BS2:ADChandler|Ct[3]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.862 ns                 ;
; 1.025 ns                                ; BSblock:ChrisBS|sinPtr2[8]                          ; BSblock:ChrisBS|DACsAddHolder[0]                                                                                   ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.864 ns                 ;
; 1.025 ns                                ; BSblock:ChrisBS|sinPtr2[2]                          ; BSblock:ChrisBS|DACsAddHolder[6]                                                                                   ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.864 ns                 ;
; 1.029 ns                                ; BSblock:ChrisBS|sinCtr[0]                           ; BSblock:ChrisBS|sinCtr[0]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.868 ns                 ;
; 1.032 ns                                ; BSblock:ChrisBS|sinCtr[3]                           ; BSblock:ChrisBS|sinCtr[3]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.871 ns                 ;
; 1.059 ns                                ; BS2:ADChandler|CurrentPort[0]                       ; BS2:ADChandler|CurrentPort[2]                                                                                      ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.898 ns                 ;
; 1.135 ns                                ; BSblock:ChrisBS|sinPtr2[3]                          ; BSblock:ChrisBS|DACsAddHolder[5]                                                                                   ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.974 ns                 ;
; 1.138 ns                                ; BSblock:ChrisBS|Arb2Prog[14]                        ; lpm_ram_dq3:Black2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a0~porta_datain_reg4   ; Clk        ; Clk      ; 0.000 ns                   ; -0.089 ns                  ; 1.049 ns                 ;
; 1.139 ns                                ; BSblock:ChrisBS|sinCtr[7]                           ; BSblock:ChrisBS|sinCtr[7]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.978 ns                 ;
; 1.141 ns                                ; BSblock:ChrisBS|sinCtr[1]                           ; BSblock:ChrisBS|sinCtr[1]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.980 ns                 ;
; 1.145 ns                                ; BSblock:ChrisBS|sinCtr[2]                           ; BSblock:ChrisBS|sinCtr[2]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 0.984 ns                 ;
; 1.156 ns                                ; BSblock:ChrisBS|HugeCtr[30]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a7~porta_address_reg7  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.035 ns                 ;
; 1.157 ns                                ; BSblock:ChrisBS|HugeCtr[27]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a7~porta_address_reg4  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.036 ns                 ;
; 1.173 ns                                ; BSblock:ChrisBS|HugeCtr[29]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a7~porta_address_reg6  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.052 ns                 ;
; 1.175 ns                                ; BSblock:ChrisBS|HugeCtr[24]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a7~porta_address_reg1  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.054 ns                 ;
; 1.189 ns                                ; BS2:ADChandler|Ct[1]                                ; BS2:ADChandler|Ct[1]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.028 ns                 ;
; 1.191 ns                                ; BSblock:ChrisBS|sinPtr2[7]                          ; BSblock:ChrisBS|DACsAddHolder[1]                                                                                   ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.030 ns                 ;
; 1.201 ns                                ; BS2:ADChandler|Ct[6]                                ; BS2:ADChandler|Ct[6]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.040 ns                 ;
; 1.210 ns                                ; BSblock:ChrisBS|sinCtr[6]                           ; BSblock:ChrisBS|sinCtr[6]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.049 ns                 ;
; 1.219 ns                                ; BSblock:ChrisBS|PhaseOffset[4]                      ; BSblock:ChrisBS|sinPtr2[4]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.058 ns                 ;
; 1.230 ns                                ; BSblock:ChrisBS|PhaseOffset[7]                      ; BSblock:ChrisBS|sinPtr2[1]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.069 ns                 ;
; 1.242 ns                                ; BSblock:ChrisBS|sinPtr1[1]                          ; BSblock:ChrisBS|sinPtr1[1]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.081 ns                 ;
; 1.349 ns                                ; BSblock:ChrisBS|sinCtr[5]                           ; BSblock:ChrisBS|sinCtr[5]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.188 ns                 ;
; 1.455 ns                                ; BSblock:ChrisBS|PhaseOffset[2]                      ; BSblock:ChrisBS|sinPtr2[6]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.294 ns                 ;
; 1.457 ns                                ; BSblock:ChrisBS|HugeCtr[1]                          ; BSblock:ChrisBS|HugeCtr[1]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.296 ns                 ;
; 1.471 ns                                ; BSSlow:inst|Ctr[10]                                 ; BSSlow:inst|Ctr[10]                                                                                                ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.310 ns                 ;
; 1.480 ns                                ; BS2:ADChandler|Ct[8]                                ; BS2:ADChandler|Ct[9]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.319 ns                 ;
; 1.482 ns                                ; BS2:ADChandler|Ct[5]                                ; BS2:ADChandler|Ct[6]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.321 ns                 ;
; 1.482 ns                                ; BS2:ADChandler|Ct[0]                                ; BS2:ADChandler|Ct[1]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.321 ns                 ;
; 1.482 ns                                ; BSblock:ChrisBS|Arb2Prog[8]                         ; lpm_ram_dq3:Black2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a0~porta_datain_reg8   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.361 ns                 ;
; 1.483 ns                                ; BSblock:ChrisBS|Arb1Prog[2]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_datain_reg6   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.362 ns                 ;
; 1.483 ns                                ; BSblock:ChrisBS|Arb2Prog[0]                         ; lpm_ram_dq4:Silver2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a5~porta_datain_reg4  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.362 ns                 ;
; 1.485 ns                                ; BS2:ADChandler|Ct[3]                                ; BS2:ADChandler|Ct[4]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.324 ns                 ;
; 1.491 ns                                ; BSblock:ChrisBS|sinCtr[0]                           ; BSblock:ChrisBS|sinCtr[1]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.330 ns                 ;
; 1.493 ns                                ; BSblock:ChrisBS|Arb1Prog[13]                        ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_datain_reg0   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.372 ns                 ;
; 1.493 ns                                ; BSblock:ChrisBS|Arb2Prog[13]                        ; lpm_ram_dq3:Black2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a0~porta_datain_reg3   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.372 ns                 ;
; 1.494 ns                                ; BSblock:ChrisBS|sinCtr[3]                           ; BSblock:ChrisBS|sinCtr[4]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.333 ns                 ;
; 1.494 ns                                ; BSblock:ChrisBS|Arb2Prog[2]                         ; lpm_ram_dq4:Silver2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a5~porta_datain_reg3  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.373 ns                 ;
; 1.495 ns                                ; BSblock:ChrisBS|Arb1Prog[15]                        ; lpm_ram_dq3:Black2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a1~porta_datain_reg8   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.374 ns                 ;
; 1.496 ns                                ; BSblock:ChrisBS|Arb2Prog[1]                         ; lpm_ram_dq4:Silver2|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a5~porta_datain_reg2  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.375 ns                 ;
; 1.497 ns                                ; BS2:ADChandler|Ct[7]                                ; BS2:ADChandler|Ct[7]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.336 ns                 ;
; 1.501 ns                                ; BSblock:ChrisBS|Arb1Prog[4]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_datain_reg7   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.380 ns                 ;
; 1.506 ns                                ; BSblock:ChrisBS|HugeCtr[28]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_address_reg5  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.385 ns                 ;
; 1.513 ns                                ; BSblock:ChrisBS|HugeCtr[27]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a5~porta_address_reg4   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.392 ns                 ;
; 1.515 ns                                ; BSblock:ChrisBS|Arb1Prog[0]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_datain_reg8   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.394 ns                 ;
; 1.520 ns                                ; BSblock:ChrisBS|sinPtr2[1]                          ; BSblock:ChrisBS|DACsAddHolder[7]                                                                                   ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.359 ns                 ;
; 1.531 ns                                ; BSblock:ChrisBS|HugeCtr[25]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a7~porta_address_reg2  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.410 ns                 ;
; 1.535 ns                                ; BSblock:ChrisBS|HugeCtr[26]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_address_reg3  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.414 ns                 ;
; 1.537 ns                                ; BSblock:ChrisBS|HugeCtr[24]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a5~porta_address_reg1   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.416 ns                 ;
; 1.542 ns                                ; BS2:ADChandler|Ct[5]                                ; BS2:ADChandler|Ct[7]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.381 ns                 ;
; 1.542 ns                                ; BS2:ADChandler|Ct[0]                                ; BS2:ADChandler|Ct[2]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.381 ns                 ;
; 1.543 ns                                ; BSblock:ChrisBS|HugeCtr[23]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a7~porta_address_reg0  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.422 ns                 ;
; 1.544 ns                                ; BSSlow:inst|Ctr[11]                                 ; BSSlow:inst|Ctr[0]                                                                                                 ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.383 ns                 ;
; 1.550 ns                                ; BSblock:ChrisBS|HugeCtr[25]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a5~porta_address_reg2   ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.429 ns                 ;
; 1.551 ns                                ; BSblock:ChrisBS|sinCtr[0]                           ; BSblock:ChrisBS|sinCtr[2]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.390 ns                 ;
; 1.558 ns                                ; BS2:ADChandler|ADCsSDI                              ; BS2:ADChandler|ADCsSDI                                                                                             ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.397 ns                 ;
; 1.576 ns                                ; BSblock:ChrisBS|HugeCtr[30]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a14~porta_address_reg7 ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.455 ns                 ;
; 1.578 ns                                ; BS2:ADChandler|Ct[2]                                ; BS2:ADChandler|Ct[2]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.417 ns                 ;
; 1.579 ns                                ; BSblock:ChrisBS|HugeCtr[29]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a14~porta_address_reg6 ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.458 ns                 ;
; 1.581 ns                                ; BSblock:ChrisBS|HugeCtr[25]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_address_reg2  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.460 ns                 ;
; 1.584 ns                                ; BSblock:ChrisBS|HugeCtr[29]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_address_reg6  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.463 ns                 ;
; 1.593 ns                                ; BSblock:ChrisBS|HugeCtr[30]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_address_reg7  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.472 ns                 ;
; 1.593 ns                                ; BSblock:ChrisBS|HugeCtr[27]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a14~porta_address_reg4 ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.472 ns                 ;
; 1.594 ns                                ; BSblock:ChrisBS|HugeCtr[25]                         ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a14~porta_address_reg2 ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.473 ns                 ;
; 1.602 ns                                ; BS2:ADChandler|Ct[5]                                ; BS2:ADChandler|Ct[8]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.441 ns                 ;
; 1.602 ns                                ; BS2:ADChandler|Ct[0]                                ; BS2:ADChandler|Ct[3]                                                                                               ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.441 ns                 ;
; 1.602 ns                                ; BSblock:ChrisBS|HugeCtr[27]                         ; lpm_ram_dq3:Black|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a13~porta_address_reg4  ; Clk        ; Clk      ; 0.000 ns                   ; -0.121 ns                  ; 1.481 ns                 ;
; 1.602 ns                                ; BSblock:ChrisBS|HugeCtr[5]                          ; BSblock:ChrisBS|HugeCtr[5]                                                                                         ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.441 ns                 ;
; 1.610 ns                                ; BSblock:ChrisBS|sinCtr[1]                           ; BSblock:ChrisBS|sinCtr[2]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.449 ns                 ;
; 1.611 ns                                ; BSblock:ChrisBS|sinCtr[0]                           ; BSblock:ChrisBS|sinCtr[3]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.450 ns                 ;
; 1.614 ns                                ; BSblock:ChrisBS|sinCtr[2]                           ; BSblock:ChrisBS|sinCtr[3]                                                                                          ; Clk        ; Clk      ; 0.000 ns                   ; -0.161 ns                  ; 1.453 ns                 ;
; 1.623 ns                                ; BSblock:ChrisBS|Arb2Prog[14]                        ; lpm_ram_dq4:Silver|altsyncram:altsyncram_component|altsyncram_9731:auto_generated|ram_block1a14~porta_datain_reg0  ; Clk        ; Clk      ; 0.000 ns                   ; -0.089 ns                  ; 1.534 ns                 ;
; Timing analysis restricted to 100 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                    ;            ;          ;                            ;                            ;                          ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+------------+---------+----------------------------------+----------+
; Slack                                   ; Required tsu                                        ; Actual tsu ; From    ; To                               ; To Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+---------+----------------------------------+----------+
; N/A                                     ; None                                                ; 13.690 ns  ; USB[14] ; BSSlow:inst|DACsData             ; Clk      ;
; N/A                                     ; None                                                ; 13.545 ns  ; USB[13] ; BSSlow:inst|DACsData             ; Clk      ;
; N/A                                     ; None                                                ; 13.115 ns  ; USB[15] ; BSSlow:inst|DACsData             ; Clk      ;
; N/A                                     ; None                                                ; 13.064 ns  ; USB[12] ; BSSlow:inst|DACsData             ; Clk      ;
; N/A                                     ; None                                                ; 10.440 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[4]  ; Clk      ;
; N/A                                     ; None                                                ; 10.440 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[6]  ; Clk      ;
; N/A                                     ; None                                                ; 10.399 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[12] ; Clk      ;
; N/A                                     ; None                                                ; 10.399 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[9]  ; Clk      ;
; N/A                                     ; None                                                ; 10.399 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[11] ; Clk      ;
; N/A                                     ; None                                                ; 10.399 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[8]  ; Clk      ;
; N/A                                     ; None                                                ; 10.399 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[14] ; Clk      ;
; N/A                                     ; None                                                ; 10.387 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[5]  ; Clk      ;
; N/A                                     ; None                                                ; 10.387 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[15] ; Clk      ;
; N/A                                     ; None                                                ; 10.387 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[13] ; Clk      ;
; N/A                                     ; None                                                ; 10.387 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[10] ; Clk      ;
; N/A                                     ; None                                                ; 10.387 ns  ; USB[14] ; BSblock:ChrisBS|DACsDWHolder[7]  ; Clk      ;
; N/A                                     ; None                                                ; 9.998 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[10]     ; Clk      ;
; N/A                                     ; None                                                ; 9.961 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[14]     ; Clk      ;
; N/A                                     ; None                                                ; 9.942 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[5]       ; Clk      ;
; N/A                                     ; None                                                ; 9.942 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[0]       ; Clk      ;
; N/A                                     ; None                                                ; 9.942 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[3]       ; Clk      ;
; N/A                                     ; None                                                ; 9.918 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[18]      ; Clk      ;
; N/A                                     ; None                                                ; 9.853 ns   ; USB[13] ; BSblock:ChrisBS|Arb2Prog[10]     ; Clk      ;
; N/A                                     ; None                                                ; 9.816 ns   ; USB[13] ; BSblock:ChrisBS|Arb2Prog[14]     ; Clk      ;
; N/A                                     ; None                                                ; 9.803 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[4]  ; Clk      ;
; N/A                                     ; None                                                ; 9.803 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[6]  ; Clk      ;
; N/A                                     ; None                                                ; 9.797 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[5]       ; Clk      ;
; N/A                                     ; None                                                ; 9.797 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[0]       ; Clk      ;
; N/A                                     ; None                                                ; 9.797 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[3]       ; Clk      ;
; N/A                                     ; None                                                ; 9.773 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[18]      ; Clk      ;
; N/A                                     ; None                                                ; 9.762 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[12] ; Clk      ;
; N/A                                     ; None                                                ; 9.762 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[9]  ; Clk      ;
; N/A                                     ; None                                                ; 9.762 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[11] ; Clk      ;
; N/A                                     ; None                                                ; 9.762 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[8]  ; Clk      ;
; N/A                                     ; None                                                ; 9.762 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[14] ; Clk      ;
; N/A                                     ; None                                                ; 9.750 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[5]  ; Clk      ;
; N/A                                     ; None                                                ; 9.750 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[15] ; Clk      ;
; N/A                                     ; None                                                ; 9.750 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[13] ; Clk      ;
; N/A                                     ; None                                                ; 9.750 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[10] ; Clk      ;
; N/A                                     ; None                                                ; 9.750 ns   ; USB[13] ; BSblock:ChrisBS|DACsDWHolder[7]  ; Clk      ;
; N/A                                     ; None                                                ; 9.740 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[21]      ; Clk      ;
; N/A                                     ; None                                                ; 9.740 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[16]      ; Clk      ;
; N/A                                     ; None                                                ; 9.740 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[22]      ; Clk      ;
; N/A                                     ; None                                                ; 9.740 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[20]      ; Clk      ;
; N/A                                     ; None                                                ; 9.740 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[19]      ; Clk      ;
; N/A                                     ; None                                                ; 9.740 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[17]      ; Clk      ;
; N/A                                     ; None                                                ; 9.736 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[12]      ; Clk      ;
; N/A                                     ; None                                                ; 9.736 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[4]       ; Clk      ;
; N/A                                     ; None                                                ; 9.736 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[2]       ; Clk      ;
; N/A                                     ; None                                                ; 9.736 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[1]       ; Clk      ;
; N/A                                     ; None                                                ; 9.712 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[7]       ; Clk      ;
; N/A                                     ; None                                                ; 9.712 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[6]       ; Clk      ;
; N/A                                     ; None                                                ; 9.688 ns   ; USB[14] ; BSblock:ChrisBS|Dig[7]           ; Clk      ;
; N/A                                     ; None                                                ; 9.639 ns   ; USB[14] ; BSblock:ChrisBS|HugeCtr[8]       ; Clk      ;
; N/A                                     ; None                                                ; 9.620 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[4]  ; Clk      ;
; N/A                                     ; None                                                ; 9.620 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[6]  ; Clk      ;
; N/A                                     ; None                                                ; 9.595 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[21]      ; Clk      ;
; N/A                                     ; None                                                ; 9.595 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[16]      ; Clk      ;
; N/A                                     ; None                                                ; 9.595 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[22]      ; Clk      ;
; N/A                                     ; None                                                ; 9.595 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[20]      ; Clk      ;
; N/A                                     ; None                                                ; 9.595 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[19]      ; Clk      ;
; N/A                                     ; None                                                ; 9.595 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[17]      ; Clk      ;
; N/A                                     ; None                                                ; 9.591 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[12]      ; Clk      ;
; N/A                                     ; None                                                ; 9.591 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[4]       ; Clk      ;
; N/A                                     ; None                                                ; 9.591 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[2]       ; Clk      ;
; N/A                                     ; None                                                ; 9.591 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[1]       ; Clk      ;
; N/A                                     ; None                                                ; 9.579 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[12] ; Clk      ;
; N/A                                     ; None                                                ; 9.579 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[9]  ; Clk      ;
; N/A                                     ; None                                                ; 9.579 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[11] ; Clk      ;
; N/A                                     ; None                                                ; 9.579 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[8]  ; Clk      ;
; N/A                                     ; None                                                ; 9.579 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[14] ; Clk      ;
; N/A                                     ; None                                                ; 9.567 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[5]  ; Clk      ;
; N/A                                     ; None                                                ; 9.567 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[15] ; Clk      ;
; N/A                                     ; None                                                ; 9.567 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[13] ; Clk      ;
; N/A                                     ; None                                                ; 9.567 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[10] ; Clk      ;
; N/A                                     ; None                                                ; 9.567 ns   ; USB[15] ; BSblock:ChrisBS|DACsDWHolder[7]  ; Clk      ;
; N/A                                     ; None                                                ; 9.567 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[7]       ; Clk      ;
; N/A                                     ; None                                                ; 9.567 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[6]       ; Clk      ;
; N/A                                     ; None                                                ; 9.543 ns   ; USB[13] ; BSblock:ChrisBS|Dig[7]           ; Clk      ;
; N/A                                     ; None                                                ; 9.494 ns   ; USB[13] ; BSblock:ChrisBS|HugeCtr[8]       ; Clk      ;
; N/A                                     ; None                                                ; 9.461 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[13]     ; Clk      ;
; N/A                                     ; None                                                ; 9.461 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[11]     ; Clk      ;
; N/A                                     ; None                                                ; 9.461 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[9]      ; Clk      ;
; N/A                                     ; None                                                ; 9.461 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[8]      ; Clk      ;
; N/A                                     ; None                                                ; 9.457 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[6]      ; Clk      ;
; N/A                                     ; None                                                ; 9.457 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[5]      ; Clk      ;
; N/A                                     ; None                                                ; 9.424 ns   ; USB[15] ; BSblock:ChrisBS|Arb2Prog[10]     ; Clk      ;
; N/A                                     ; None                                                ; 9.387 ns   ; USB[15] ; BSblock:ChrisBS|Arb2Prog[14]     ; Clk      ;
; N/A                                     ; None                                                ; 9.373 ns   ; USB[12] ; BSblock:ChrisBS|Arb2Prog[10]     ; Clk      ;
; N/A                                     ; None                                                ; 9.367 ns   ; USB[15] ; BSblock:ChrisBS|HugeCtr[5]       ; Clk      ;
; N/A                                     ; None                                                ; 9.367 ns   ; USB[15] ; BSblock:ChrisBS|HugeCtr[0]       ; Clk      ;
; N/A                                     ; None                                                ; 9.367 ns   ; USB[15] ; BSblock:ChrisBS|HugeCtr[3]       ; Clk      ;
; N/A                                     ; None                                                ; 9.359 ns   ; USB[14] ; BSblock:ChrisBS|DACsAddHolder[0] ; Clk      ;
; N/A                                     ; None                                                ; 9.359 ns   ; USB[14] ; BSblock:ChrisBS|DACsAddHolder[3] ; Clk      ;
; N/A                                     ; None                                                ; 9.359 ns   ; USB[14] ; BSblock:ChrisBS|DACsAddHolder[6] ; Clk      ;
; N/A                                     ; None                                                ; 9.359 ns   ; USB[14] ; BSblock:ChrisBS|DACsAddHolder[7] ; Clk      ;
; N/A                                     ; None                                                ; 9.354 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[4]      ; Clk      ;
; N/A                                     ; None                                                ; 9.354 ns   ; USB[14] ; BSblock:ChrisBS|Arb2Prog[3]      ; Clk      ;
; N/A                                     ; None                                                ; 9.343 ns   ; USB[15] ; BSblock:ChrisBS|HugeCtr[18]      ; Clk      ;
; N/A                                     ; None                                                ; 9.336 ns   ; USB[12] ; BSblock:ChrisBS|DACsAddHolder[0] ; Clk      ;
; Timing analysis restricted to 100 rows. ; To change the limit use Settings (Assignments menu) ;            ;         ;                                  ;          ;
+-----------------------------------------+-----------------------------------------------------+------------+---------+----------------------------------+----------+


+----------------------------------------------------------------------------------------+
; tco                                                                                    ;
+-------+--------------+------------+----------------------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From                       ; To       ; From Clock ;
+-------+--------------+------------+----------------------------+----------+------------+
; N/A   ; None         ; 10.213 ns  ; BS2:ADChandler|ADCsCS      ; ADCsCS   ; Clk        ;
; N/A   ; None         ; 9.841 ns   ; BS2:ADChandler|ADCsClk     ; ADCsClk  ; Clk        ;
; N/A   ; None         ; 9.378 ns   ; BS2:ADChandler|ADCsSDI     ; ADCsSDI  ; Clk        ;
; N/A   ; None         ; 7.656 ns   ; BSblock:ChrisBS|Dig[7]     ; Dig[7]   ; Clk        ;
; N/A   ; None         ; 6.989 ns   ; BSSlow:inst|DACsData       ; DACsData ; Clk        ;
; N/A   ; None         ; 6.395 ns   ; BSSlow:inst|DACsSync       ; DACsSync ; Clk        ;
; N/A   ; None         ; 5.455 ns   ; BSblock:ChrisBS|DataOut[7] ; USB[7]   ; Clk        ;
; N/A   ; None         ; 5.448 ns   ; BSblock:ChrisBS|DataOut[5] ; USB[5]   ; Clk        ;
; N/A   ; None         ; 5.442 ns   ; BSblock:ChrisBS|DataOut[6] ; USB[6]   ; Clk        ;
; N/A   ; None         ; 5.194 ns   ; BSblock:ChrisBS|DataOut[4] ; USB[4]   ; Clk        ;
; N/A   ; None         ; 5.177 ns   ; BSblock:ChrisBS|DataOut[3] ; USB[3]   ; Clk        ;
; N/A   ; None         ; 4.929 ns   ; BSblock:ChrisBS|DataOut[2] ; USB[2]   ; Clk        ;
; N/A   ; None         ; 4.926 ns   ; BSblock:ChrisBS|DataOut[1] ; USB[1]   ; Clk        ;
; N/A   ; None         ; 4.826 ns   ; BSblock:ChrisBS|DataOut[0] ; USB[0]   ; Clk        ;
+-------+--------------+------------+----------------------------+----------+------------+


+-----------------------------------------------------------------+
; tpd                                                             ;
+-------+-------------------+-----------------+---------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To      ;
+-------+-------------------+-----------------+---------+---------+
; N/A   ; None              ; 11.078 ns       ; USB[14] ; USB[0]  ;
; N/A   ; None              ; 10.983 ns       ; USB[14] ; USB[2]  ;
; N/A   ; None              ; 10.983 ns       ; USB[14] ; USB[1]  ;
; N/A   ; None              ; 10.930 ns       ; USB[13] ; USB[0]  ;
; N/A   ; None              ; 10.835 ns       ; USB[13] ; USB[2]  ;
; N/A   ; None              ; 10.835 ns       ; USB[13] ; USB[1]  ;
; N/A   ; None              ; 10.705 ns       ; USB[14] ; USB[4]  ;
; N/A   ; None              ; 10.705 ns       ; USB[14] ; USB[3]  ;
; N/A   ; None              ; 10.557 ns       ; USB[13] ; USB[4]  ;
; N/A   ; None              ; 10.557 ns       ; USB[13] ; USB[3]  ;
; N/A   ; None              ; 10.501 ns       ; USB[15] ; USB[0]  ;
; N/A   ; None              ; 10.450 ns       ; USB[12] ; USB[0]  ;
; N/A   ; None              ; 10.406 ns       ; USB[15] ; USB[2]  ;
; N/A   ; None              ; 10.406 ns       ; USB[15] ; USB[1]  ;
; N/A   ; None              ; 10.355 ns       ; USB[12] ; USB[2]  ;
; N/A   ; None              ; 10.355 ns       ; USB[12] ; USB[1]  ;
; N/A   ; None              ; 10.128 ns       ; USB[15] ; USB[4]  ;
; N/A   ; None              ; 10.128 ns       ; USB[15] ; USB[3]  ;
; N/A   ; None              ; 10.077 ns       ; USB[12] ; USB[4]  ;
; N/A   ; None              ; 10.077 ns       ; USB[12] ; USB[3]  ;
; N/A   ; None              ; 9.556 ns        ; USB[14] ; USB[5]  ;
; N/A   ; None              ; 9.556 ns        ; USB[14] ; USB[6]  ;
; N/A   ; None              ; 9.546 ns        ; USB[14] ; USB[7]  ;
; N/A   ; None              ; 9.408 ns        ; USB[13] ; USB[5]  ;
; N/A   ; None              ; 9.408 ns        ; USB[13] ; USB[6]  ;
; N/A   ; None              ; 9.398 ns        ; USB[13] ; USB[7]  ;
; N/A   ; None              ; 8.979 ns        ; USB[15] ; USB[5]  ;
; N/A   ; None              ; 8.979 ns        ; USB[15] ; USB[6]  ;
; N/A   ; None              ; 8.969 ns        ; USB[15] ; USB[7]  ;
; N/A   ; None              ; 8.928 ns        ; USB[12] ; USB[5]  ;
; N/A   ; None              ; 8.928 ns        ; USB[12] ; USB[6]  ;
; N/A   ; None              ; 8.918 ns        ; USB[12] ; USB[7]  ;
; N/A   ; None              ; 3.839 ns        ; Clk     ; DACsClk ;
+-------+-------------------+-----------------+---------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-----------+---------+----------------------------------+----------+
; Minimum Slack                           ; Required th                                         ; Actual th ; From    ; To                               ; To Clock ;
+-----------------------------------------+-----------------------------------------------------+-----------+---------+----------------------------------+----------+
; N/A                                     ; None                                                ; -0.985 ns ; ADCsSDO ; BS2:ADChandler|Port8[1]          ; Clk      ;
; N/A                                     ; None                                                ; -1.577 ns ; ADCsSDO ; BS2:ADChandler|Port1[9]          ; Clk      ;
; N/A                                     ; None                                                ; -2.101 ns ; ADCsSDO ; BS2:ADChandler|Port8[6]          ; Clk      ;
; N/A                                     ; None                                                ; -2.101 ns ; ADCsSDO ; BS2:ADChandler|Port8[14]         ; Clk      ;
; N/A                                     ; None                                                ; -2.819 ns ; ADCsSDO ; BS2:ADChandler|Port1[15]         ; Clk      ;
; N/A                                     ; None                                                ; -2.938 ns ; ADCsSDO ; BS2:ADChandler|Port1[8]          ; Clk      ;
; N/A                                     ; None                                                ; -2.938 ns ; ADCsSDO ; BS2:ADChandler|Port8[0]          ; Clk      ;
; N/A                                     ; None                                                ; -2.942 ns ; ADCsSDO ; BS2:ADChandler|Port8[5]          ; Clk      ;
; N/A                                     ; None                                                ; -2.942 ns ; ADCsSDO ; BS2:ADChandler|Port1[10]         ; Clk      ;
; N/A                                     ; None                                                ; -3.008 ns ; USB[7]  ; BSblock:ChrisBS|PhaseOffset[7]   ; Clk      ;
; N/A                                     ; None                                                ; -3.158 ns ; ADCsSDO ; BS2:ADChandler|Port8[2]          ; Clk      ;
; N/A                                     ; None                                                ; -3.173 ns ; ADCsSDO ; BS2:ADChandler|Port8[13]         ; Clk      ;
; N/A                                     ; None                                                ; -3.174 ns ; ADCsSDO ; BS2:ADChandler|Port8[7]          ; Clk      ;
; N/A                                     ; None                                                ; -3.204 ns ; USB[5]  ; BSblock:ChrisBS|PhaseOffset[5]   ; Clk      ;
; N/A                                     ; None                                                ; -3.250 ns ; USB[6]  ; BSblock:ChrisBS|PhaseOffset[6]   ; Clk      ;
; N/A                                     ; None                                                ; -3.256 ns ; USB[3]  ; BSblock:ChrisBS|PhaseOffset[3]   ; Clk      ;
; N/A                                     ; None                                                ; -3.462 ns ; USB[2]  ; BSblock:ChrisBS|PhaseOffset[2]   ; Clk      ;
; N/A                                     ; None                                                ; -3.518 ns ; ADCsSDO ; BS2:ADChandler|Port8[4]          ; Clk      ;
; N/A                                     ; None                                                ; -3.519 ns ; ADCsSDO ; BS2:ADChandler|Port1[12]         ; Clk      ;
; N/A                                     ; None                                                ; -3.545 ns ; ADCsSDO ; BS2:ADChandler|Port8[10]         ; Clk      ;
; N/A                                     ; None                                                ; -3.546 ns ; ADCsSDO ; BS2:ADChandler|Port8[12]         ; Clk      ;
; N/A                                     ; None                                                ; -3.562 ns ; USB[0]  ; BSblock:ChrisBS|PhaseOffset[0]   ; Clk      ;
; N/A                                     ; None                                                ; -3.585 ns ; USB[7]  ; BSblock:ChrisBS|Arb1Prog[7]      ; Clk      ;
; N/A                                     ; None                                                ; -3.607 ns ; USB[5]  ; BSblock:ChrisBS|Arb1Prog[13]     ; Clk      ;
; N/A                                     ; None                                                ; -3.609 ns ; USB[5]  ; BSblock:ChrisBS|Arb1Prog[5]      ; Clk      ;
; N/A                                     ; None                                                ; -3.767 ns ; USB[9]  ; BSblock:ChrisBS|WriteTOP         ; Clk      ;
; N/A                                     ; None                                                ; -3.821 ns ; USB[1]  ; BSblock:ChrisBS|DACsDWHolder[5]  ; Clk      ;
; N/A                                     ; None                                                ; -3.851 ns ; USB[5]  ; BSblock:ChrisBS|HugeCtr[28]      ; Clk      ;
; N/A                                     ; None                                                ; -3.886 ns ; USB[4]  ; BSblock:ChrisBS|DACsDWHolder[8]  ; Clk      ;
; N/A                                     ; None                                                ; -3.895 ns ; USB[3]  ; BSblock:ChrisBS|DACsDWHolder[7]  ; Clk      ;
; N/A                                     ; None                                                ; -3.899 ns ; USB[6]  ; BSblock:ChrisBS|HugeCtr[29]      ; Clk      ;
; N/A                                     ; None                                                ; -3.915 ns ; USB[4]  ; BSblock:ChrisBS|PhaseOffset[4]   ; Clk      ;
; N/A                                     ; None                                                ; -3.947 ns ; USB[4]  ; BSblock:ChrisBS|HugeCtr[27]      ; Clk      ;
; N/A                                     ; None                                                ; -3.955 ns ; USB[7]  ; BSblock:ChrisBS|DACsDWHolder[11] ; Clk      ;
; N/A                                     ; None                                                ; -3.957 ns ; USB[0]  ; BSblock:ChrisBS|DACsDWHolder[4]  ; Clk      ;
; N/A                                     ; None                                                ; -3.992 ns ; USB[7]  ; BSblock:ChrisBS|Arb2Prog[15]     ; Clk      ;
; N/A                                     ; None                                                ; -4.001 ns ; USB[13] ; BSblock:ChrisBS|HugeCtr[30]      ; Clk      ;
; N/A                                     ; None                                                ; -4.002 ns ; USB[13] ; BSblock:ChrisBS|HugeCtr[24]      ; Clk      ;
; N/A                                     ; None                                                ; -4.002 ns ; USB[13] ; BSblock:ChrisBS|HugeCtr[25]      ; Clk      ;
; N/A                                     ; None                                                ; -4.003 ns ; USB[13] ; BSblock:ChrisBS|HugeCtr[23]      ; Clk      ;
; N/A                                     ; None                                                ; -4.004 ns ; USB[13] ; BSblock:ChrisBS|HugeCtr[27]      ; Clk      ;
; N/A                                     ; None                                                ; -4.005 ns ; USB[13] ; BSblock:ChrisBS|HugeCtr[29]      ; Clk      ;
; N/A                                     ; None                                                ; -4.007 ns ; USB[3]  ; BSblock:ChrisBS|HugeCtr[26]      ; Clk      ;
; N/A                                     ; None                                                ; -4.123 ns ; USB[2]  ; BSblock:ChrisBS|Arb1Prog[2]      ; Clk      ;
; N/A                                     ; None                                                ; -4.135 ns ; USB[1]  ; BSblock:ChrisBS|Arb2Prog[9]      ; Clk      ;
; N/A                                     ; None                                                ; -4.136 ns ; USB[1]  ; BSblock:ChrisBS|Arb1Prog[9]      ; Clk      ;
; N/A                                     ; None                                                ; -4.142 ns ; USB[6]  ; BSblock:ChrisBS|Arb2Prog[14]     ; Clk      ;
; N/A                                     ; None                                                ; -4.151 ns ; USB[1]  ; BSblock:ChrisBS|Arb1Prog[1]      ; Clk      ;
; N/A                                     ; None                                                ; -4.180 ns ; USB[3]  ; BSblock:ChrisBS|Arb1Prog[3]      ; Clk      ;
; N/A                                     ; None                                                ; -4.211 ns ; USB[3]  ; BSblock:ChrisBS|Arb2Prog[11]     ; Clk      ;
; N/A                                     ; None                                                ; -4.212 ns ; USB[3]  ; BSblock:ChrisBS|Arb1Prog[11]     ; Clk      ;
; N/A                                     ; None                                                ; -4.223 ns ; USB[1]  ; BSblock:ChrisBS|HugeCtr[24]      ; Clk      ;
; N/A                                     ; None                                                ; -4.250 ns ; USB[2]  ; BSblock:ChrisBS|HugeCtr[25]      ; Clk      ;
; N/A                                     ; None                                                ; -4.273 ns ; ADCsSDO ; BS2:ADChandler|Port1[11]         ; Clk      ;
; N/A                                     ; None                                                ; -4.274 ns ; ADCsSDO ; BS2:ADChandler|Port8[3]          ; Clk      ;
; N/A                                     ; None                                                ; -4.279 ns ; USB[0]  ; BSblock:ChrisBS|HugeCtr[23]      ; Clk      ;
; N/A                                     ; None                                                ; -4.282 ns ; USB[2]  ; BSblock:ChrisBS|DACsDWHolder[6]  ; Clk      ;
; N/A                                     ; None                                                ; -4.307 ns ; USB[4]  ; BSblock:ChrisBS|Arb2Prog[4]      ; Clk      ;
; N/A                                     ; None                                                ; -4.315 ns ; ADCsSDO ; BS2:ADChandler|Port1[3]          ; Clk      ;
; N/A                                     ; None                                                ; -4.317 ns ; ADCsSDO ; BS2:ADChandler|Port8[9]          ; Clk      ;
; N/A                                     ; None                                                ; -4.321 ns ; USB[5]  ; BSblock:ChrisBS|Arb2Prog[13]     ; Clk      ;
; N/A                                     ; None                                                ; -4.426 ns ; USB[7]  ; BSblock:ChrisBS|HugeCtr[30]      ; Clk      ;
; N/A                                     ; None                                                ; -4.439 ns ; USB[9]  ; BSblock:ChrisBS|DACsDWHolder[13] ; Clk      ;
; N/A                                     ; None                                                ; -4.459 ns ; USB[6]  ; BSblock:ChrisBS|Arb1Prog[6]      ; Clk      ;
; N/A                                     ; None                                                ; -4.464 ns ; USB[6]  ; BSblock:ChrisBS|Arb1Prog[14]     ; Clk      ;
; N/A                                     ; None                                                ; -4.473 ns ; USB[13] ; BSblock:ChrisBS|DACsTrigger      ; Clk      ;
; N/A                                     ; None                                                ; -4.474 ns ; ADCsSDO ; BS2:ADChandler|Port8[15]         ; Clk      ;
; N/A                                     ; None                                                ; -4.476 ns ; ADCsSDO ; BS2:ADChandler|Port8[11]         ; Clk      ;
; N/A                                     ; None                                                ; -4.487 ns ; ADCsSDO ; BS2:ADChandler|Port1[7]          ; Clk      ;
; N/A                                     ; None                                                ; -4.487 ns ; ADCsSDO ; BS2:ADChandler|Port1[1]          ; Clk      ;
; N/A                                     ; None                                                ; -4.512 ns ; USB[7]  ; BSblock:ChrisBS|Arb2Prog[7]      ; Clk      ;
; N/A                                     ; None                                                ; -4.519 ns ; USB[4]  ; BSblock:ChrisBS|Arb2Prog[12]     ; Clk      ;
; N/A                                     ; None                                                ; -4.536 ns ; USB[2]  ; BSblock:ChrisBS|Arb2Prog[2]      ; Clk      ;
; N/A                                     ; None                                                ; -4.537 ns ; USB[2]  ; BSblock:ChrisBS|Arb1Prog[10]     ; Clk      ;
; N/A                                     ; None                                                ; -4.554 ns ; USB[7]  ; BSblock:ChrisBS|Arb1Prog[15]     ; Clk      ;
; N/A                                     ; None                                                ; -4.554 ns ; USB[1]  ; BSblock:ChrisBS|PhaseOffset[1]   ; Clk      ;
; N/A                                     ; None                                                ; -4.572 ns ; ADCsSDO ; BS2:ADChandler|Port1[13]         ; Clk      ;
; N/A                                     ; None                                                ; -4.572 ns ; ADCsSDO ; BS2:ADChandler|Port1[14]         ; Clk      ;
; N/A                                     ; None                                                ; -4.595 ns ; ADCsSDO ; BS2:ADChandler|Port1[5]          ; Clk      ;
; N/A                                     ; None                                                ; -4.617 ns ; USB[1]  ; BSblock:ChrisBS|Arb2Prog[1]      ; Clk      ;
; N/A                                     ; None                                                ; -4.619 ns ; USB[12] ; BSblock:ChrisBS|WriteTOP         ; Clk      ;
; N/A                                     ; None                                                ; -4.623 ns ; USB[6]  ; BSblock:ChrisBS|Arb2Prog[6]      ; Clk      ;
; N/A                                     ; None                                                ; -4.629 ns ; USB[4]  ; BSblock:ChrisBS|Arb1Prog[12]     ; Clk      ;
; N/A                                     ; None                                                ; -4.644 ns ; USB[3]  ; BSblock:ChrisBS|Arb2Prog[3]      ; Clk      ;
; N/A                                     ; None                                                ; -4.650 ns ; USB[5]  ; BSblock:ChrisBS|Arb2Prog[5]      ; Clk      ;
; N/A                                     ; None                                                ; -4.670 ns ; USB[15] ; BSblock:ChrisBS|WriteTOP         ; Clk      ;
; N/A                                     ; None                                                ; -4.757 ns ; USB[0]  ; BSblock:ChrisBS|Arb1Prog[0]      ; Clk      ;
; N/A                                     ; None                                                ; -4.774 ns ; USB[5]  ; BSblock:ChrisBS|DACsDWHolder[9]  ; Clk      ;
; N/A                                     ; None                                                ; -4.776 ns ; USB[11] ; BSblock:ChrisBS|DataOut[1]       ; Clk      ;
; N/A                                     ; None                                                ; -4.778 ns ; USB[11] ; BSblock:ChrisBS|DataOut[6]       ; Clk      ;
; N/A                                     ; None                                                ; -4.778 ns ; USB[11] ; BSblock:ChrisBS|DataOut[7]       ; Clk      ;
; N/A                                     ; None                                                ; -4.780 ns ; USB[11] ; BSblock:ChrisBS|DataOut[2]       ; Clk      ;
; N/A                                     ; None                                                ; -4.782 ns ; USB[11] ; BSblock:ChrisBS|DataOut[0]       ; Clk      ;
; N/A                                     ; None                                                ; -4.783 ns ; USB[11] ; BSblock:ChrisBS|DataOut[5]       ; Clk      ;
; N/A                                     ; None                                                ; -4.831 ns ; ADCsSDO ; BS2:ADChandler|Port1[6]          ; Clk      ;
; N/A                                     ; None                                                ; -4.837 ns ; USB[9]  ; BSblock:ChrisBS|DataOut[0]       ; Clk      ;
; N/A                                     ; None                                                ; -4.860 ns ; USB[0]  ; BSblock:ChrisBS|Arb2Prog[0]      ; Clk      ;
; N/A                                     ; None                                                ; -4.902 ns ; USB[2]  ; BSblock:ChrisBS|Arb2Prog[10]     ; Clk      ;
; N/A                                     ; None                                                ; -4.911 ns ; USB[12] ; BSblock:ChrisBS|DACsTrigger      ; Clk      ;
; N/A                                     ; None                                                ; -4.920 ns ; USB[15] ; BSblock:ChrisBS|DACsTrigger      ; Clk      ;
; Timing analysis restricted to 100 rows. ; To change the limit use Settings (Assignments menu) ;           ;         ;                                  ;          ;
+-----------------------------------------+-----------------------------------------------------+-----------+---------+----------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
    Info: Processing started: Wed Sep 28 15:29:02 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off BarrierShaper -c BarrierShaper --timing_analysis_only
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "BSblock:ChrisBS|ADCClk" as buffer
Info: Slack time is -12.486 ns for clock "Clk" between source memory "lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[6]" and destination register "BSSlow:inst|DACsData"
    Info: Fmax is 28.59 MHz (period= 34.972 ns)
    Info: + Largest memory to register requirement is 4.445 ns
        Info: + Setup relationship between source and destination is 5.000 ns
            Info: + Latch edge is 5.000 ns
                Info: Clock period of Destination clock "Clk" is 10.000 ns with , Inverted offset of 5.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "Clk" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is -0.026 ns
            Info: + Shortest clock path from clock "Clk" to destination register is 2.110 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 475; CLK Node = 'Clk'
                Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X23_Y3_N3; Fanout = 2; REG Node = 'BSSlow:inst|DACsData'
                Info: Total cell delay = 1.677 ns ( 79.48 % )
                Info: Total interconnect delay = 0.433 ns ( 20.52 % )
            Info: - Longest clock path from clock "Clk" to source memory is 2.136 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 475; CLK Node = 'Clk'
                Info: 2: + IC(0.461 ns) + CELL(0.545 ns) = 2.136 ns; Loc. = M4K_X13_Y13; Fanout = 8; MEM Node = 'lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[6]'
                Info: Total cell delay = 1.675 ns ( 78.42 % )
                Info: Total interconnect delay = 0.461 ns ( 21.58 % )
        Info: - Micro clock to output delay of source is 0.500 ns
        Info: - Micro setup delay of destination is 0.029 ns
    Info: - Longest memory to register delay is 16.931 ns
        Info: 1: + IC(0.000 ns) + CELL(0.080 ns) = 0.080 ns; Loc. = M4K_X13_Y13; Fanout = 8; MEM Node = 'lpm_rom1:Sin|altsyncram:altsyncram_component|altsyncram_slp:auto_generated|q_a[6]'
        Info: 2: + IC(1.329 ns) + CELL(0.434 ns) = 1.843 ns; Loc. = LC_X22_Y13_N3; Fanout = 2; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mul_boothc:booth_enc|sel0_a[3]~COUT'
        Info: 3: + IC(0.000 ns) + CELL(0.137 ns) = 1.980 ns; Loc. = LC_X22_Y13_N4; Fanout = 3; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mul_boothc:booth_enc|sel0_a[4]~COUT'
        Info: 4: + IC(0.000 ns) + CELL(0.478 ns) = 2.458 ns; Loc. = LC_X22_Y13_N7; Fanout = 18; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mul_boothc:booth_enc|sel0_a[6]~165'
        Info: 5: + IC(0.989 ns) + CELL(0.088 ns) = 3.535 ns; Loc. = LC_X20_Y13_N0; Fanout = 15; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mul_boothc:booth_enc|sel0_a[7]~157'
        Info: 6: + IC(0.346 ns) + CELL(0.340 ns) = 4.221 ns; Loc. = LC_X20_Y13_N5; Fanout = 2; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|partial_product_node[7][1]~3761'
        Info: 7: + IC(0.933 ns) + CELL(0.449 ns) = 5.603 ns; Loc. = LC_X20_Y9_N4; Fanout = 6; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~175'
        Info: 8: + IC(0.000 ns) + CELL(0.478 ns) = 6.081 ns; Loc. = LC_X20_Y9_N5; Fanout = 3; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[3]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~133'
        Info: 9: + IC(1.195 ns) + CELL(0.443 ns) = 7.719 ns; Loc. = LC_X24_Y8_N1; Fanout = 2; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~149COUT1_280'
        Info: 10: + IC(0.000 ns) + CELL(0.062 ns) = 7.781 ns; Loc. = LC_X24_Y8_N2; Fanout = 2; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154COUT1_282'
        Info: 11: + IC(0.000 ns) + CELL(0.468 ns) = 8.249 ns; Loc. = LC_X24_Y8_N3; Fanout = 3; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~167'
        Info: 12: + IC(0.833 ns) + CELL(0.443 ns) = 9.525 ns; Loc. = LC_X25_Y8_N5; Fanout = 2; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~197COUT1_339'
        Info: 13: + IC(0.000 ns) + CELL(0.062 ns) = 9.587 ns; Loc. = LC_X25_Y8_N6; Fanout = 2; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~202COUT1_341'
        Info: 14: + IC(0.000 ns) + CELL(0.062 ns) = 9.649 ns; Loc. = LC_X25_Y8_N7; Fanout = 2; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~187COUT1_343'
        Info: 15: + IC(0.000 ns) + CELL(0.062 ns) = 9.711 ns; Loc. = LC_X25_Y8_N8; Fanout = 2; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~192COUT1_345'
        Info: 16: + IC(0.000 ns) + CELL(0.199 ns) = 9.910 ns; Loc. = LC_X25_Y8_N9; Fanout = 6; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~212'
        Info: 17: + IC(0.000 ns) + CELL(0.523 ns) = 10.433 ns; Loc. = LC_X25_Y7_N1; Fanout = 1; COMB Node = 'BSblock:ChrisBS|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~245'
        Info: 18: + IC(0.572 ns) + CELL(0.088 ns) = 11.093 ns; Loc. = LC_X26_Y7_N9; Fanout = 6; COMB Node = 'BSblock:ChrisBS|DACsDataWord[8]~633'
        Info: 19: + IC(0.958 ns) + CELL(0.443 ns) = 12.494 ns; Loc. = LC_X25_Y6_N1; Fanout = 2; COMB Node = 'TwosComp:inst3|add~1187COUT1_1281'
        Info: 20: + IC(0.000 ns) + CELL(0.062 ns) = 12.556 ns; Loc. = LC_X25_Y6_N2; Fanout = 2; COMB Node = 'TwosComp:inst3|add~1182COUT1_1283'
        Info: 21: + IC(0.000 ns) + CELL(0.062 ns) = 12.618 ns; Loc. = LC_X25_Y6_N3; Fanout = 2; COMB Node = 'TwosComp:inst3|add~1152COUT1_1284'
        Info: 22: + IC(0.000 ns) + CELL(0.468 ns) = 13.086 ns; Loc. = LC_X25_Y6_N4; Fanout = 1; COMB Node = 'TwosComp:inst3|add~1155'
        Info: 23: + IC(0.526 ns) + CELL(0.340 ns) = 13.952 ns; Loc. = LC_X24_Y6_N2; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2975'
        Info: 24: + IC(0.335 ns) + CELL(0.225 ns) = 14.512 ns; Loc. = LC_X24_Y6_N1; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2976'
        Info: 25: + IC(0.944 ns) + CELL(0.088 ns) = 15.544 ns; Loc. = LC_X23_Y3_N6; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2979'
        Info: 26: + IC(0.140 ns) + CELL(0.088 ns) = 15.772 ns; Loc. = LC_X23_Y3_N7; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2981'
        Info: 27: + IC(0.140 ns) + CELL(0.088 ns) = 16.000 ns; Loc. = LC_X23_Y3_N8; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2982'
        Info: 28: + IC(0.140 ns) + CELL(0.088 ns) = 16.228 ns; Loc. = LC_X23_Y3_N9; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2983'
        Info: 29: + IC(0.335 ns) + CELL(0.368 ns) = 16.931 ns; Loc. = LC_X23_Y3_N3; Fanout = 2; REG Node = 'BSSlow:inst|DACsData'
        Info: Total cell delay = 7.216 ns ( 42.62 % )
        Info: Total interconnect delay = 9.715 ns ( 57.38 % )
Warning: Can't achieve timing requirement Clock Setup: 'Clk' along 2304 path(s). See Report window for details.
Info: Minimum slack time is 633 ps for clock "Clk" between source register "BS2:ADChandler|CurrentPort[2]" and destination register "BS2:ADChandler|CurrentPort[2]"
    Info: + Shortest register to register delay is 0.472 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y8_N2; Fanout = 6; REG Node = 'BS2:ADChandler|CurrentPort[2]'
        Info: 2: + IC(0.000 ns) + CELL(0.472 ns) = 0.472 ns; Loc. = LC_X11_Y8_N2; Fanout = 6; REG Node = 'BS2:ADChandler|CurrentPort[2]'
        Info: Total cell delay = 0.472 ns ( 100.00 % )
    Info: - Smallest register to register requirement is -0.161 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 5.000 ns
                Info: Clock period of Destination clock "Clk" is 10.000 ns with , Inverted offset of 5.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 5.000 ns
                Info: Clock period of Source clock "Clk" is 10.000 ns with , Inverted offset of 5.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "Clk" to destination register is 5.487 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 475; CLK Node = 'Clk'
                Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N6; Fanout = 49; REG Node = 'BSblock:ChrisBS|ADCClk'
                Info: 3: + IC(2.661 ns) + CELL(0.547 ns) = 5.487 ns; Loc. = LC_X11_Y8_N2; Fanout = 6; REG Node = 'BS2:ADChandler|CurrentPort[2]'
                Info: Total cell delay = 2.397 ns ( 43.69 % )
                Info: Total interconnect delay = 3.090 ns ( 56.31 % )
            Info: - Shortest clock path from clock "Clk" to source register is 5.487 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 475; CLK Node = 'Clk'
                Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N6; Fanout = 49; REG Node = 'BSblock:ChrisBS|ADCClk'
                Info: 3: + IC(2.661 ns) + CELL(0.547 ns) = 5.487 ns; Loc. = LC_X11_Y8_N2; Fanout = 6; REG Node = 'BS2:ADChandler|CurrentPort[2]'
                Info: Total cell delay = 2.397 ns ( 43.69 % )
                Info: Total interconnect delay = 3.090 ns ( 56.31 % )
        Info: - Micro clock to output delay of source is 0.173 ns
        Info: + Micro hold delay of destination is 0.012 ns
Info: tsu for register "BSSlow:inst|DACsData" (data pin = "USB[14]", clock pin = "Clk") is 13.690 ns
    Info: + Longest pin to register delay is 15.771 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_97; Fanout = 1; PIN Node = 'USB[14]'
        Info: 2: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = IOC_X6_Y14_N0; Fanout = 12; COMB Node = 'USB~1'
        Info: 3: + IC(5.358 ns) + CELL(0.340 ns) = 6.833 ns; Loc. = LC_X19_Y12_N5; Fanout = 36; COMB Node = 'BSblock:ChrisBS|DACsDataWord~622'
        Info: 4: + IC(2.875 ns) + CELL(0.225 ns) = 9.933 ns; Loc. = LC_X26_Y7_N9; Fanout = 6; COMB Node = 'BSblock:ChrisBS|DACsDataWord[8]~633'
        Info: 5: + IC(0.958 ns) + CELL(0.443 ns) = 11.334 ns; Loc. = LC_X25_Y6_N1; Fanout = 2; COMB Node = 'TwosComp:inst3|add~1187COUT1_1281'
        Info: 6: + IC(0.000 ns) + CELL(0.062 ns) = 11.396 ns; Loc. = LC_X25_Y6_N2; Fanout = 2; COMB Node = 'TwosComp:inst3|add~1182COUT1_1283'
        Info: 7: + IC(0.000 ns) + CELL(0.062 ns) = 11.458 ns; Loc. = LC_X25_Y6_N3; Fanout = 2; COMB Node = 'TwosComp:inst3|add~1152COUT1_1284'
        Info: 8: + IC(0.000 ns) + CELL(0.468 ns) = 11.926 ns; Loc. = LC_X25_Y6_N4; Fanout = 1; COMB Node = 'TwosComp:inst3|add~1155'
        Info: 9: + IC(0.526 ns) + CELL(0.340 ns) = 12.792 ns; Loc. = LC_X24_Y6_N2; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2975'
        Info: 10: + IC(0.335 ns) + CELL(0.225 ns) = 13.352 ns; Loc. = LC_X24_Y6_N1; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2976'
        Info: 11: + IC(0.944 ns) + CELL(0.088 ns) = 14.384 ns; Loc. = LC_X23_Y3_N6; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2979'
        Info: 12: + IC(0.140 ns) + CELL(0.088 ns) = 14.612 ns; Loc. = LC_X23_Y3_N7; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2981'
        Info: 13: + IC(0.140 ns) + CELL(0.088 ns) = 14.840 ns; Loc. = LC_X23_Y3_N8; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2982'
        Info: 14: + IC(0.140 ns) + CELL(0.088 ns) = 15.068 ns; Loc. = LC_X23_Y3_N9; Fanout = 1; COMB Node = 'BSSlow:inst|Select~2983'
        Info: 15: + IC(0.335 ns) + CELL(0.368 ns) = 15.771 ns; Loc. = LC_X23_Y3_N3; Fanout = 2; REG Node = 'BSSlow:inst|DACsData'
        Info: Total cell delay = 4.020 ns ( 25.49 % )
        Info: Total interconnect delay = 11.751 ns ( 74.51 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "Clk" to destination register is 2.110 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 475; CLK Node = 'Clk'
        Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X23_Y3_N3; Fanout = 2; REG Node = 'BSSlow:inst|DACsData'
        Info: Total cell delay = 1.677 ns ( 79.48 % )
        Info: Total interconnect delay = 0.433 ns ( 20.52 % )
Info: tco from clock "Clk" to destination pin "ADCsCS" through register "BS2:ADChandler|ADCsCS" is 10.213 ns
    Info: + Longest clock path from clock "Clk" to source register is 5.508 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 475; CLK Node = 'Clk'
        Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N6; Fanout = 49; REG Node = 'BSblock:ChrisBS|ADCClk'
        Info: 3: + IC(2.682 ns) + CELL(0.547 ns) = 5.508 ns; Loc. = LC_X12_Y11_N4; Fanout = 2; REG Node = 'BS2:ADChandler|ADCsCS'
        Info: Total cell delay = 2.397 ns ( 43.52 % )
        Info: Total interconnect delay = 3.111 ns ( 56.48 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 4.532 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y11_N4; Fanout = 2; REG Node = 'BS2:ADChandler|ADCsCS'
        Info: 2: + IC(2.910 ns) + CELL(1.622 ns) = 4.532 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'ADCsCS'
        Info: Total cell delay = 1.622 ns ( 35.79 % )
        Info: Total interconnect delay = 2.910 ns ( 64.21 % )
Info: Longest tpd from source pin "USB[14]" to destination pin "USB[0]" is 11.078 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_97; Fanout = 1; PIN Node = 'USB[14]'
    Info: 2: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = IOC_X6_Y14_N0; Fanout = 12; COMB Node = 'USB~1'
    Info: 3: + IC(5.359 ns) + CELL(0.340 ns) = 6.834 ns; Loc. = LC_X19_Y12_N7; Fanout = 16; COMB Node = 'BSblock:ChrisBS|reduce_nor~427'
    Info: 4: + IC(2.648 ns) + CELL(1.596 ns) = 11.078 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'USB[0]'
    Info: Total cell delay = 3.071 ns ( 27.72 % )
    Info: Total interconnect delay = 8.007 ns ( 72.28 % )
Info: th for register "BS2:ADChandler|Port8[1]" (data pin = "ADCsSDO", clock pin = "Clk") is -0.985 ns
    Info: + Longest clock path from clock "Clk" to destination register is 5.479 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 475; CLK Node = 'Clk'
        Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N6; Fanout = 49; REG Node = 'BSblock:ChrisBS|ADCClk'
        Info: 3: + IC(2.653 ns) + CELL(0.547 ns) = 5.479 ns; Loc. = LC_X12_Y1_N7; Fanout = 1; REG Node = 'BS2:ADChandler|Port8[1]'
        Info: Total cell delay = 2.397 ns ( 43.75 % )
        Info: Total interconnect delay = 3.082 ns ( 56.25 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 6.476 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_27; Fanout = 32; PIN Node = 'ADCsSDO'
        Info: 2: + IC(5.252 ns) + CELL(0.089 ns) = 6.476 ns; Loc. = LC_X12_Y1_N7; Fanout = 1; REG Node = 'BS2:ADChandler|Port8[1]'
        Info: Total cell delay = 1.224 ns ( 18.90 % )
        Info: Total interconnect delay = 5.252 ns ( 81.10 % )
Critical Warning: Timing requirements were not met. See Report window for details.
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Wed Sep 28 15:29:06 2005
    Info: Elapsed time: 00:00:04


