Analysis & Synthesis report for n-Pulse
Wed Dec 09 15:05:39 2009
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (No Restructuring Performed)
 10. Source assignments for lpm_counter0:DacClk|lpm_counter:lpm_counter_component
 11. Source assignments for lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component
 12. Parameter Settings for User Entity Instance: lpm_counter0:DacClk|lpm_counter:lpm_counter_component
 13. Parameter Settings for User Entity Instance: lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component
 14. Parameter Settings for User Entity Instance: USB_Interface:OutsideWorld
 15. Parameter Settings for User Entity Instance: nPulseSelector:Banker
 16. Analysis & Synthesis Messages
 17. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Dec 09 15:05:39 2009    ;
; Quartus II Version          ; 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name               ; n-Pulse                                  ;
; Top-level Entity Name       ; nPulse                                   ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 455                                      ;
; Total pins                  ; 34                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP1C3T100C6        ;                    ;
; Top-level entity name                                                      ; nPulse             ; n-Pulse            ;
; Family name                                                                ; Cyclone            ; Stratix            ;
; Use smart compilation                                                      ; On                 ; Off                ;
; Maximum processors allowed for parallel compilation                        ; 2                  ;                    ;
; Restructure Multiplexers                                                   ; Off                ; Auto               ;
; Preserve fewer node names                                                  ; Off                ; On                 ;
; Verilog Show LMF Mapping Messages                                          ; Off                ;                    ;
; Verilog Version                                                            ; SystemVerilog_2005 ; Verilog_2001       ;
; State Machine Processing                                                   ; One-Hot            ; Auto               ;
; Power-Up Don't Care                                                        ; Off                ; On                 ;
; Ignore LCELL Buffers                                                       ; On                 ; Off                ;
; Optimization Technique                                                     ; Speed              ; Balanced           ;
; Perform WYSIWYG Primitive Resynthesis                                      ; On                 ; Off                ;
; HDL message level                                                          ; Level1             ; Level2             ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Maximum Number of M512 Memory Blocks                                       ; -1                 ; -1                 ;
; Maximum Number of M4K/M9K Memory Blocks                                    ; -1                 ; -1                 ;
; Maximum Number of M-RAM/M144K Memory Blocks                                ; -1                 ; -1                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                         ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation attempted to use more processors than were available, which may cause increased compilation time. For lowest compilation time, correct your settings.
+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 1           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                     ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                     ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------+
; nPulse.bdf                       ; yes             ; User Block Diagram/Schematic File  ; C:/Projects/Archives/n-Pulse Selector/Altera/nPulse.bdf                          ;
; nPulseSelector.v                 ; yes             ; User Verilog HDL File              ; C:/Projects/Archives/n-Pulse Selector/Altera/nPulseSelector.v                    ;
; USB_Interface.v                  ; yes             ; User Verilog HDL File              ; C:/Projects/Archives/n-Pulse Selector/Altera/USB_Interface.v                     ;
; lpm_counter0.v                   ; yes             ; User Wizard-Generated File         ; C:/Projects/Archives/n-Pulse Selector/Altera/lpm_counter0.v                      ;
; lpm_counter1.v                   ; yes             ; User Wizard-Generated File         ; C:/Projects/Archives/n-Pulse Selector/Altera/lpm_counter1.v                      ;
; LTC1453.v                        ; yes             ; User Verilog HDL File              ; C:/Projects/Archives/n-Pulse Selector/Altera/LTC1453.v                           ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; c:/program files/altera/quartu~1/quartus/libraries/megafunctions/lpm_counter.tdf ;
; db/cntr_6dh.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/n-Pulse Selector/Altera/db/cntr_6dh.tdf                     ;
; db/cntr_8ii.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/n-Pulse Selector/Altera/db/cntr_8ii.tdf                     ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Total logic elements                        ; 455       ;
;     -- Combinational with no register       ; 232       ;
;     -- Register only                        ; 53        ;
;     -- Combinational with a register        ; 170       ;
;                                             ;           ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 165       ;
;     -- 3 input functions                    ; 69        ;
;     -- 2 input functions                    ; 164       ;
;     -- 1 input functions                    ; 4         ;
;     -- 0 input functions                    ; 0         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 337       ;
;     -- arithmetic mode                      ; 118       ;
;     -- qfbk mode                            ; 0         ;
;     -- register cascade mode                ; 0         ;
;     -- synchronous clear/load mode          ; 46        ;
;     -- asynchronous clear/load mode         ; 0         ;
;                                             ;           ;
; Total registers                             ; 223       ;
; Total logic cells in carry chains           ; 124       ;
; I/O pins                                    ; 34        ;
; Maximum fan-out node                        ; Clk100MHz ;
; Maximum fan-out                             ; 147       ;
; Total fan-out                               ; 1647      ;
; Average fan-out                             ; 3.37      ;
+---------------------------------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                       ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                      ; Library Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------+--------------+
; |nPulse                                   ; 455 (0)     ; 223          ; 0           ; 34   ; 0            ; 232 (0)      ; 53 (0)            ; 170 (0)          ; 124 (0)         ; 0 (0)      ; |nPulse                                                                                  ; work         ;
;    |LTC1453:HV_Supply|                    ; 45 (45)     ; 18           ; 0           ; 0    ; 0            ; 27 (27)      ; 12 (12)           ; 6 (6)            ; 0 (0)           ; 0 (0)      ; |nPulse|LTC1453:HV_Supply                                                                ;              ;
;    |LTC1453:PD_Threshold|                 ; 43 (43)     ; 18           ; 0           ; 0    ; 0            ; 25 (25)      ; 12 (12)           ; 6 (6)            ; 0 (0)           ; 0 (0)      ; |nPulse|LTC1453:PD_Threshold                                                             ;              ;
;    |LTC1453:Supply200|                    ; 45 (45)     ; 18           ; 0           ; 0    ; 0            ; 27 (27)      ; 12 (12)           ; 6 (6)            ; 0 (0)           ; 0 (0)      ; |nPulse|LTC1453:Supply200                                                                ;              ;
;    |USB_Interface:OutsideWorld|           ; 198 (198)   ; 101          ; 0           ; 0    ; 0            ; 97 (97)      ; 17 (17)           ; 84 (84)          ; 61 (61)         ; 0 (0)      ; |nPulse|USB_Interface:OutsideWorld                                                       ;              ;
;    |lpm_counter0:DacClk|                  ; 4 (0)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; 0 (0)      ; |nPulse|lpm_counter0:DacClk                                                              ;              ;
;       |lpm_counter:lpm_counter_component| ; 4 (0)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; 0 (0)      ; |nPulse|lpm_counter0:DacClk|lpm_counter:lpm_counter_component                            ;              ;
;          |cntr_6dh:auto_generated|        ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; 0 (0)      ; |nPulse|lpm_counter0:DacClk|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated    ;              ;
;    |lpm_counter1:POR_671mS|               ; 23 (0)      ; 22           ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 22 (0)           ; 23 (0)          ; 0 (0)      ; |nPulse|lpm_counter1:POR_671mS                                                           ;              ;
;       |lpm_counter:lpm_counter_component| ; 23 (0)      ; 22           ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 22 (0)           ; 23 (0)          ; 0 (0)      ; |nPulse|lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component                         ;              ;
;          |cntr_8ii:auto_generated|        ; 23 (23)     ; 22           ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 22 (22)          ; 23 (23)         ; 0 (0)      ; |nPulse|lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component|cntr_8ii:auto_generated ;              ;
;    |nPulseSelector:Banker|                ; 97 (97)     ; 42           ; 0           ; 0    ; 0            ; 55 (55)      ; 0 (0)             ; 42 (42)          ; 36 (36)         ; 0 (0)      ; |nPulse|nPulseSelector:Banker                                                            ;              ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 223   ;
; Number of registers using Synchronous Clear  ; 22    ;
; Number of registers using Synchronous Load   ; 24    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 87    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed)                                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |nPulse|nPulseSelector:Banker|OffAnd           ;
; 4:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |nPulse|nPulseSelector:Banker|TmrOff[11]       ;
; 4:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; Yes        ; |nPulse|nPulseSelector:Banker|TmrOn[15]        ;
; 3:1                ; 36 bits   ; 72 LEs        ; 72 LEs               ; 0 LEs                  ; Yes        ; |nPulse|USB_Interface:OutsideWorld|Sandman[31] ;
; 4:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |nPulse|USB_Interface:OutsideWorld|TH_DAC[0]   ;
; 4:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |nPulse|USB_Interface:OutsideWorld|HV_Req[7]   ;
; 5:1                ; 12 bits   ; 36 LEs        ; 12 LEs               ; 24 LEs                 ; Yes        ; |nPulse|USB_Interface:OutsideWorld|V160_Req[9] ;
; 17:1               ; 3 bits    ; 33 LEs        ; 9 LEs                ; 24 LEs                 ; Yes        ; |nPulse|LTC1453:HV_Supply|State[1]             ;
; 17:1               ; 3 bits    ; 33 LEs        ; 9 LEs                ; 24 LEs                 ; Yes        ; |nPulse|LTC1453:Supply200|State[3]             ;
; 17:1               ; 3 bits    ; 33 LEs        ; 9 LEs                ; 24 LEs                 ; Yes        ; |nPulse|LTC1453:PD_Threshold|State[1]          ;
; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; Yes        ; |nPulse|nPulseSelector:Banker|State[1]         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+


+------------------------------------------------------------------------------+
; Source assignments for lpm_counter0:DacClk|lpm_counter:lpm_counter_component ;
+---------------------------+-------+------+-----------------------------------+
; Assignment                ; Value ; From ; To                                ;
+---------------------------+-------+------+-----------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                 ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                 ;
+---------------------------+-------+------+-----------------------------------+


+---------------------------------------------------------------------------------+
; Source assignments for lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component ;
+---------------------------+-------+------+--------------------------------------+
; Assignment                ; Value ; From ; To                                   ;
+---------------------------+-------+------+--------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                    ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                    ;
+---------------------------+-------+------+--------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter0:DacClk|lpm_counter:lpm_counter_component ;
+------------------------+-------------+-------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                        ;
+------------------------+-------------+-------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                              ;
; LPM_WIDTH              ; 4           ; Signed Integer                                              ;
; LPM_DIRECTION          ; UP          ; Untyped                                                     ;
; LPM_MODULUS            ; 0           ; Untyped                                                     ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                                     ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                                     ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                     ;
; DEVICE_FAMILY          ; Cyclone     ; Untyped                                                     ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                     ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                          ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                          ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                                     ;
; LABWIDE_SCLR           ; ON          ; Untyped                                                     ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                                     ;
; CBXI_PARAMETER         ; cntr_6dh    ; Untyped                                                     ;
+------------------------+-------------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component ;
+------------------------+-------------+----------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                           ;
+------------------------+-------------+----------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                 ;
; LPM_WIDTH              ; 22          ; Signed Integer                                                 ;
; LPM_DIRECTION          ; UP          ; Untyped                                                        ;
; LPM_MODULUS            ; 0           ; Untyped                                                        ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                                        ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                                        ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                        ;
; DEVICE_FAMILY          ; Cyclone     ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                        ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                             ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                             ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                                        ;
; LABWIDE_SCLR           ; ON          ; Untyped                                                        ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                                        ;
; CBXI_PARAMETER         ; cntr_8ii    ; Untyped                                                        ;
+------------------------+-------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: USB_Interface:OutsideWorld ;
+----------------+--------------------------------------+-----------------+
; Parameter Name ; Value                                ; Type            ;
+----------------+--------------------------------------+-----------------+
; DEFAULT_HV     ; 101010111100                         ; Unsigned Binary ;
; DEFAULT_V160   ; 011000101100                         ; Unsigned Binary ;
; DEFAULT_TH     ; 110011001100                         ; Unsigned Binary ;
; DAC2_100V      ; 011000101100                         ; Unsigned Binary ;
; NAPTIME        ; 011011111100001000111010110000000000 ; Unsigned Binary ;
+----------------+--------------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: nPulseSelector:Banker ;
+----------------+--------------------------+------------------------+
; Parameter Name ; Value                    ; Type                   ;
+----------------+--------------------------+------------------------+
; PULSE_WIDTH    ; 000000000000011111010000 ; Unsigned Binary        ;
; MIN_PERIOD     ; 100110001001011010000000 ; Unsigned Binary        ;
+----------------+--------------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
    Info: Processing started: Wed Dec 09 15:05:21 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off nPulse -c n-Pulse
Info: Parallel compilation is enabled and will use up to 2 processors
Warning: Parallel compilation is enabled for 2 processors, but there are only 1 processors in the system. Runtime may increase due to over usage of the processor space.
Info: Found 1 design units, including 1 entities, in source file npulse.bdf
    Info: Found entity 1: nPulse
Info: Found 1 design units, including 1 entities, in source file npulseselector.v
    Info: Found entity 1: nPulseSelector
Info: Found 1 design units, including 1 entities, in source file usb_interface.v
    Info: Found entity 1: USB_Interface
Info: Found 1 design units, including 1 entities, in source file lpm_counter0.v
    Info: Found entity 1: lpm_counter0
Info: Found 1 design units, including 1 entities, in source file lpm_counter1.v
    Info: Found entity 1: lpm_counter1
Info: Found 1 design units, including 1 entities, in source file lpm_counter2.v
    Info: Found entity 1: lpm_counter2
Info: Found 2 design units, including 1 entities, in source file lpm_counter3.vhd
    Info: Found design unit 1: lpm_counter3-SYN
    Info: Found entity 1: lpm_counter3
Info: Found 1 design units, including 1 entities, in source file lpm_inv0.v
    Info: Found entity 1: lpm_inv0
Info: Found 1 design units, including 1 entities, in source file ltc1453.v
    Info: Found entity 1: LTC1453
Info: Elaborating entity "nPulse" for the top level hierarchy
Info: Elaborating entity "LTC1453" for hierarchy "LTC1453:HV_Supply"
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:DacClk"
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:DacClk|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter0:DacClk|lpm_counter:lpm_counter_component"
Info: Instantiated megafunction "lpm_counter0:DacClk|lpm_counter:lpm_counter_component" with the following parameter:
    Info: Parameter "lpm_direction" = "UP"
    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
    Info: Parameter "lpm_type" = "LPM_COUNTER"
    Info: Parameter "lpm_width" = "4"
Info: Found 1 design units, including 1 entities, in source file db/cntr_6dh.tdf
    Info: Found entity 1: cntr_6dh
Info: Elaborating entity "cntr_6dh" for hierarchy "lpm_counter0:DacClk|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated"
Info: Elaborating entity "lpm_counter1" for hierarchy "lpm_counter1:POR_671mS"
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component"
Info: Instantiated megafunction "lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component" with the following parameter:
    Info: Parameter "lpm_direction" = "UP"
    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
    Info: Parameter "lpm_type" = "LPM_COUNTER"
    Info: Parameter "lpm_width" = "22"
Info: Found 1 design units, including 1 entities, in source file db/cntr_8ii.tdf
    Info: Found entity 1: cntr_8ii
Info: Elaborating entity "cntr_8ii" for hierarchy "lpm_counter1:POR_671mS|lpm_counter:lpm_counter_component|cntr_8ii:auto_generated"
Info: Elaborating entity "USB_Interface" for hierarchy "USB_Interface:OutsideWorld"
Info: Elaborating entity "nPulseSelector" for hierarchy "nPulseSelector:Banker"
Info: Ignored 1 buffer(s)
    Info: Ignored 1 EXPANDER buffer(s)
Info: Resynthesizing 0 WYSIWYG logic cells and I/Os using "speed" technology mapper which leaves 27 WYSIWYG logic cells and I/Os untouched
Info: Performing gate-level register retiming
Info: Not allowed to move 108 registers
    Info: Not allowed to move at least 2 registers because they are in a sequence of registers directly fed by input pins
    Info: Not allowed to move at least 5 registers because they feed output pins directly
    Info: Not allowed to move at least 75 registers because they are fed by registers in a different clock domain
    Info: Not allowed to move at least 26 registers because they feed registers in a different clock domain
Info: The Quartus II software applied gate-level register retiming to 0 clock domains
Info: Generated suppressed messages file C:/Projects/Archives/n-Pulse Selector/Altera/n-Pulse.map.smsg
Info: Implemented 489 device resources after synthesis - the final resource count might be different
    Info: Implemented 19 input pins
    Info: Implemented 15 output pins
    Info: Implemented 455 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 201 megabytes
    Info: Processing ended: Wed Dec 09 15:05:39 2009
    Info: Elapsed time: 00:00:18
    Info: Total CPU time (on all processors): 00:00:12


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Projects/Archives/n-Pulse Selector/Altera/n-Pulse.map.smsg.


