Coincidence Timer AKA "PhotoFinish" PROTOCOLS Started Dec 2007 by Alan Stummer, astummer_at_physics.utoronto.ca Last revised 11 Feb 2009 (PE3-4 naming discrepency). IMPORTANT NOTE Xingxing Xing revamped both the GUI and embedded software in 2010. This document might be superceded! RAISON D'ETRE ============= PhotoFinish measures the time difference between signals from two APDs (Avalanche PhotoDiode), from about 100pS to 150nS. MODUS OPERANDI ============== When an APD event happens on either channel, the hardware trips and begins ramping an RC low pass filter. Two ADCs asynchronously (to the events) measures both RC filters at 10nS intervals. If either ADC level is above threshold then the event cycle is triggered. If both ADCs are above threshold before timeout (about 100-150nS) then a coincidence has occured. A flag is set, the Rabbit processor reads the ADCs and the number of cycles between the photodide events, then acknowledges the coicidence and the cycle starts again. By knowing the RC "1" and "0" levels and the RC time constant, the photodiode event times can be calculated and therefore the time difference between them is known. Expected resolution is <100pS. COMMANDS FROM HOST COMPUTER TO RABBIT ===================================== (all undefined bits are ignored) 1st byte Size Description ---- ---- ------------------------ "R" 5 Run (detect and report coincidences). byte 2, bit 0: high means run, low means stop. byte 3, CountTime [15:8] byte 4, CountTime [7:0], Counttime = 0 means run forever. byte 5, bit 0: high means send arrival time, low means not. "C" 2 Set calibration mode. byte 2, bit 0: high is calibration on, low is off. Will stop running. bit 1 high is calibration high level, low is low level. "3" 1 Read FPGA register 3, present value of ADC "A", used for calibration. "4" 1 Read FPGA register 4. present value of ADC "B", used for calibration. "V" 1 Read Rabbit (Dynamic C) and FPGA (Verilog) version numbers. *** Following are not used but code can be uncommented if needed *** "A" 3 Set DAC A, next two bytes are data. "B" 3 Set DAC B, next two bytes are data. TRAFFIC FROM RABBIT TO HOST ============================= (all undefined bits are in an unknown state) 1st byte Size Description ---- ---- ----------------- "H" 1 Heartbeat, every few seconds to say PhotoFinish is alive and well and living in Toronto. "D" 1 Scheduled time out. Rabbit has stop running. "3" @@4 ADC A (FPGA register 3). byte 2: MS nibble of ADC A, 4 MS bits are 0. byte 3: LS byte of ADC A. @@byte 4: bit 0: high is calibration high, low is calibration low. "4" @@4 ADC B (FPGA register 4). byte 2: MS nibble of ADC B, 4 MS bits are 0. byte 3: LS byte of ADC B. @@byte 4: bit 0: high is calibration high, low is calibration low. "S" 16 Hits report header. byte 2: hits A [23:16] byte 3: hits A [15:8] byte 4: hits A [7:0] byte 5: hits B [23:16] byte 6: hits B [15:8] byte 7: hits B [7:0] byte 8: CoinAB [23:16] byte 9: CoinAB [15:8] byte 10: CoinAB [7:0] byte 11: TimedCoinAB counter [23:16] byte 12: TimedCoinAB counter [15:8] byte 13: TimedCoinAB counter [7:0] byte 14: WaitTime counter [23:16] byte 15: WaitTime counter [15:8] byte 16: WaitTime counter [7:0] "P" 2 Coincidence report packet header (see "R" below). byte 2: number of coincidence reports in packet. "R" 7 When running and detected a coincidence (see "P" above). byte 2: MS nibble of ADC A, 4 MS bits are 0. byte 3: LS byte of ADC A. byte 4: MS nibble of ADC B, 4 MS bits are 0. byte 5: LS byte of ADC B. byte 6: Offset counter, 10nS per count. byte 7, bit 0: Overrange on ADC A. bit 1: Overrange on ADC B. bit 2: high means APD A arrived before B, low is B then A. "V" 16 Rabbit (Dynamic C) and FPGA (Verilog) version numbers. byte 2: FPGA major version, 4 LS bits only. byte 3: FPGA minor version (4 MS bits) and revision (4 LS bits). byte 4-16: Rabbit version, padded with trailing spaces. *** All of the following if for development only, the host GUI does not care about it *** FPGA REGISTER MAP as read by the Rabbit (ADC values are in plain old unsigned binary) ===================================================================================== Address[0][11:0] Read ADC value for channel "A", first measurement after it tripped Address[1][11:0] Read ADC value for channel "B", first measurement after it tripped Address[2][3:0] Read offset counter [2][7:4] not used [2][8] OverRange A [2][9] OverRange B [2][10] 1: A arrived before B, 0: B arrived before A [2][11] not used, defaults to 0 if CalOut = 1: Address[3][11:0] Read current ADC A value, for calibration Address[4][11:0] Read current ADC B value, for calibration else Address[3][11:0] Read wait time register, [11:0] Address[4][11:0] Read wait time register, [23:12] Address[5][11:0] Read hits count for channel A, [11:0] Address[6][11:0] Read hits count for channel B, [11:0] Address[7][11:0] Read hits count for channel A, [23:12] Address[8][11:0] Read hits count for channel B, [23:12] Address[9] Reset hits counter Address[10] Calibrate low value Address[11] Calibrate high value Address[12] Not used (was Stop calibrate mode) Address[13][11:0] Read Verilog version Address[14][11:0] Read coincidence counter, [11:0] Address[15][11:0] Read coincidence counter, [23:12] DAC CONTROL & SETTINGS ============================= DACs are used only for development and will be replaced by a resistor later. Do not use in the host GUI. The DACs set the threshold voltages for the input discriminators. To load a DAC, set the DAC's /CS low. For each bit of the 12-bit little endian data, set the data then toggle the clock high then low. End by raising the /CS high. DAC full scale is +2.5V, the threshold full scale is 0.5V. Therefore, the threshold voltage is 2.5 / 5 * n / 4095, where 'n' is the DAC value. RABBIT ADDRESS MAP ("-" means not used) ======================================= Port I/O Description ---- --- ---------------------------- PB0 O Display_RS PB2 O Display_RW PB3 O Display_En PB4 O Display_D4 PB5 O Display_D5 PB6 O Display_D6 PB7 O Display_D7 PC0 O - PC1 I - PC2 O DAC-D PC3 I - PC4 O DAC-CLK PC5 I - PD4 O DAC_/CS-A PD5 O DAC_/CS-B PE1 I FPGA DataReady (true when a coincidence is detected, continues to count but not measure coincidences) PE3 O FPGA CS PE4 O FPGA Address3 PE5 O FPGA Address0 PE6 O FPGA Address1 PE7 O FPGA Address2 PF0 I FPGA Data0 PF1 I FPGA Data1 PF2 I FPGA Data2 PF3 I FPGA Data3 PF4 I FPGA Data4 PF5 I FPGA Data5 PF6 I FPGA Data6 PF7 I FPGA Data7 PG0 I FPGA Data8 PG1 I FPGA Data9 PG2 I FPGA Data10 PG3 I FPGA Data11 PG4 - - PG5 - - PG6 O RabbitReadingData (tells FPGA to count but not measure coincidences) PG7 O RunEnable (enables FPGA to detect coincidences and timing, depending on RabbitHasData)