<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">Fitter report for CoincidenceCounter
Tue Nov 04 14:02:54 2014
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. I/O Assignment Warnings
  6. Fitter Netlist Optimizations
  7. Incremental Compilation Preservation Summary
  8. Incremental Compilation Partition Settings
  9. Incremental Compilation Placement Preservation
 10. Pin-Out File
 11. Fitter Resource Usage Summary
 12. Fitter Partition Statistics
 13. Input Pins
 14. Output Pins
 15. Dual Purpose and Dedicated Pins
 16. I/O Bank Usage
 17. All Package Pins
 18. Fitter Resource Utilization by Entity
 19. Delay Chain Summary
 20. Pad To Core Delay Chain Fanout
 21. Control Signals
 22. Global &amp; Other Fast Signals
 23. Non-Global High Fan-Out Signals
 24. Fitter RAM Summary
 25. Routing Usage Summary
 26. LAB Logic Elements
 27. LAB-wide Signals
 28. LAB Signals Sourced
 29. LAB Signals Sourced Out
 30. LAB Distinct Inputs
 31. I/O Rules Summary
 32. I/O Rules Details
 33. I/O Rules Matrix
 34. Fitter Device Options
 35. Operating Settings and Conditions
 36. Estimated Delay Added for Hold Timing Summary
 37. Estimated Delay Added for Hold Timing Details
 38. Fitter Messages
 39. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Fitter Summary                                                                   ;
+------------------------------------+---------------------------------------------+
; Fitter Status                      ; Successful - Tue Nov 04 14:02:54 2014       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; CoincidenceCounter                          ;
; Top-level Entity Name              ; CoincidenceCounter                          ;
; Family                             ; Cyclone III                                 ;
; Device                             ; EP3C10E144C7                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 287 / 10,320 ( 3 % )                        ;
;     Total combinational functions  ; 246 / 10,320 ( 2 % )                        ;
;     Dedicated logic registers      ; 106 / 10,320 ( 1 % )                        ;
; Total registers                    ; 106                                         ;
; Total pins                         ; 43 / 95 ( 45 % )                            ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 65,536 / 423,936 ( 15 % )                   ;
; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % )                              ;
; Total PLLs                         ; 0 / 2 ( 0 % )                               ;
+------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                            ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                                     ; Setting                               ; Default Value                         ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                                     ; EP3C10E144C7                          ;                                       ;
; Use smart compilation                                                      ; On                                    ; Off                                   ;
; Maximum processors allowed for parallel compilation                        ; All                                   ; 1                                     ;
; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; On                                    ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; On                                    ; Off                                   ;
; Perform Register Duplication for Performance                               ; On                                    ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                                ; On                                    ; Off                                   ;
; Perform Register Retiming for Performance                                  ; On                                    ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                     ; On                                    ; Off                                   ;
; Fitter Effort                                                              ; Standard Fit                          ; Auto Fit                              ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
; Enable compact report table                                                ; Off                                   ; Off                                   ;
; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
; SSN Optimization                                                           ; Off                                   ; Off                                   ;
; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
; PCI I/O                                                                    ; Off                                   ; Off                                   ;
; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
; Auto Delay Chains                                                          ; On                                    ; On                                    ;
; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
; Auto Global Clock                                                          ; On                                    ; On                                    ;
; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
; Optimize Design for Metastability                                          ; Off                                   ; Off                                   ;
; Maximum number of global clocks allowed                                    ; -1                                    ; -1                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.06        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   6.3%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+-----------------------------------+
; I/O Assignment Warnings           ;
+----------+------------------------+
; Pin Name ; Reason                 ;
+----------+------------------------+
; Rdat[15] ; Missing drive strength ;
; Rdat[14] ; Missing drive strength ;
; Rdat[13] ; Missing drive strength ;
; Rdat[12] ; Missing drive strength ;
; Rdat[11] ; Missing drive strength ;
; Rdat[10] ; Missing drive strength ;
; Rdat[9]  ; Missing drive strength ;
; Rdat[8]  ; Missing drive strength ;
; Rdat[7]  ; Missing drive strength ;
; Rdat[6]  ; Missing drive strength ;
; Rdat[5]  ; Missing drive strength ;
; Rdat[4]  ; Missing drive strength ;
; Rdat[3]  ; Missing drive strength ;
; Rdat[2]  ; Missing drive strength ;
; Rdat[1]  ; Missing drive strength ;
; Rdat[0]  ; Missing drive strength ;
+----------+------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                           ;
+---------------------------------+------------+--------------------+---------------------+-----------+----------------+----------------------+------------------+-----------------------+
; Node                            ; Action     ; Operation          ; Reason              ; Node Port ; Node Port Name ; Destination Node     ; Destination Port ; Destination Port Name ;
+---------------------------------+------------+--------------------+---------------------+-----------+----------------+----------------------+------------------+-----------------------+
; RabbitControl:inst|Add2~1       ; Modified   ; Physical Synthesis ; Timing optimization ;           ;                ;                      ;                  ;                       ;
; RabbitControl:inst|Selector10~1 ; Modified   ; Physical Synthesis ; Timing optimization ;           ;                ;                      ;                  ;                       ;
; inst10                          ; Duplicated ; Physical Synthesis ; Timing optimization ; COMBOUT   ;                ; inst10~_Duplicate_1  ; COMBOUT          ;                       ;
; inst10                          ; Duplicated ; Physical Synthesis ; Timing optimization ; COMBOUT   ;                ; inst10~_Duplicate_3  ; COMBOUT          ;                       ;
; inst10                          ; Duplicated ; Physical Synthesis ; Timing optimization ; COMBOUT   ;                ; inst10~_Duplicate_5  ; COMBOUT          ;                       ;
; inst10                          ; Duplicated ; Physical Synthesis ; Timing optimization ; COMBOUT   ;                ; inst10~_Duplicate_7  ; COMBOUT          ;                       ;
; inst10                          ; Duplicated ; Physical Synthesis ; Timing optimization ; COMBOUT   ;                ; inst10~_Duplicate_9  ; COMBOUT          ;                       ;
; inst10                          ; Duplicated ; Physical Synthesis ; Timing optimization ; COMBOUT   ;                ; inst10~_Duplicate_11 ; COMBOUT          ;                       ;
; inst10                          ; Duplicated ; Physical Synthesis ; Timing optimization ; COMBOUT   ;                ; inst10~_Duplicate_13 ; COMBOUT          ;                       ;
; inst10                          ; Duplicated ; Physical Synthesis ; Timing optimization ; COMBOUT   ;                ; inst10~_Duplicate_15 ; COMBOUT          ;                       ;
; inst10                          ; Deleted    ; Physical Synthesis ; Timing optimization ;           ;                ;                      ;                  ;                       ;
+---------------------------------+------------+--------------------+---------------------+-----------+----------------+----------------------+------------------+-----------------------+


+--------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary                                                     ;
+---------------------+--------------------+----------------------------+--------------------------+
; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+--------------------+----------------------------+--------------------------+
; Placement (by node) ;                    ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 475 ) ; 0.00 % ( 0 / 475 )         ; 0.00 % ( 0 / 475 )       ;
;     -- Achieved     ; 0.00 % ( 0 / 475 ) ; 0.00 % ( 0 / 475 )         ; 0.00 % ( 0 / 475 )       ;
;                     ;                    ;                            ;                          ;
; Routing (by net)    ;                    ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+---------------------+--------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                                                     ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top                            ; 0.00 % ( 0 / 465 )    ; N/A                     ; Source File       ; N/A                 ;       ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Projects/Archives/2008 Coincidence Counter/Altera/CoincidenceCounter.pin.


+-------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                           ;
+---------------------------------------------+---------------------------+
; Resource                                    ; Usage                     ;
+---------------------------------------------+---------------------------+
; Total logic elements                        ; 287 / 10,320 ( 3 % )      ;
;     -- Combinational with no register       ; 181                       ;
;     -- Register only                        ; 41                        ;
;     -- Combinational with a register        ; 65                        ;
;                                             ;                           ;
; Logic element usage by number of LUT inputs ;                           ;
;     -- 4 input functions                    ; 138                       ;
;     -- 3 input functions                    ; 29                        ;
;     -- &lt;=2 input functions                  ; 79                        ;
;     -- Register only                        ; 41                        ;
;                                             ;                           ;
; Logic elements by mode                      ;                           ;
;     -- normal mode                          ; 195                       ;
;     -- arithmetic mode                      ; 51                        ;
;                                             ;                           ;
; Total registers*                            ; 106 / 10,744 ( &lt; 1 % )    ;
;     -- Dedicated logic registers            ; 106 / 10,320 ( 1 % )      ;
;     -- I/O registers                        ; 0 / 424 ( 0 % )           ;
;                                             ;                           ;
; Total LABs:  partially or completely used   ; 33 / 645 ( 5 % )          ;
; Virtual pins                                ; 0                         ;
; I/O pins                                    ; 43 / 95 ( 45 % )          ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )            ;
;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )             ;
;                                             ;                           ;
; Global signals                              ; 2                         ;
; M9Ks                                        ; 8 / 46 ( 17 % )           ;
; Total block memory bits                     ; 65,536 / 423,936 ( 15 % ) ;
; Total block memory implementation bits      ; 73,728 / 423,936 ( 17 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 46 ( 0 % )            ;
; PLLs                                        ; 0 / 2 ( 0 % )             ;
; Global clocks                               ; 2 / 10 ( 20 % )           ;
; JTAGs                                       ; 0 / 1 ( 0 % )             ;
; CRC blocks                                  ; 0 / 1 ( 0 % )             ;
; ASMI blocks                                 ; 0 / 1 ( 0 % )             ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )             ;
; Average interconnect usage (total/H/V)      ; 1% / 1% / 1%              ;
; Peak interconnect usage (total/H/V)         ; 4% / 2% / 5%              ;
; Maximum fan-out                             ; 113                       ;
; Highest non-global fan-out                  ; 45                        ;
; Total fan-out                               ; 1440                      ;
; Average fan-out                             ; 2.96                      ;
+---------------------------------------------+---------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                        ;
+---------------------------------------------+---------------------+--------------------------------+
; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
+---------------------------------------------+---------------------+--------------------------------+
; Difficulty Clustering Region                ; Low                 ; Low                            ;
;                                             ;                     ;                                ;
; Total logic elements                        ; 287 / 10320 ( 3 % ) ; 0 / 10320 ( 0 % )              ;
;     -- Combinational with no register       ; 181                 ; 0                              ;
;     -- Register only                        ; 41                  ; 0                              ;
;     -- Combinational with a register        ; 65                  ; 0                              ;
;                                             ;                     ;                                ;
; Logic element usage by number of LUT inputs ;                     ;                                ;
;     -- 4 input functions                    ; 138                 ; 0                              ;
;     -- 3 input functions                    ; 29                  ; 0                              ;
;     -- &lt;=2 input functions                  ; 79                  ; 0                              ;
;     -- Register only                        ; 41                  ; 0                              ;
;                                             ;                     ;                                ;
; Logic elements by mode                      ;                     ;                                ;
;     -- normal mode                          ; 195                 ; 0                              ;
;     -- arithmetic mode                      ; 51                  ; 0                              ;
;                                             ;                     ;                                ;
; Total registers                             ; 106                 ; 0                              ;
;     -- Dedicated logic registers            ; 106 / 10320 ( 1 % ) ; 0 / 10320 ( 0 % )              ;
;     -- I/O registers                        ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Total LABs:  partially or completely used   ; 33 / 645 ( 5 % )    ; 0 / 645 ( 0 % )                ;
;                                             ;                     ;                                ;
; Virtual pins                                ; 0                   ; 0                              ;
; I/O pins                                    ; 43                  ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 0 / 46 ( 0 % )      ; 0 / 46 ( 0 % )                 ;
; Total memory bits                           ; 65536               ; 0                              ;
; Total RAM block bits                        ; 73728               ; 0                              ;
; M9K                                         ; 8 / 46 ( 17 % )     ; 0 / 46 ( 0 % )                 ;
; Clock control block                         ; 2 / 12 ( 16 % )     ; 0 / 12 ( 0 % )                 ;
;                                             ;                     ;                                ;
; Connections                                 ;                     ;                                ;
;     -- Input Connections                    ; 0                   ; 0                              ;
;     -- Registered Input Connections         ; 0                   ; 0                              ;
;     -- Output Connections                   ; 0                   ; 0                              ;
;     -- Registered Output Connections        ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Internal Connections                        ;                     ;                                ;
;     -- Total Connections                    ; 1452                ; 5                              ;
;     -- Registered Connections               ; 600                 ; 0                              ;
;                                             ;                     ;                                ;
; External Connections                        ;                     ;                                ;
;     -- Top                                  ; 0                   ; 0                              ;
;     -- hard_block:auto_generated_inst       ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Partition Interface                         ;                     ;                                ;
;     -- Input Ports                          ; 27                  ; 0                              ;
;     -- Output Ports                         ; 16                  ; 0                              ;
;     -- Bidir Ports                          ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Registered Ports                            ;                     ;                                ;
;     -- Registered Input Ports               ; 0                   ; 0                              ;
;     -- Registered Output Ports              ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Port Connectivity                           ;                     ;                                ;
;     -- Input Ports driven by GND            ; 0                   ; 0                              ;
;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
;     -- Input Ports with no Source           ; 0                   ; 0                              ;
;     -- Output Ports with no Source          ; 0                   ; 0                              ;
;     -- Input Ports with no Fanout           ; 0                   ; 0                              ;
;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
+---------------------------------------------+---------------------+--------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                      ;
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; ApdDel[0]  ; 39    ; 3        ; 1            ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[10] ; 77    ; 5        ; 34           ; 4            ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[1]  ; 43    ; 3        ; 5            ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[2]  ; 46    ; 3        ; 7            ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[3]  ; 50    ; 3        ; 13           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[4]  ; 58    ; 4        ; 21           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[5]  ; 60    ; 4        ; 23           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[6]  ; 65    ; 4        ; 28           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[7]  ; 67    ; 4        ; 30           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[8]  ; 69    ; 4        ; 30           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; ApdDel[9]  ; 72    ; 4        ; 32           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[0]     ; 42    ; 3        ; 3            ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[10]    ; 79    ; 5        ; 34           ; 7            ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[1]     ; 44    ; 3        ; 5            ; 0            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[2]     ; 49    ; 3        ; 13           ; 0            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[3]     ; 51    ; 3        ; 16           ; 0            ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[4]     ; 59    ; 4        ; 23           ; 0            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[5]     ; 64    ; 4        ; 25           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[6]     ; 66    ; 4        ; 28           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[7]     ; 68    ; 4        ; 30           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[8]     ; 71    ; 4        ; 32           ; 0            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Apd[9]     ; 76    ; 5        ; 34           ; 4            ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Clk        ; 22    ; 1        ; 0            ; 11           ; 0            ; 113                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Rcmd[0]    ; 103   ; 6        ; 34           ; 18           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Rcmd[1]    ; 100   ; 6        ; 34           ; 17           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Rcmd[2]    ; 99    ; 6        ; 34           ; 17           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
; Rcs        ; 98    ; 6        ; 34           ; 17           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Rdat[0]  ; 135   ; 8        ; 11           ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[10] ; 112   ; 7        ; 28           ; 24           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[11] ; 111   ; 7        ; 30           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[12] ; 110   ; 7        ; 30           ; 24           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[13] ; 106   ; 6        ; 34           ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[14] ; 105   ; 6        ; 34           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[15] ; 104   ; 6        ; 34           ; 18           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[1]  ; 133   ; 8        ; 13           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[2]  ; 132   ; 8        ; 13           ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[3]  ; 125   ; 7        ; 18           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[4]  ; 121   ; 7        ; 23           ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[5]  ; 120   ; 7        ; 23           ; 24           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[6]  ; 119   ; 7        ; 23           ; 24           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[7]  ; 115   ; 7        ; 28           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[8]  ; 114   ; 7        ; 28           ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Rdat[9]  ; 113   ; 7        ; 28           ; 24           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                         ;
+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
; 6        ; DIFFIO_L1n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
; 8        ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
; 9        ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
; 12       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
; 13       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
; 14       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
; 21       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
; 92       ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
; 94       ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
; 96       ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
; 97       ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
; 97       ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
; 98       ; DIFFIO_R4n, INIT_DONE       ; Use as regular IO        ; Rcs                     ; Dual Purpose Pin          ;
; 99       ; DIFFIO_R4p, CRC_ERROR       ; Use as regular IO        ; Rcmd[2]                 ; Dual Purpose Pin          ;
; 101      ; DIFFIO_R3n, nCEO            ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
; 103      ; DIFFIO_R3p, CLKUSR          ; Use as regular IO        ; Rcmd[0]                 ; Dual Purpose Pin          ;
; 132      ; DIFFIO_T10n, DATA2          ; Use as regular IO        ; Rdat[2]                 ; Dual Purpose Pin          ;
; 133      ; DIFFIO_T10p, DATA3          ; Use as regular IO        ; Rdat[1]                 ; Dual Purpose Pin          ;
+----------+-----------------------------+--------------------------+-------------------------+---------------------------+


+------------------------------------------------------------+
; I/O Bank Usage                                             ;
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1        ; 5 / 13 ( 38 % )  ; 3.3V          ; --           ;
; 2        ; 0 / 8 ( 0 % )    ; 3.3V          ; --           ;
; 3        ; 8 / 11 ( 73 % )  ; 3.3V          ; --           ;
; 4        ; 11 / 14 ( 79 % ) ; 3.3V          ; --           ;
; 5        ; 3 / 14 ( 21 % )  ; 3.3V          ; --           ;
; 6        ; 8 / 10 ( 80 % )  ; 3.3V          ; --           ;
; 7        ; 10 / 13 ( 77 % ) ; 3.3V          ; --           ;
; 8        ; 3 / 12 ( 25 % )  ; 3.3V          ; --           ;
+----------+------------------+---------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                                        ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1        ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 2        ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 3        ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 4        ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 5        ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 6        ; 5          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
; 7        ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 8        ; 7          ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
; 9        ; 9          ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 10       ; 13         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 11       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 12       ; 15         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
; 13       ; 16         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
; 14       ; 17         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 15       ; 18         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 16       ; 19         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 17       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 18       ; 20         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 19       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 20       ; 21         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
; 21       ; 22         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 22       ; 23         ; 1        ; Clk                                                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 23       ; 24         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 24       ; 25         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 25       ; 26         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 26       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 27       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 28       ; 31         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 29       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 30       ; 34         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 31       ; 36         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 32       ; 39         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 33       ; 40         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 34       ; 41         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 35       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 36       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 37       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 38       ; 45         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 39       ; 46         ; 3        ; ApdDel[0]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 40       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 41       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 42       ; 52         ; 3        ; Apd[0]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 43       ; 53         ; 3        ; ApdDel[1]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 44       ; 54         ; 3        ; Apd[1]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 45       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 46       ; 58         ; 3        ; ApdDel[2]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 47       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 48       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 49       ; 68         ; 3        ; Apd[2]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 50       ; 69         ; 3        ; ApdDel[3]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 51       ; 70         ; 3        ; Apd[3]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 52       ; 72         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 53       ; 73         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 54       ; 74         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 55       ; 75         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 56       ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 57       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 58       ; 80         ; 4        ; ApdDel[4]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 59       ; 83         ; 4        ; Apd[4]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 60       ; 84         ; 4        ; ApdDel[5]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 61       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 62       ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 63       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 64       ; 89         ; 4        ; Apd[5]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 65       ; 90         ; 4        ; ApdDel[6]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 66       ; 93         ; 4        ; Apd[6]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 67       ; 94         ; 4        ; ApdDel[7]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 68       ; 96         ; 4        ; Apd[7]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 69       ; 97         ; 4        ; ApdDel[8]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 70       ; 98         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 71       ; 99         ; 4        ; Apd[8]                                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 72       ; 100        ; 4        ; ApdDel[9]                                                 ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 73       ; 102        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 74       ; 103        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 75       ; 104        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 76       ; 106        ; 5        ; Apd[9]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 77       ; 107        ; 5        ; ApdDel[10]                                                ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 78       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 79       ; 111        ; 5        ; Apd[10]                                                   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 80       ; 113        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 81       ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 82       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 83       ; 117        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 84       ; 118        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 85       ; 119        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 86       ; 120        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 87       ; 121        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 88       ; 125        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 89       ; 126        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 90       ; 127        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 91       ; 128        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 92       ; 129        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 93       ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 94       ; 130        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 95       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 96       ; 131        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 97       ; 132        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 97       ; 133        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 98       ; 136        ; 6        ; Rcs                                                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 99       ; 137        ; 6        ; Rcmd[2]                                                   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 100      ; 138        ; 6        ; Rcmd[1]                                                   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 101      ; 139        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
; 102      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 103      ; 140        ; 6        ; Rcmd[0]                                                   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 104      ; 141        ; 6        ; Rdat[15]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 105      ; 142        ; 6        ; Rdat[14]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 106      ; 146        ; 6        ; Rdat[13]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 107      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 108      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 109      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 110      ; 152        ; 7        ; Rdat[12]                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 111      ; 154        ; 7        ; Rdat[11]                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 112      ; 155        ; 7        ; Rdat[10]                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 113      ; 156        ; 7        ; Rdat[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 114      ; 157        ; 7        ; Rdat[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 115      ; 158        ; 7        ; Rdat[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 116      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 117      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 118      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 119      ; 163        ; 7        ; Rdat[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 120      ; 164        ; 7        ; Rdat[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 121      ; 165        ; 7        ; Rdat[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 122      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 123      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 124      ; 173        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 125      ; 174        ; 7        ; Rdat[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 126      ; 175        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 127      ; 176        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 128      ; 177        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 129      ; 178        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 130      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 131      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 132      ; 181        ; 8        ; Rdat[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 133      ; 182        ; 8        ; Rdat[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 134      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 135      ; 185        ; 8        ; Rdat[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; 136      ; 187        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 137      ; 190        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 138      ; 191        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 139      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 140      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 141      ; 195        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 142      ; 201        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 143      ; 202        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 144      ; 203        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; EPAD     ;            ;          ; GND                                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                   ;
+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                          ; Library Name ;
+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------+--------------+
; |CoincidenceCounter                       ; 287 (13)    ; 106 (8)                   ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 43   ; 0            ; 181 (6)      ; 41 (4)            ; 65 (2)           ; |CoincidenceCounter                                                                                          ; work         ;
;    |CoinCounter:inst2|                    ; 29 (29)     ; 21 (21)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (8)        ; 13 (13)           ; 8 (8)            ; |CoincidenceCounter|CoinCounter:inst2                                                                        ; work         ;
;    |CoincidenceAsyncInput:inst1|          ; 56 (49)     ; 27 (27)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 29 (22)      ; 24 (24)           ; 3 (2)            ; |CoincidenceCounter|CoincidenceAsyncInput:inst1                                                              ; work         ;
;       |lpm_or0:inst3|                     ; 4 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (0)        ; 0 (0)             ; 1 (0)            ; |CoincidenceCounter|CoincidenceAsyncInput:inst1|lpm_or0:inst3                                                ; work         ;
;          |lpm_or:lpm_or_component|        ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 1 (1)            ; |CoincidenceCounter|CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component                        ; work         ;
;       |lpm_or0:inst4|                     ; 4 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 0 (0)            ; |CoincidenceCounter|CoincidenceAsyncInput:inst1|lpm_or0:inst4                                                ; work         ;
;          |lpm_or:lpm_or_component|        ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |CoincidenceCounter|CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component                        ; work         ;
;    |RabbitControl:inst|                   ; 159 (159)   ; 50 (50)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 106 (106)    ; 0 (0)             ; 53 (53)          ; |CoincidenceCounter|RabbitControl:inst                                                                       ; work         ;
;    |lpm_add_sub0:inst4|                   ; 32 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (0)       ; 0 (0)             ; 1 (0)            ; |CoincidenceCounter|lpm_add_sub0:inst4                                                                       ; work         ;
;       |lpm_add_sub:lpm_add_sub_component| ; 32 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (0)       ; 0 (0)             ; 1 (0)            ; |CoincidenceCounter|lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component                                     ; work         ;
;          |add_sub_api:auto_generated|     ; 32 (32)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 0 (0)             ; 1 (1)            ; |CoincidenceCounter|lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated          ; work         ;
;    |lpm_ram_dp0:Counter_Block|            ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; |CoincidenceCounter|lpm_ram_dp0:Counter_Block                                                                ; work         ;
;       |altsyncram:altsyncram_component|   ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; |CoincidenceCounter|lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component                                ; work         ;
;          |altsyncram_16f2:auto_generated| ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |CoincidenceCounter|lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated ; work         ;
+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                        ;
+------------+----------+---------------+---------------+-----------------------+-----+------+
; Name       ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
+------------+----------+---------------+---------------+-----------------------+-----+------+
; Rdat[15]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[14]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[13]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[12]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[11]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[10]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[9]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[8]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[7]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[6]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[5]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[4]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[3]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[2]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[1]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Rdat[0]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Clk        ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; Rcmd[2]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Rcmd[1]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Rcs        ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Rcmd[0]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; ApdDel[2]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; ApdDel[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; ApdDel[9]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; ApdDel[8]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; ApdDel[7]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; ApdDel[6]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; ApdDel[5]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; ApdDel[4]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; ApdDel[3]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; ApdDel[1]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; ApdDel[10] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[10]    ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; Apd[9]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[8]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[7]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[6]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[5]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[4]     ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; Apd[3]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[2]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[1]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Apd[0]     ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+------------+----------+---------------+---------------+-----------------------+-----+------+


+-------------------------------------------------------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                                                                          ;
+-------------------------------------------------------------------------------------------+-------------------+---------+
; Source Pin / Fanout                                                                       ; Pad To Core Index ; Setting ;
+-------------------------------------------------------------------------------------------+-------------------+---------+
; Clk                                                                                       ;                   ;         ;
; Rcmd[2]                                                                                   ;                   ;         ;
;      - inst6[2]                                                                           ; 0                 ; 6       ;
; Rcmd[1]                                                                                   ;                   ;         ;
;      - inst6[1]~feeder                                                                    ; 0                 ; 6       ;
; Rcs                                                                                       ;                   ;         ;
;      - inst8~feeder                                                                       ; 0                 ; 6       ;
; Rcmd[0]                                                                                   ;                   ;         ;
;      - inst6[0]~feeder                                                                    ; 0                 ; 6       ;
; ApdDel[2]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]   ; 0                 ; 6       ;
; ApdDel[0]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]   ; 0                 ; 0       ;
; ApdDel[9]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~1 ; 1                 ; 6       ;
; ApdDel[8]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~1 ; 0                 ; 6       ;
; ApdDel[7]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~1 ; 0                 ; 6       ;
; ApdDel[6]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~0 ; 1                 ; 6       ;
; ApdDel[5]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~0 ; 0                 ; 6       ;
; ApdDel[4]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~0 ; 1                 ; 6       ;
; ApdDel[3]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~0 ; 0                 ; 6       ;
; ApdDel[1]                                                                                 ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~2 ; 1                 ; 6       ;
; ApdDel[10]                                                                                ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~2 ; 0                 ; 6       ;
; Apd[10]                                                                                   ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~0 ; 1                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[10]                                            ; 1                 ; 6       ;
; Apd[9]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~0 ; 0                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[9]                                             ; 0                 ; 6       ;
; Apd[8]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~0 ; 0                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[8]                                             ; 0                 ; 6       ;
; Apd[7]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~0 ; 0                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[7]                                             ; 0                 ; 6       ;
; Apd[6]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~1 ; 0                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[6]                                             ; 0                 ; 6       ;
; Apd[5]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~1 ; 0                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[5]                                             ; 0                 ; 6       ;
; Apd[4]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~1 ; 1                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[4]                                             ; 1                 ; 6       ;
; Apd[3]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~1 ; 0                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[3]                                             ; 0                 ; 6       ;
; Apd[2]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~3 ; 0                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[2]                                             ; 0                 ; 6       ;
; Apd[1]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~2 ; 0                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[1]                                             ; 0                 ; 6       ;
; Apd[0]                                                                                    ;                   ;         ;
;      - CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~2 ; 1                 ; 6       ;
;      - CoincidenceAsyncInput:inst1|Stretch[0]                                             ; 1                 ; 6       ;
+-------------------------------------------------------------------------------------------+-------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                                               ;
+----------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
; Name                                                                             ; Location           ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+----------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
; Clk                                                                              ; PIN_22             ; 113     ; Clock        ; yes    ; Global Clock         ; GCLK4            ; --                        ;
; CoinCounter:inst2|ApdsReset                                                      ; FF_X32_Y10_N17     ; 24      ; Async. clear ; no     ; --                   ; --               ; --                        ;
; CoinCounter:inst2|MemAdd[0]~0                                                    ; LCCOMB_X28_Y14_N10 ; 12      ; Clock enable ; no     ; --                   ; --               ; --                        ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3                                            ; FF_X33_Y12_N7      ; 11      ; Latch enable ; yes    ; Global Clock         ; GCLK9            ; --                        ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10] ; LCCOMB_X2_Y1_N16   ; 2       ; Clock        ; no     ; --                   ; --               ; --                        ;
; RabbitControl:inst|MemAdd[0]~24                                                  ; LCCOMB_X24_Y14_N2  ; 11      ; Sync. clear  ; no     ; --                   ; --               ; --                        ;
; RabbitControl:inst|MemAdd[7]~27                                                  ; LCCOMB_X24_Y14_N18 ; 11      ; Clock enable ; no     ; --                   ; --               ; --                        ;
; RabbitControl:inst|MemWrEn                                                       ; FF_X24_Y14_N31     ; 9       ; Write enable ; no     ; --                   ; --               ; --                        ;
; RabbitControl:inst|MemWr[16]~33                                                  ; LCCOMB_X25_Y14_N14 ; 32      ; Clock enable ; no     ; --                   ; --               ; --                        ;
; inst10~_Duplicate_1                                                              ; LCCOMB_X26_Y10_N16 ; 1       ; Write enable ; no     ; --                   ; --               ; --                        ;
; inst10~_Duplicate_11                                                             ; LCCOMB_X26_Y11_N10 ; 1       ; Write enable ; no     ; --                   ; --               ; --                        ;
; inst10~_Duplicate_13                                                             ; LCCOMB_X28_Y14_N0  ; 1       ; Write enable ; no     ; --                   ; --               ; --                        ;
; inst10~_Duplicate_15                                                             ; LCCOMB_X28_Y14_N6  ; 1       ; Write enable ; no     ; --                   ; --               ; --                        ;
; inst10~_Duplicate_3                                                              ; LCCOMB_X26_Y12_N30 ; 1       ; Write enable ; no     ; --                   ; --               ; --                        ;
; inst10~_Duplicate_5                                                              ; LCCOMB_X26_Y17_N30 ; 1       ; Write enable ; no     ; --                   ; --               ; --                        ;
; inst10~_Duplicate_7                                                              ; LCCOMB_X26_Y13_N6  ; 1       ; Write enable ; no     ; --                   ; --               ; --                        ;
; inst10~_Duplicate_9                                                              ; LCCOMB_X26_Y16_N6  ; 1       ; Write enable ; no     ; --                   ; --               ; --                        ;
; inst7[2]                                                                         ; FF_X25_Y14_N17     ; 45      ; Sync. clear  ; no     ; --                   ; --               ; --                        ;
+----------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global &amp; Other Fast Signals                                                                                                                                                  ;
+---------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name                                  ; Location      ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+---------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Clk                                   ; PIN_22        ; 113     ; 21                                   ; Global Clock         ; GCLK4            ; --                        ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; FF_X33_Y12_N7 ; 11      ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+---------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                                                     ;
+-----------------------------------------------------------------------------------------------------------+---------+
; Name                                                                                                      ; Fan-Out ;
+-----------------------------------------------------------------------------------------------------------+---------+
; inst7[2]                                                                                                  ; 45      ;
; RabbitControl:inst|MemAdd[1]                                                                              ; 38      ;
; RabbitControl:inst|MemAdd[2]                                                                              ; 37      ;
; RabbitControl:inst|MemWr[16]~33                                                                           ; 32      ;
; RabbitControl:inst|MemAdd[3]                                                                              ; 32      ;
; RabbitControl:inst|MemAdd[4]                                                                              ; 31      ;
; RabbitControl:inst|MemAdd[0]                                                                              ; 30      ;
; CoinCounter:inst2|ApdsReset                                                                               ; 24      ;
; RabbitControl:inst|MemAdd[5]                                                                              ; 21      ;
; RabbitControl:inst|HighWordOnBus                                                                          ; 19      ;
; RabbitControl:inst|MemAdd[10]                                                                             ; 19      ;
; RabbitControl:inst|always0~0                                                                              ; 16      ;
; RabbitControl:inst|Equal2~0                                                                               ; 15      ;
; RabbitControl:inst|MemAdd[9]                                                                              ; 14      ;
; RabbitControl:inst|MemAdd[8]                                                                              ; 14      ;
; RabbitControl:inst|MemAdd[7]                                                                              ; 14      ;
; RabbitControl:inst|MemAdd[6]                                                                              ; 14      ;
; RabbitControl:inst|WideNor0~37                                                                            ; 12      ;
; RabbitControl:inst|WideNor0~36                                                                            ; 12      ;
; CoinCounter:inst2|MemAdd[0]~0                                                                             ; 12      ;
; RabbitControl:inst|MemAdd[7]~27                                                                           ; 11      ;
; RabbitControl:inst|MemAdd[0]~24                                                                           ; 11      ;
; RabbitControl:inst|Equal1~2                                                                               ; 10      ;
; inst7[0]                                                                                                  ; 10      ;
; inst7[1]                                                                                                  ; 10      ;
; RabbitControl:inst|Equal11~1                                                                              ; 9       ;
; RabbitControl:inst|MemWrEn                                                                                ; 9       ;
; CoinCounter:inst2|MemInc                                                                                  ; 9       ;
; CoinCounter:inst2|MemAdd[10]                                                                              ; 8       ;
; CoinCounter:inst2|MemAdd[9]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[8]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[7]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[6]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[5]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[4]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[3]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[2]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[1]                                                                               ; 8       ;
; CoinCounter:inst2|MemAdd[0]                                                                               ; 8       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~62                   ; 8       ;
; RabbitControl:inst|Selector11~4                                                                           ; 7       ;
; RabbitControl:inst|WideNor0~31                                                                            ; 7       ;
; RabbitControl:inst|Equal8~0                                                                               ; 7       ;
; RabbitControl:inst|Equal1~0                                                                               ; 7       ;
; inst9                                                                                                     ; 7       ;
; RabbitControl:inst|WideOr6~2                                                                              ; 6       ;
; RabbitControl:inst|Equal7~0                                                                               ; 6       ;
; RabbitControl:inst|Equal9~0                                                                               ; 6       ;
; RabbitControl:inst|Equal1~1                                                                               ; 6       ;
; RabbitControl:inst|RunEn                                                                                  ; 6       ;
; RabbitControl:inst|Equal1~3                                                                               ; 5       ;
; RabbitControl:inst|Equal10~0                                                                              ; 5       ;
; RabbitControl:inst|Equal11~0                                                                              ; 5       ;
; RabbitControl:inst|TestDataState[0]                                                                       ; 5       ;
; CoinCounter:inst2|CoinState.0001                                                                          ; 4       ;
; RabbitControl:inst|Equal27~0                                                                              ; 4       ;
; RabbitControl:inst|Equal9~1                                                                               ; 4       ;
; RabbitControl:inst|Equal7~1                                                                               ; 4       ;
; RabbitControl:inst|Equal33~0                                                                              ; 4       ;
; RabbitControl:inst|Equal19~0                                                                              ; 4       ;
; RabbitControl:inst|Equal41~1                                                                              ; 4       ;
; RabbitControl:inst|Equal17~0                                                                              ; 4       ;
; RabbitControl:inst|Equal3~1                                                                               ; 4       ;
; RabbitControl:inst|TestDataState[1]~1                                                                     ; 4       ;
; CoincidenceAsyncInput:inst1|CDC_OFF2                                                                      ; 4       ;
; RabbitControl:inst|TestDataState[1]                                                                       ; 4       ;
; CoinCounter:inst2|CoinState.0000                                                                          ; 4       ;
; RabbitControl:inst|Equal6~0                                                                               ; 3       ;
; RabbitControl:inst|Equal34~0                                                                              ; 3       ;
; RabbitControl:inst|Equal41~2                                                                              ; 3       ;
; RabbitControl:inst|Equal3~0                                                                               ; 3       ;
; RabbitControl:inst|Equal41~0                                                                              ; 3       ;
; CoinCounter:inst2|CoinState.0101                                                                          ; 3       ;
; RabbitControl:inst|LastCs                                                                                 ; 3       ;
; Apd[0]~input                                                                                              ; 2       ;
; Apd[1]~input                                                                                              ; 2       ;
; Apd[2]~input                                                                                              ; 2       ;
; Apd[3]~input                                                                                              ; 2       ;
; Apd[4]~input                                                                                              ; 2       ;
; Apd[5]~input                                                                                              ; 2       ;
; Apd[6]~input                                                                                              ; 2       ;
; Apd[7]~input                                                                                              ; 2       ;
; Apd[8]~input                                                                                              ; 2       ;
; Apd[9]~input                                                                                              ; 2       ;
; Apd[10]~input                                                                                             ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[10]                                                                   ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[9]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[8]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[7]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[6]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[5]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[4]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[3]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[2]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[1]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Stretch[0]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[10]                                                                   ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[9]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[8]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[7]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[6]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[5]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[4]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[3]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[2]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[1]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|Capture[0]                                                                    ; 2       ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]                          ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_OFF1                                                                      ; 2       ;
; CoinCounter:inst2|Equal0~3                                                                                ; 2       ;
; CoinCounter:inst2|CoinState.0100                                                                          ; 2       ;
; RabbitControl:inst|Equal6~1                                                                               ; 2       ;
; RabbitControl:inst|WideOr2~0                                                                              ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[10]                                                                 ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]                                                                  ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]                                                                  ; 2       ;
; CoinCounter:inst2|CoinState.0111                                                                          ; 2       ;
; RabbitControl:inst|HighWordOnBus~1                                                                        ; 2       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[0]           ; 2       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3~feeder                                                              ; 1       ;
; inst10~_Duplicate_15                                                                                      ; 1       ;
; inst10~_Duplicate_13                                                                                      ; 1       ;
; inst10~_Duplicate_11                                                                                      ; 1       ;
; inst10~_Duplicate_9                                                                                       ; 1       ;
; inst10~_Duplicate_7                                                                                       ; 1       ;
; inst10~_Duplicate_5                                                                                       ; 1       ;
; inst10~_Duplicate_3                                                                                       ; 1       ;
; inst10~_Duplicate_1                                                                                       ; 1       ;
; ApdDel[10]~input                                                                                          ; 1       ;
; ApdDel[1]~input                                                                                           ; 1       ;
; ApdDel[3]~input                                                                                           ; 1       ;
; ApdDel[4]~input                                                                                           ; 1       ;
; ApdDel[5]~input                                                                                           ; 1       ;
; ApdDel[6]~input                                                                                           ; 1       ;
; ApdDel[7]~input                                                                                           ; 1       ;
; ApdDel[8]~input                                                                                           ; 1       ;
; ApdDel[9]~input                                                                                           ; 1       ;
; ApdDel[0]~input                                                                                           ; 1       ;
; ApdDel[2]~input                                                                                           ; 1       ;
; Rcmd[0]~input                                                                                             ; 1       ;
; Rcs~input                                                                                                 ; 1       ;
; Rcmd[1]~input                                                                                             ; 1       ;
; Rcmd[2]~input                                                                                             ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[0]~_wirecell ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_OFF9~0                                                                    ; 1       ;
; RabbitControl:inst|WideNor0~39                                                                            ; 1       ;
; RabbitControl:inst|WideNor0~38                                                                            ; 1       ;
; RabbitControl:inst|Selector2~21                                                                           ; 1       ;
; RabbitControl:inst|Selector2~20                                                                           ; 1       ;
; RabbitControl:inst|WideNor0~14                                                                            ; 1       ;
; RabbitControl:inst|Selector2~3                                                                            ; 1       ;
; RabbitControl:inst|Selector2~19                                                                           ; 1       ;
; RabbitControl:inst|WideOr4~3                                                                              ; 1       ;
; RabbitControl:inst|WideOr4                                                                                ; 1       ;
; RabbitControl:inst|WideOr4~6                                                                              ; 1       ;
; RabbitControl:inst|WideOr4~8                                                                              ; 1       ;
; RabbitControl:inst|WideNor0~7                                                                             ; 1       ;
; RabbitControl:inst|WideNor0~10                                                                            ; 1       ;
; RabbitControl:inst|Equal28~0                                                                              ; 1       ;
; RabbitControl:inst|Equal5~0                                                                               ; 1       ;
; RabbitControl:inst|Equal26~0                                                                              ; 1       ;
; RabbitControl:inst|Equal29~2                                                                              ; 1       ;
; RabbitControl:inst|Selector9~3                                                                            ; 1       ;
; CoinCounter:inst2|Selector1~0                                                                             ; 1       ;
; CoinCounter:inst2|Selector4~1                                                                             ; 1       ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~3                        ; 1       ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~2                        ; 1       ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~1                        ; 1       ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~0                        ; 1       ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~2                        ; 1       ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~1                        ; 1       ;
; CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~0                        ; 1       ;
; CoinCounter:inst2|CoinState.0010                                                                          ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_OFF                                                                       ; 1       ;
; CoinCounter:inst2|CoinState.0011                                                                          ; 1       ;
; CoinCounter:inst2|Selector3~0                                                                             ; 1       ;
; CoinCounter:inst2|Selector4~0                                                                             ; 1       ;
; RabbitControl:inst|MemAdd[7]~48                                                                           ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[10]                                                                  ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[9]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[8]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[7]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[6]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[5]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[4]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[3]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[2]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[1]                                                                   ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_OFF9                                                                      ; 1       ;
; CoinCounter:inst2|Selector7~0                                                                             ; 1       ;
; CoinCounter:inst2|MemAdd[0]~1                                                                             ; 1       ;
; RabbitControl:inst|RunEn~1                                                                                ; 1       ;
; RabbitControl:inst|RunEn~0                                                                                ; 1       ;
; CoincidenceAsyncInput:inst1|CDC_CAPT[0]                                                                   ; 1       ;
; RabbitControl:inst|TestDataState[0]~3                                                                     ; 1       ;
; RabbitControl:inst|TestDataState[1]~2                                                                     ; 1       ;
; CoinCounter:inst2|Selector2~1                                                                             ; 1       ;
; CoinCounter:inst2|Equal0~2                                                                                ; 1       ;
; CoinCounter:inst2|Equal0~1                                                                                ; 1       ;
; CoinCounter:inst2|Equal0~0                                                                                ; 1       ;
; CoinCounter:inst2|Selector2~0                                                                             ; 1       ;
; CoinCounter:inst2|CoinState.0110                                                                          ; 1       ;
; RabbitControl:inst|Selector11~3                                                                           ; 1       ;
; RabbitControl:inst|Selector11~2                                                                           ; 1       ;
; RabbitControl:inst|WideOr12                                                                               ; 1       ;
; RabbitControl:inst|Selector10~1                                                                           ; 1       ;
; RabbitControl:inst|Selector10~0                                                                           ; 1       ;
; RabbitControl:inst|WideOr11                                                                               ; 1       ;
; RabbitControl:inst|Selector9~2                                                                            ; 1       ;
; RabbitControl:inst|WideOr10                                                                               ; 1       ;
; RabbitControl:inst|Selector8~1                                                                            ; 1       ;
; RabbitControl:inst|Selector8~0                                                                            ; 1       ;
; RabbitControl:inst|WideOr9                                                                                ; 1       ;
; RabbitControl:inst|WideOr9~0                                                                              ; 1       ;
; RabbitControl:inst|Selector7~1                                                                            ; 1       ;
; RabbitControl:inst|Selector7~0                                                                            ; 1       ;
; RabbitControl:inst|WideOr8                                                                                ; 1       ;
; RabbitControl:inst|Equal32~0                                                                              ; 1       ;
; RabbitControl:inst|Selector6~1                                                                            ; 1       ;
; RabbitControl:inst|Selector6~0                                                                            ; 1       ;
; RabbitControl:inst|Equal17~1                                                                              ; 1       ;
; RabbitControl:inst|WideOr7                                                                                ; 1       ;
; RabbitControl:inst|Selector5~1                                                                            ; 1       ;
; RabbitControl:inst|Selector5~0                                                                            ; 1       ;
; RabbitControl:inst|WideOr6                                                                                ; 1       ;
; RabbitControl:inst|Selector4~1                                                                            ; 1       ;
; RabbitControl:inst|Selector4~0                                                                            ; 1       ;
; RabbitControl:inst|WideOr5                                                                                ; 1       ;
; RabbitControl:inst|Selector3~1                                                                            ; 1       ;
; RabbitControl:inst|Selector3~0                                                                            ; 1       ;
; RabbitControl:inst|Selector2~18                                                                           ; 1       ;
; RabbitControl:inst|WideOr3                                                                                ; 1       ;
; RabbitControl:inst|Selector1~1                                                                            ; 1       ;
; RabbitControl:inst|Selector1~0                                                                            ; 1       ;
; RabbitControl:inst|MemWr~35                                                                               ; 1       ;
; RabbitControl:inst|Selector0~1                                                                            ; 1       ;
; RabbitControl:inst|WideNor0~35                                                                            ; 1       ;
; RabbitControl:inst|WideNor0~34                                                                            ; 1       ;
; RabbitControl:inst|WideNor0~33                                                                            ; 1       ;
; RabbitControl:inst|Equal33~1                                                                              ; 1       ;
; RabbitControl:inst|WideNor0~32                                                                            ; 1       ;
; RabbitControl:inst|Equal20~0                                                                              ; 1       ;
; RabbitControl:inst|Equal3~2                                                                               ; 1       ;
; RabbitControl:inst|Equal18~0                                                                              ; 1       ;
; RabbitControl:inst|Selector0~0                                                                            ; 1       ;
; RabbitControl:inst|WideOr2                                                                                ; 1       ;
; RabbitControl:inst|WideOr16                                                                               ; 1       ;
; RabbitControl:inst|WideOr1~0                                                                              ; 1       ;
; RabbitControl:inst|WideOr15                                                                               ; 1       ;
; RabbitControl:inst|WideOr0~0                                                                              ; 1       ;
; RabbitControl:inst|WideOr14~0                                                                             ; 1       ;
; RabbitControl:inst|MemWr~34                                                                               ; 1       ;
; RabbitControl:inst|LastCs~0                                                                               ; 1       ;
; RabbitControl:inst|WideOr13                                                                               ; 1       ;
; RabbitControl:inst|MemAdd[7]~26                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[7]~25                                                                           ; 1       ;
; RabbitControl:inst|TestDataState[0]~0                                                                     ; 1       ;
; RabbitControl:inst|MemWr~32                                                                               ; 1       ;
; RabbitControl:inst|MemWrEn~2                                                                              ; 1       ;
; RabbitControl:inst|MemWrEn~1                                                                              ; 1       ;
; RabbitControl:inst|MemWrEn~0                                                                              ; 1       ;
; CoinCounter:inst2|Selector0~0                                                                             ; 1       ;
; inst6[0]                                                                                                  ; 1       ;
; inst8                                                                                                     ; 1       ;
; inst6[1]                                                                                                  ; 1       ;
; inst6[2]                                                                                                  ; 1       ;
; RabbitControl:inst|HighWordOnBus~3                                                                        ; 1       ;
; RabbitControl:inst|HighWordOnBus~2                                                                        ; 1       ;
; RabbitControl:inst|HighWordOnBus~0                                                                        ; 1       ;
; RabbitControl:inst|Rdat[0]~15                                                                             ; 1       ;
; RabbitControl:inst|Rdat[1]~14                                                                             ; 1       ;
; RabbitControl:inst|Rdat[2]~13                                                                             ; 1       ;
; RabbitControl:inst|Rdat[3]~12                                                                             ; 1       ;
; RabbitControl:inst|Rdat[4]~11                                                                             ; 1       ;
; RabbitControl:inst|Rdat[5]~10                                                                             ; 1       ;
; RabbitControl:inst|Rdat[6]~9                                                                              ; 1       ;
; RabbitControl:inst|Rdat[7]~8                                                                              ; 1       ;
; RabbitControl:inst|Rdat[8]~7                                                                              ; 1       ;
; RabbitControl:inst|Rdat[9]~6                                                                              ; 1       ;
; RabbitControl:inst|Rdat[10]~5                                                                             ; 1       ;
; RabbitControl:inst|Rdat[11]~4                                                                             ; 1       ;
; RabbitControl:inst|Rdat[12]~3                                                                             ; 1       ;
; RabbitControl:inst|Rdat[13]~2                                                                             ; 1       ;
; RabbitControl:inst|Rdat[14]~1                                                                             ; 1       ;
; RabbitControl:inst|Rdat[15]~0                                                                             ; 1       ;
; RabbitControl:inst|Add2~20                                                                                ; 1       ;
; RabbitControl:inst|Add2~19                                                                                ; 1       ;
; RabbitControl:inst|Add2~18                                                                                ; 1       ;
; RabbitControl:inst|Add2~17                                                                                ; 1       ;
; RabbitControl:inst|Add2~16                                                                                ; 1       ;
; RabbitControl:inst|Add2~15                                                                                ; 1       ;
; RabbitControl:inst|Add2~14                                                                                ; 1       ;
; RabbitControl:inst|Add2~13                                                                                ; 1       ;
; RabbitControl:inst|Add2~12                                                                                ; 1       ;
; RabbitControl:inst|Add2~11                                                                                ; 1       ;
; RabbitControl:inst|Add2~10                                                                                ; 1       ;
; RabbitControl:inst|Add2~9                                                                                 ; 1       ;
; RabbitControl:inst|Add2~8                                                                                 ; 1       ;
; RabbitControl:inst|Add2~7                                                                                 ; 1       ;
; RabbitControl:inst|Add2~6                                                                                 ; 1       ;
; RabbitControl:inst|Add2~5                                                                                 ; 1       ;
; RabbitControl:inst|Add2~4                                                                                 ; 1       ;
; RabbitControl:inst|Add2~3                                                                                 ; 1       ;
; RabbitControl:inst|Add2~2                                                                                 ; 1       ;
; RabbitControl:inst|Add2~1                                                                                 ; 1       ;
; RabbitControl:inst|MemAdd[10]~46                                                                          ; 1       ;
; RabbitControl:inst|MemAdd[9]~45                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[9]~44                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[8]~43                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[8]~42                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[7]~41                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[7]~40                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[6]~39                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[6]~38                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[5]~37                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[5]~36                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[4]~35                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[4]~34                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[3]~33                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[3]~32                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[2]~31                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[2]~30                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[1]~29                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[1]~28                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[0]~23                                                                           ; 1       ;
; RabbitControl:inst|MemAdd[0]~22                                                                           ; 1       ;
; RabbitControl:inst|MemWr[0]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[16]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[1]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[17]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[2]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[18]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[3]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[19]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[4]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[20]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[5]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[21]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[6]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[22]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[7]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[23]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[8]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[24]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[9]                                                                               ; 1       ;
; RabbitControl:inst|MemWr[25]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[10]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[26]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[11]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[27]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[12]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[28]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[13]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[29]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[14]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[30]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[15]                                                                              ; 1       ;
; RabbitControl:inst|MemWr[31]                                                                              ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~61                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~60                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~59                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~58                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~57                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~56                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~55                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~54                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~53                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~52                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~51                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~50                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~49                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~48                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~47                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~46                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~45                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~44                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~43                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~42                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~41                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~40                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~39                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~38                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~37                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~36                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~35                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~34                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~33                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~32                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~31                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~30                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~29                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~28                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~27                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~26                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~25                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~24                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~23                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~22                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~21                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~20                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~19                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~18                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~17                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~16                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~15                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~14                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~13                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~12                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~11                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~10                   ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~9                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~8                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~7                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~6                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~5                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~4                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~3                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~2                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~1                    ; 1       ;
; lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~0                    ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[1]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[16]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[17]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[1]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[16]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[17]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[0]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[3]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[18]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[19]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[3]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[18]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[19]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[2]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[2]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[5]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[20]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[21]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[5]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[20]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[21]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[4]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[4]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[7]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[22]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[23]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[7]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[22]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[23]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[6]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[6]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[9]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[24]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[25]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[9]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[24]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[25]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[8]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[8]           ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[11]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[26]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[27]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[11]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[26]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[27]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[10]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[10]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[13]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[28]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[29]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[13]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[28]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[29]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[12]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[12]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[15]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[30]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[31]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[15]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[30]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[31]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[14]          ; 1       ;
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[14]          ; 1       ;
+-----------------------------------------------------------------------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-----------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
; Name                                                                                                ; Type ; Mode           ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
+-----------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Single Clock ; 2048         ; 32           ; 2048         ; 32           ; yes                    ; no                      ; yes                    ; no                      ; 65536 ; 2048                        ; 32                          ; 2048                        ; 32                          ; 65536               ; 8    ; None ; M9K_X27_Y13_N0, M9K_X27_Y16_N0, M9K_X27_Y12_N0, M9K_X27_Y10_N0, M9K_X27_Y17_N0, M9K_X27_Y11_N0, M9K_X27_Y14_N0, M9K_X27_Y15_N0 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+-----------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


+------------------------------------------------+
; Routing Usage Summary                          ;
+-----------------------+------------------------+
; Routing Resource Type ; Usage                  ;
+-----------------------+------------------------+
; Block interconnects   ; 633 / 32,401 ( 2 % )   ;
; C16 interconnects     ; 17 / 1,326 ( 1 % )     ;
; C4 interconnects      ; 308 / 21,816 ( 1 % )   ;
; Direct links          ; 85 / 32,401 ( &lt; 1 % )  ;
; Global clocks         ; 2 / 10 ( 20 % )        ;
; Local interconnects   ; 113 / 10,320 ( 1 % )   ;
; R24 interconnects     ; 17 / 1,289 ( 1 % )     ;
; R4 interconnects      ; 267 / 28,186 ( &lt; 1 % ) ;
+-----------------------+------------------------+


+---------------------------------------------------------------------------+
; LAB Logic Elements                                                        ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 8.70) ; Number of LABs  (Total = 33) ;
+--------------------------------------------+------------------------------+
; 1                                          ; 8                            ;
; 2                                          ; 3                            ;
; 3                                          ; 1                            ;
; 4                                          ; 3                            ;
; 5                                          ; 1                            ;
; 6                                          ; 0                            ;
; 7                                          ; 0                            ;
; 8                                          ; 0                            ;
; 9                                          ; 1                            ;
; 10                                         ; 0                            ;
; 11                                         ; 1                            ;
; 12                                         ; 0                            ;
; 13                                         ; 1                            ;
; 14                                         ; 1                            ;
; 15                                         ; 2                            ;
; 16                                         ; 11                           ;
+--------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 0.91) ; Number of LABs  (Total = 33) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 1                            ;
; 1 Clock                            ; 18                           ;
; 1 Clock enable                     ; 6                            ;
; 1 Sync. clear                      ; 5                            ;
+------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Signals Sourced                                                         ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 11.52) ; Number of LABs  (Total = 33) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 6                            ;
; 2                                            ; 4                            ;
; 3                                            ; 2                            ;
; 4                                            ; 2                            ;
; 5                                            ; 1                            ;
; 6                                            ; 0                            ;
; 7                                            ; 1                            ;
; 8                                            ; 0                            ;
; 9                                            ; 0                            ;
; 10                                           ; 0                            ;
; 11                                           ; 0                            ;
; 12                                           ; 0                            ;
; 13                                           ; 1                            ;
; 14                                           ; 0                            ;
; 15                                           ; 1                            ;
; 16                                           ; 4                            ;
; 17                                           ; 2                            ;
; 18                                           ; 1                            ;
; 19                                           ; 1                            ;
; 20                                           ; 0                            ;
; 21                                           ; 0                            ;
; 22                                           ; 0                            ;
; 23                                           ; 1                            ;
; 24                                           ; 1                            ;
; 25                                           ; 1                            ;
; 26                                           ; 3                            ;
; 27                                           ; 1                            ;
+----------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 7.24) ; Number of LABs  (Total = 33) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 8                            ;
; 2                                               ; 3                            ;
; 3                                               ; 1                            ;
; 4                                               ; 3                            ;
; 5                                               ; 1                            ;
; 6                                               ; 0                            ;
; 7                                               ; 1                            ;
; 8                                               ; 1                            ;
; 9                                               ; 0                            ;
; 10                                              ; 2                            ;
; 11                                              ; 2                            ;
; 12                                              ; 5                            ;
; 13                                              ; 2                            ;
; 14                                              ; 1                            ;
; 15                                              ; 1                            ;
; 16                                              ; 1                            ;
; 17                                              ; 1                            ;
+-------------------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                         ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 10.12) ; Number of LABs  (Total = 33) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 0                            ;
; 2                                            ; 6                            ;
; 3                                            ; 2                            ;
; 4                                            ; 2                            ;
; 5                                            ; 2                            ;
; 6                                            ; 1                            ;
; 7                                            ; 0                            ;
; 8                                            ; 2                            ;
; 9                                            ; 1                            ;
; 10                                           ; 2                            ;
; 11                                           ; 4                            ;
; 12                                           ; 1                            ;
; 13                                           ; 3                            ;
; 14                                           ; 0                            ;
; 15                                           ; 1                            ;
; 16                                           ; 0                            ;
; 17                                           ; 1                            ;
; 18                                           ; 1                            ;
; 19                                           ; 0                            ;
; 20                                           ; 0                            ;
; 21                                           ; 1                            ;
; 22                                           ; 1                            ;
; 23                                           ; 0                            ;
; 24                                           ; 0                            ;
; 25                                           ; 0                            ;
; 26                                           ; 1                            ;
; 27                                           ; 0                            ;
; 28                                           ; 0                            ;
; 29                                           ; 0                            ;
; 30                                           ; 0                            ;
; 31                                           ; 0                            ;
; 32                                           ; 0                            ;
; 33                                           ; 1                            ;
+----------------------------------------------+------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 9     ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 21    ;
+----------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                                    ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass         ; 43        ; 0            ; 43        ; 0            ; 0            ; 43        ; 43        ; 0            ; 43        ; 43        ; 0            ; 0            ; 0            ; 0            ; 27           ; 0            ; 0            ; 27           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 43        ; 0            ; 0            ;
; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable ; 0         ; 43           ; 0         ; 43           ; 43           ; 0         ; 0         ; 43           ; 0         ; 0         ; 43           ; 43           ; 43           ; 43           ; 16           ; 43           ; 43           ; 16           ; 43           ; 43           ; 43           ; 43           ; 43           ; 43           ; 43           ; 43           ; 43           ; 0         ; 43           ; 43           ;
; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Rdat[15]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[14]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[13]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[12]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[11]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[10]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rdat[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Clk                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rcmd[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rcmd[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rcs                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Rcmd[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[9]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[8]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ApdDel[10]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[10]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[9]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[8]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[7]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[6]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[5]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[4]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Apd[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+---------------------------------------------------------------------------------------------+
; Fitter Device Options                                                                       ;
+------------------------------------------------------------------+--------------------------+
; Option                                                           ; Setting                  ;
+------------------------------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
; Enable INIT_DONE output                                          ; Off                      ;
; Configuration scheme                                             ; Active Serial            ;
; Error detection CRC                                              ; Off                      ;
; Enable open drain on CRC_ERROR pin                               ; Off                      ;
; Enable input tri-state on active configuration pins in user mode ; Off                      ;
; Configuration Voltage Level                                      ; Auto                     ;
; Force Configuration Voltage Level                                ; On                       ;
; nCEO                                                             ; As output driving ground ;
; Data[0]                                                          ; As input tri-stated      ;
; Data[1]/ASDO                                                     ; As input tri-stated      ;
; Data[7..2]                                                       ; Unreserved               ;
; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
; Other Active Parallel pins                                       ; Unreserved               ;
; DCLK                                                             ; As output driving ground ;
; Base pin-out file on sameframe device                            ; Off                      ;
+------------------------------------------------------------------+--------------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 °C   ;
; High Junction Temperature ; 85 °C  ;
+---------------------------+--------+


+----------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Summary                                    ;
+---------------------------------------+----------------------+-------------------+
; Source Clock(s)                       ; Destination Clock(s) ; Delay Added in ns ;
+---------------------------------------+----------------------+-------------------+
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk                  ; 4.0               ;
; Clk                                   ; Clk                  ; 1.7               ;
+---------------------------------------+----------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.


+--------------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Details                                                          ;
+-----------------------------------------+------------------------------------------+-------------------+
; Source Register                         ; Destination Register                     ; Delay Added in ns ;
+-----------------------------------------+------------------------------------------+-------------------+
; CoincidenceAsyncInput:inst1|Capture[5]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]  ; 0.508             ;
; CoincidenceAsyncInput:inst1|Capture[6]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]  ; 0.508             ;
; CoincidenceAsyncInput:inst1|Capture[0]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]  ; 0.508             ;
; CoincidenceAsyncInput:inst1|Capture[1]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]  ; 0.508             ;
; inst9                                   ; RabbitControl:inst|LastCs                ; 0.381             ;
; inst7[0]                                ; RabbitControl:inst|HighWordOnBus         ; 0.357             ;
; CoincidenceAsyncInput:inst1|Capture[2]  ; CoinCounter:inst2|MemAdd[2]              ; 0.277             ;
; CoincidenceAsyncInput:inst1|Capture[7]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]  ; 0.277             ;
; CoincidenceAsyncInput:inst1|Capture[8]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]  ; 0.277             ;
; CoincidenceAsyncInput:inst1|Capture[9]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]  ; 0.277             ;
; CoincidenceAsyncInput:inst1|Capture[10] ; CoincidenceAsyncInput:inst1|CDC_CAPT[10] ; 0.277             ;
; CoincidenceAsyncInput:inst1|Capture[3]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]  ; 0.277             ;
; CoincidenceAsyncInput:inst1|Capture[4]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]  ; 0.277             ;
; inst7[1]                                ; RabbitControl:inst|MemWrEn               ; 0.272             ;
; inst7[2]                                ; RabbitControl:inst|HighWordOnBus         ; 0.056             ;
+-----------------------------------------+------------------------------------------+-------------------+
Note: This table only shows the top 15 path(s) that have the largest delay added for hold.


+-----------------+
; Fitter Messages ;
+-----------------+
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (119006): Selected device EP3C10E144C7 for design "CoincidenceCounter"
Info (21077): Core supply voltage is 1.2V
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info (176445): Device EP3C5E144C7 is compatible
    Info (176445): Device EP3C5E144I7 is compatible
    Info (176445): Device EP3C10E144I7 is compatible
    Info (176445): Device EP3C16E144C7 is compatible
    Info (176445): Device EP3C16E144I7 is compatible
    Info (176445): Device EP3C25E144C7 is compatible
    Info (176445): Device EP3C25E144I7 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12
    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13
    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning (335093): TimeQuest Timing Analyzer is analyzing 22 combinational loops as latches.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'CoincidenceCounter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (336004): TimeQuest will use the Classic Timing Analyzer's FMAX_REQUIREMENT assignment (or --fmax command-line argument) as default timing requirement. Any other Classic Timing Analyzer assignment will be ignored.
Info (332144): No user constrained base clocks found in the design
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 3 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):    1.000    ApdDel[0]
    Info (332111):    1.000          Clk
    Info (332111):    1.000 CoincidenceAsyncInput:inst1|CDC_CAPT3
Info (176353): Automatically promoted node Clk~input (placed in PIN 22 (CLK0, DIFFCLK_0p))
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
Info (176353): Automatically promoted node CoincidenceAsyncInput:inst1|CDC_CAPT3 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Info (128000): Starting physical synthesis optimizations for speed
Info (128002): Starting physical synthesis algorithm automatic asynchronous signal pipelining
Info (128016): Automatic asynchronous signal pipelining - Evaluation Phase
    Info (128017): Asynchronous signal |CoincidenceCounter|CoinCounter:inst2|ApdsReset
        Info (128020): Signal is critical
        Info (128022): Signal fans out to non asynchronous inputs at node |CoincidenceCounter|CoinCounter:inst2|Selector1~0. No action will be taken
    Info (128018): Found 1 asynchronous signals of which 0 will be pipelined
Info (128005): Physical synthesis algorithm automatic asynchronous signal pipelining complete
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:00
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (128000): Starting physical synthesis optimizations for speed
Info (128002): Starting physical synthesis algorithm automatic asynchronous signal pipelining
Info (128027): Automatic asynchronous signal pipelining - Execution Phase
Info (128005): Physical synthesis algorithm automatic asynchronous signal pipelining complete
Info (128002): Starting physical synthesis algorithm register retiming
Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
Info (128002): Starting physical synthesis algorithm logic and register replication
Info (128003): Physical synthesis algorithm logic and register replication complete: estimated slack improvement of 20 ps
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:02
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 1% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24
Info (170194): Fitter routing operations ending: elapsed time is 00:00:03
Info (11888): Total time spent on timing analysis during the Fitter is 1.20 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
Warning (169177): 27 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin Clk uses I/O standard 3.3-V LVTTL at 22
    Info (169178): Pin Rcmd[2] uses I/O standard 3.3-V LVTTL at 99
    Info (169178): Pin Rcmd[1] uses I/O standard 3.3-V LVTTL at 100
    Info (169178): Pin Rcs uses I/O standard 3.3-V LVTTL at 98
    Info (169178): Pin Rcmd[0] uses I/O standard 3.3-V LVTTL at 103
    Info (169178): Pin ApdDel[2] uses I/O standard 3.3-V LVTTL at 46
    Info (169178): Pin ApdDel[0] uses I/O standard 3.3-V LVTTL at 39
    Info (169178): Pin ApdDel[9] uses I/O standard 3.3-V LVTTL at 72
    Info (169178): Pin ApdDel[8] uses I/O standard 3.3-V LVTTL at 69
    Info (169178): Pin ApdDel[7] uses I/O standard 3.3-V LVTTL at 67
    Info (169178): Pin ApdDel[6] uses I/O standard 3.3-V LVTTL at 65
    Info (169178): Pin ApdDel[5] uses I/O standard 3.3-V LVTTL at 60
    Info (169178): Pin ApdDel[4] uses I/O standard 3.3-V LVTTL at 58
    Info (169178): Pin ApdDel[3] uses I/O standard 3.3-V LVTTL at 50
    Info (169178): Pin ApdDel[1] uses I/O standard 3.3-V LVTTL at 43
    Info (169178): Pin ApdDel[10] uses I/O standard 3.3-V LVTTL at 77
    Info (169178): Pin Apd[10] uses I/O standard 3.3-V LVTTL at 79
    Info (169178): Pin Apd[9] uses I/O standard 3.3-V LVTTL at 76
    Info (169178): Pin Apd[8] uses I/O standard 3.3-V LVTTL at 71
    Info (169178): Pin Apd[7] uses I/O standard 3.3-V LVTTL at 68
    Info (169178): Pin Apd[6] uses I/O standard 3.3-V LVTTL at 66
    Info (169178): Pin Apd[5] uses I/O standard 3.3-V LVTTL at 64
    Info (169178): Pin Apd[4] uses I/O standard 3.3-V LVTTL at 59
    Info (169178): Pin Apd[3] uses I/O standard 3.3-V LVTTL at 51
    Info (169178): Pin Apd[2] uses I/O standard 3.3-V LVTTL at 49
    Info (169178): Pin Apd[1] uses I/O standard 3.3-V LVTTL at 44
    Info (169178): Pin Apd[0] uses I/O standard 3.3-V LVTTL at 42
Info (144001): Generated suppressed messages file C:/Projects/Archives/2008 Coincidence Counter/Altera/CoincidenceCounter.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 966 megabytes
    Info: Processing ended: Tue Nov 04 14:02:56 2014
    Info: Elapsed time: 00:00:19
    Info: Total CPU time (on all processors): 00:00:15


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Projects/Archives/2008 Coincidence Counter/Altera/CoincidenceCounter.fit.smsg.


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