TimeQuest Timing Analyzer report for CoincidenceCounter
Tue Nov 04 14:03:15 2014
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Timing Closure Recommendations
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'Clk'
 13. Slow 1200mV 85C Model Hold: 'Clk'
 14. Slow 1200mV 85C Model Recovery: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 15. Slow 1200mV 85C Model Recovery: 'ApdDel[0]'
 16. Slow 1200mV 85C Model Removal: 'ApdDel[0]'
 17. Slow 1200mV 85C Model Removal: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 18. Slow 1200mV 85C Model Minimum Pulse Width: 'Clk'
 19. Slow 1200mV 85C Model Minimum Pulse Width: 'ApdDel[0]'
 20. Slow 1200mV 85C Model Minimum Pulse Width: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 21. Setup Times
 22. Hold Times
 23. Clock to Output Times
 24. Minimum Clock to Output Times
 25. Slow 1200mV 85C Model Metastability Report
 26. Slow 1200mV 0C Model Fmax Summary
 27. Slow 1200mV 0C Model Setup Summary
 28. Slow 1200mV 0C Model Hold Summary
 29. Slow 1200mV 0C Model Recovery Summary
 30. Slow 1200mV 0C Model Removal Summary
 31. Slow 1200mV 0C Model Minimum Pulse Width Summary
 32. Slow 1200mV 0C Model Setup: 'Clk'
 33. Slow 1200mV 0C Model Hold: 'Clk'
 34. Slow 1200mV 0C Model Recovery: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 35. Slow 1200mV 0C Model Recovery: 'ApdDel[0]'
 36. Slow 1200mV 0C Model Removal: 'ApdDel[0]'
 37. Slow 1200mV 0C Model Removal: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 38. Slow 1200mV 0C Model Minimum Pulse Width: 'Clk'
 39. Slow 1200mV 0C Model Minimum Pulse Width: 'ApdDel[0]'
 40. Slow 1200mV 0C Model Minimum Pulse Width: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 41. Setup Times
 42. Hold Times
 43. Clock to Output Times
 44. Minimum Clock to Output Times
 45. Slow 1200mV 0C Model Metastability Report
 46. Fast 1200mV 0C Model Setup Summary
 47. Fast 1200mV 0C Model Hold Summary
 48. Fast 1200mV 0C Model Recovery Summary
 49. Fast 1200mV 0C Model Removal Summary
 50. Fast 1200mV 0C Model Minimum Pulse Width Summary
 51. Fast 1200mV 0C Model Setup: 'Clk'
 52. Fast 1200mV 0C Model Hold: 'Clk'
 53. Fast 1200mV 0C Model Recovery: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 54. Fast 1200mV 0C Model Recovery: 'ApdDel[0]'
 55. Fast 1200mV 0C Model Removal: 'ApdDel[0]'
 56. Fast 1200mV 0C Model Removal: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 57. Fast 1200mV 0C Model Minimum Pulse Width: 'Clk'
 58. Fast 1200mV 0C Model Minimum Pulse Width: 'ApdDel[0]'
 59. Fast 1200mV 0C Model Minimum Pulse Width: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'
 60. Setup Times
 61. Hold Times
 62. Clock to Output Times
 63. Minimum Clock to Output Times
 64. Fast 1200mV 0C Model Metastability Report
 65. Multicorner Timing Analysis Summary
 66. Setup Times
 67. Hold Times
 68. Clock to Output Times
 69. Minimum Clock to Output Times
 70. Board Trace Model Assignments
 71. Input Transition Times
 72. Slow Corner Signal Integrity Metrics
 73. Fast Corner Signal Integrity Metrics
 74. Setup Transfers
 75. Hold Transfers
 76. Recovery Transfers
 77. Removal Transfers
 78. Report TCCS
 79. Report RSKM
 80. Unconstrained Paths
 81. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                        ;
+--------------------+-----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name      ; CoincidenceCounter                                  ;
; Device Family      ; Cyclone III                                         ;
; Device Name        ; EP3C10E144C7                                        ;
; Timing Models      ; Final                                               ;
; Delay Model        ; Combined                                            ;
; Rise/Fall Delays   ; Enabled                                             ;
+--------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.25        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  25.0%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                       ;
+---------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------------------------+
; Clock Name                            ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                   ;
+---------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------------------------+
; ApdDel[0]                             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ApdDel[0] }                             ;
; Clk                                   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { Clk }                                   ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CoincidenceAsyncInput:inst1|CDC_CAPT3 } ;
+---------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------------------------+


+--------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary               ;
+------------+-----------------+------------+------+
; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------+------+
; 113.37 MHz ; 113.37 MHz      ; Clk        ;      ;
+------------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+-------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+-------+--------+--------------------+
; Clock ; Slack  ; End Point TNS      ;
+-------+--------+--------------------+
; Clk   ; -7.821 ; -326.565           ;
+-------+--------+--------------------+


+------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+-------+-------+--------------------+
; Clock ; Slack ; End Point TNS      ;
+-------+-------+--------------------+
; Clk   ; 0.152 ; 0.000              ;
+-------+-------+--------------------+


+----------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                         ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -2.117 ; -19.960       ;
; ApdDel[0]                             ; 0.099  ; 0.000         ;
+---------------------------------------+--------+---------------+


+---------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                         ;
+---------------------------------------+-------+---------------+
; Clock                                 ; Slack ; End Point TNS ;
+---------------------------------------+-------+---------------+
; ApdDel[0]                             ; 0.311 ; 0.000         ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 1.430 ; 0.000         ;
+---------------------------------------+-------+---------------+


+----------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary              ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; Clk                                   ; -3.000 ; -267.189      ;
; ApdDel[0]                             ; -3.000 ; -4.285        ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.404  ; 0.000         ;
+---------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'Clk'                                                                                                                                                                                                                                                                                            ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                           ; To Node                                                                                                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -7.821 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 8.792      ;
; -7.779 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.039     ; 8.778      ;
; -7.750 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 8.721      ;
; -7.736 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 8.707      ;
; -7.736 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 8.707      ;
; -7.722 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 8.693      ;
; -7.677 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.070     ; 8.645      ;
; -7.606 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.070     ; 8.574      ;
; -7.595 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.079     ; 8.554      ;
; -7.592 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.070     ; 8.560      ;
; -7.588 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.079     ; 8.547      ;
; -7.565 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 8.537      ;
; -7.538 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.068     ; 8.508      ;
; -7.512 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 8.483      ;
; -7.494 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 8.466      ;
; -7.491 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 8.462      ;
; -7.480 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 8.452      ;
; -7.477 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.039     ; 8.476      ;
; -7.470 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.039     ; 8.469      ;
; -7.467 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.068     ; 8.437      ;
; -7.453 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.068     ; 8.423      ;
; -7.434 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.064     ; 8.408      ;
; -7.430 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 8.401      ;
; -7.424 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.064     ; 8.398      ;
; -7.416 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.039     ; 8.415      ;
; -7.391 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 8.363      ;
; -7.390 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.068     ; 8.360      ;
; -7.380 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.068     ; 8.350      ;
; -7.320 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 8.292      ;
; -7.306 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 8.278      ;
; -7.300 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.070     ; 8.268      ;
; -7.239 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.039     ; 8.238      ;
; -7.223 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.071     ; 8.190      ;
; -7.221 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.076     ; 8.183      ;
; -7.218 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.079     ; 8.177      ;
; -7.217 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.076     ; 8.179      ;
; -7.211 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.079     ; 8.170      ;
; -7.188 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 8.160      ;
; -7.188 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.063     ; 8.163      ;
; -7.177 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.080     ; 8.135      ;
; -7.173 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.080     ; 8.131      ;
; -7.162 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.065     ; 8.135      ;
; -7.161 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.068     ; 8.131      ;
; -7.148 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.065     ; 8.121      ;
; -7.146 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.065     ; 8.119      ;
; -7.116 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.039     ; 8.115      ;
; -7.102 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.069     ; 8.071      ;
; -7.082 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.068     ; 8.052      ;
; -7.072 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.068     ; 8.042      ;
; -7.018 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.068     ; 7.988      ;
; -7.014 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.986      ;
; -6.990 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.063     ; 7.965      ;
; -6.946 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.067     ; 7.917      ;
; -6.936 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.077     ; 7.897      ;
; -6.929 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.077     ; 7.890      ;
; -6.915 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.071     ; 7.882      ;
; -6.906 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.880      ;
; -6.869 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.080     ; 7.827      ;
; -6.865 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.080     ; 7.823      ;
; -6.852 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.039     ; 7.851      ;
; -6.836 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.067     ; 7.807      ;
; -6.794 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.069     ; 7.763      ;
; -6.760 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.062     ; 7.736      ;
; -6.732 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.706      ;
; -6.729 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.062     ; 7.705      ;
; -6.696 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.062     ; 7.672      ;
; -6.651 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 7.629      ;
; -6.610 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.039     ; 7.609      ;
; -6.580 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 7.558      ;
; -6.566 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 7.544      ;
; -6.496 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.059     ; 7.475      ;
; -6.452 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.063     ; 7.427      ;
; -6.392 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.366      ;
; -6.384 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 7.362      ;
; -6.383 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.062     ; 7.359      ;
; -6.334 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 7.312      ;
; -6.321 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.295      ;
; -6.318 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.057     ; 7.299      ;
; -6.313 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 7.291      ;
; -6.307 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.281      ;
; -6.274 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 7.252      ;
; -6.274 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.073     ; 7.239      ;
; -6.274 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.061     ; 7.251      ;
; -6.191 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.061     ; 7.168      ;
; -6.159 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.033     ; 7.164      ;
; -6.144 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.063     ; 7.119      ;
; -6.101 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.057     ; 7.082      ;
; -6.074 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.033     ; 7.079      ;
; -6.029 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.033     ; 7.034      ;
; -6.026 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.073     ; 6.991      ;
; -6.015 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.064     ; 6.989      ;
; -6.007 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 6.985      ;
; -5.992 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.058     ; 6.972      ;
; -5.966 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.070     ; 6.934      ;
; -5.938 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.033     ; 6.943      ;
; -5.929 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.061     ; 6.906      ;
; -5.922 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.074     ; 6.886      ;
; -5.915 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.033     ; 6.920      ;
; -5.906 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.065     ; 6.879      ;
; -5.897 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.073     ; 6.862      ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'Clk'                                                                                                                                                                                                                                          ;
+-------+------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                ; To Node                                                                                                                  ; Launch Clock                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+
; 0.152 ; ApdDel[0]                                ; CoincidenceAsyncInput:inst1|CDC_OFF9                                                                                     ; ApdDel[0]                             ; Clk         ; 0.000        ; 2.624      ; 2.992      ;
; 0.412 ; CoinCounter:inst2|MemInc                 ; CoinCounter:inst2|MemInc                                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; CoinCounter:inst2|CoinState.0001         ; CoinCounter:inst2|CoinState.0001                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; RabbitControl:inst|RunEn                 ; RabbitControl:inst|RunEn                                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; RabbitControl:inst|HighWordOnBus         ; RabbitControl:inst|HighWordOnBus                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; RabbitControl:inst|LastCs                ; RabbitControl:inst|LastCs                                                                                                ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; RabbitControl:inst|TestDataState[1]      ; RabbitControl:inst|TestDataState[1]                                                                                      ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; CoinCounter:inst2|ApdsReset              ; CoinCounter:inst2|ApdsReset                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.669      ;
; 0.413 ; RabbitControl:inst|TestDataState[0]      ; RabbitControl:inst|TestDataState[0]                                                                                      ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 0.669      ;
; 0.437 ; CoinCounter:inst2|CoinState.0010         ; CoinCounter:inst2|CoinState.0011                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.694      ;
; 0.438 ; CoinCounter:inst2|CoinState.0110         ; CoinCounter:inst2|CoinState.0111                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.695      ;
; 0.438 ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.695      ;
; 0.440 ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.697      ;
; 0.467 ; CoinCounter:inst2|CoinState.0000         ; CoinCounter:inst2|CoinState.0001                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.724      ;
; 0.476 ; CoinCounter:inst2|CoinState.0000         ; CoinCounter:inst2|MemInc                                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.733      ;
; 0.481 ; RabbitControl:inst|MemAdd[10]            ; RabbitControl:inst|MemAdd[10]                                                                                            ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.738      ;
; 0.572 ; ApdDel[0]                                ; CoincidenceAsyncInput:inst1|CDC_OFF9                                                                                     ; ApdDel[0]                             ; Clk         ; -0.500       ; 2.624      ; 2.912      ;
; 0.605 ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.862      ;
; 0.606 ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.863      ;
; 0.610 ; inst6[2]                                 ; inst7[2]                                                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 0.866      ;
; 0.611 ; CoinCounter:inst2|CoinState.0011         ; CoinCounter:inst2|CoinState.0100                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.868      ;
; 0.629 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7] ; CoinCounter:inst2|MemAdd[7]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 0.885      ;
; 0.631 ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.888      ;
; 0.634 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2] ; CoinCounter:inst2|MemAdd[2]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 0.890      ;
; 0.656 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9] ; CoinCounter:inst2|MemAdd[9]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 0.912      ;
; 0.657 ; CoinCounter:inst2|CoinState.0100         ; CoinCounter:inst2|CoinState.0101                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.914      ;
; 0.663 ; CoincidenceAsyncInput:inst1|Capture[10]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[10]                                                                                 ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.431      ; 0.810      ;
; 0.666 ; CoincidenceAsyncInput:inst1|Capture[4]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.429      ; 0.811      ;
; 0.669 ; CoinCounter:inst2|CoinState.0111         ; CoinCounter:inst2|MemInc                                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.926      ;
; 0.674 ; RabbitControl:inst|MemAdd[9]             ; RabbitControl:inst|MemAdd[9]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.931      ;
; 0.676 ; CoincidenceAsyncInput:inst1|CDC_OFF2     ; CoinCounter:inst2|CoinState.0010                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.933      ;
; 0.676 ; RabbitControl:inst|MemAdd[7]             ; RabbitControl:inst|MemAdd[7]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.933      ;
; 0.677 ; RabbitControl:inst|MemAdd[5]             ; RabbitControl:inst|MemAdd[5]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.934      ;
; 0.680 ; RabbitControl:inst|MemAdd[6]             ; RabbitControl:inst|MemAdd[6]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.937      ;
; 0.692 ; CoincidenceAsyncInput:inst1|CDC_OFF2     ; CoinCounter:inst2|CoinState.0101                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.949      ;
; 0.693 ; RabbitControl:inst|MemAdd[8]             ; RabbitControl:inst|MemAdd[8]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.950      ;
; 0.694 ; RabbitControl:inst|TestDataState[1]      ; RabbitControl:inst|TestDataState[0]~0                                                                                    ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.951      ;
; 0.695 ; RabbitControl:inst|MemAdd[3]             ; RabbitControl:inst|MemAdd[3]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.952      ;
; 0.695 ; RabbitControl:inst|MemAdd[1]             ; RabbitControl:inst|MemAdd[1]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.952      ;
; 0.695 ; CoincidenceAsyncInput:inst1|Capture[9]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.434      ; 0.845      ;
; 0.698 ; RabbitControl:inst|MemAdd[4]             ; RabbitControl:inst|MemAdd[4]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.955      ;
; 0.699 ; CoincidenceAsyncInput:inst1|Capture[2]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.436      ; 0.851      ;
; 0.701 ; RabbitControl:inst|MemAdd[2]             ; RabbitControl:inst|MemAdd[2]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.958      ;
; 0.723 ; RabbitControl:inst|MemAdd[0]             ; RabbitControl:inst|MemAdd[0]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 0.980      ;
; 0.745 ; inst7[2]                                 ; RabbitControl:inst|TestDataState[0]                                                                                      ; Clk                                   ; Clk         ; -0.500       ; 0.265      ; 0.716      ;
; 0.750 ; CoinCounter:inst2|CoinState.0100         ; CoinCounter:inst2|CoinState.0000                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.007      ;
; 0.774 ; RabbitControl:inst|MemAdd[6]             ; RabbitControl:inst|MemWr[24]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.509      ; 1.469      ;
; 0.794 ; RabbitControl:inst|TestDataState[0]      ; RabbitControl:inst|TestDataState[0]~0                                                                                    ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.050      ;
; 0.799 ; CoincidenceAsyncInput:inst1|Capture[7]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.431      ; 0.946      ;
; 0.800 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8] ; CoinCounter:inst2|MemAdd[8]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.056      ;
; 0.809 ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.065      ;
; 0.810 ; inst6[1]                                 ; inst7[1]                                                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.066      ;
; 0.811 ; RabbitControl:inst|MemAdd[0]             ; RabbitControl:inst|MemWr[31]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.509      ; 1.506      ;
; 0.812 ; CoincidenceAsyncInput:inst1|Capture[6]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.433      ; 0.961      ;
; 0.814 ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.070      ;
; 0.814 ; CoincidenceAsyncInput:inst1|Capture[1]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.429      ; 0.959      ;
; 0.821 ; CoincidenceAsyncInput:inst1|Capture[5]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.437      ; 0.974      ;
; 0.822 ; CoincidenceAsyncInput:inst1|Capture[0]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.437      ; 0.975      ;
; 0.829 ; RabbitControl:inst|MemAdd[0]             ; RabbitControl:inst|MemWr[30]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.509      ; 1.524      ;
; 0.832 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4] ; CoinCounter:inst2|MemAdd[4]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.069      ; 1.087      ;
; 0.834 ; CoinCounter:inst2|CoinState.0001         ; CoinCounter:inst2|CoinState.0010                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.091      ;
; 0.835 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1] ; CoinCounter:inst2|MemAdd[1]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.091      ;
; 0.839 ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.095      ;
; 0.839 ; CoincidenceAsyncInput:inst1|Capture[3]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.429      ; 0.984      ;
; 0.860 ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.116      ;
; 0.864 ; CoinCounter:inst2|CoinState.0111         ; CoinCounter:inst2|CoinState.0000                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.121      ;
; 0.866 ; CoincidenceAsyncInput:inst1|Capture[8]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]                                                                                  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.436      ; 1.018      ;
; 0.897 ; RabbitControl:inst|TestDataState[0]      ; RabbitControl:inst|TestDataState[1]                                                                                      ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.153      ;
; 0.914 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3] ; CoinCounter:inst2|MemAdd[3]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.069      ; 1.169      ;
; 0.915 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6] ; CoinCounter:inst2|MemAdd[6]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.069      ; 1.170      ;
; 0.935 ; CoinCounter:inst2|CoinState.0000         ; CoinCounter:inst2|CoinState.0000                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.192      ;
; 0.989 ; CoincidenceAsyncInput:inst1|CDC_CAPT[10] ; CoincidenceAsyncInput:inst1|CDC_CAPT1[10]                                                                                ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.245      ;
; 0.992 ; RabbitControl:inst|MemAdd[9]             ; RabbitControl:inst|MemAdd[10]                                                                                            ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.249      ;
; 0.993 ; inst7[2]                                 ; RabbitControl:inst|MemWrEn                                                                                               ; Clk                                   ; Clk         ; -0.500       ; 0.265      ; 0.964      ;
; 0.993 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0] ; CoinCounter:inst2|MemAdd[0]                                                                                              ; Clk                                   ; Clk         ; 0.000        ; 0.069      ; 1.248      ;
; 0.993 ; RabbitControl:inst|MemAdd[7]             ; RabbitControl:inst|MemAdd[8]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.250      ;
; 0.994 ; inst7[2]                                 ; RabbitControl:inst|TestDataState[1]                                                                                      ; Clk                                   ; Clk         ; -0.500       ; 0.265      ; 0.965      ;
; 0.994 ; RabbitControl:inst|MemAdd[5]             ; RabbitControl:inst|MemAdd[6]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.251      ;
; 1.000 ; inst7[1]                                 ; RabbitControl:inst|MemWrEn                                                                                               ; Clk                                   ; Clk         ; -0.500       ; 0.266      ; 0.972      ;
; 1.004 ; RabbitControl:inst|LastCs                ; RabbitControl:inst|HighWordOnBus                                                                                         ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.261      ;
; 1.007 ; RabbitControl:inst|MemAdd[6]             ; RabbitControl:inst|MemAdd[7]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.264      ;
; 1.012 ; RabbitControl:inst|MemAdd[6]             ; RabbitControl:inst|MemAdd[8]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.269      ;
; 1.013 ; RabbitControl:inst|MemAdd[3]             ; RabbitControl:inst|MemAdd[4]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.270      ;
; 1.013 ; RabbitControl:inst|MemAdd[1]             ; RabbitControl:inst|MemAdd[2]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.270      ;
; 1.020 ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]                                                                                 ; Clk                                   ; Clk         ; 0.000        ; 0.070      ; 1.276      ;
; 1.020 ; RabbitControl:inst|MemAdd[8]             ; RabbitControl:inst|MemAdd[9]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.277      ;
; 1.025 ; RabbitControl:inst|MemAdd[4]             ; RabbitControl:inst|MemAdd[5]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.282      ;
; 1.025 ; RabbitControl:inst|MemAdd[8]             ; RabbitControl:inst|MemAdd[10]                                                                                            ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.282      ;
; 1.027 ; RabbitControl:inst|MemAdd[0]             ; RabbitControl:inst|MemAdd[1]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.284      ;
; 1.028 ; RabbitControl:inst|MemWr[5]              ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_datain_reg0  ; Clk                                   ; Clk         ; -0.500       ; 0.242      ; 1.012      ;
; 1.028 ; RabbitControl:inst|MemAdd[2]             ; RabbitControl:inst|MemAdd[3]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.285      ;
; 1.030 ; RabbitControl:inst|MemAdd[4]             ; RabbitControl:inst|MemAdd[6]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.287      ;
; 1.032 ; RabbitControl:inst|MemAdd[0]             ; RabbitControl:inst|MemAdd[2]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.289      ;
; 1.033 ; RabbitControl:inst|MemAdd[2]             ; RabbitControl:inst|MemAdd[4]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.071      ; 1.290      ;
; 1.037 ; CoinCounter:inst2|MemAdd[9]              ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_address_reg0 ; Clk                                   ; Clk         ; -0.500       ; 0.231      ; 1.010      ;
; 1.037 ; RabbitControl:inst|MemAdd[3]             ; RabbitControl:inst|MemWr[13]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.509      ; 1.732      ;
; 1.040 ; RabbitControl:inst|MemAdd[9]             ; RabbitControl:inst|MemWr[24]                                                                                             ; Clk                                   ; Clk         ; 0.000        ; 0.509      ; 1.735      ;
; 1.041 ; CoinCounter:inst2|MemAdd[1]              ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_address_reg0 ; Clk                                   ; Clk         ; -0.500       ; 0.231      ; 1.014      ;
; 1.043 ; CoinCounter:inst2|MemAdd[2]              ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_address_reg0 ; Clk                                   ; Clk         ; -0.500       ; 0.231      ; 1.016      ;
; 1.057 ; CoinCounter:inst2|MemAdd[0]              ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_address_reg0 ; Clk                                   ; Clk         ; -0.500       ; 0.231      ; 1.030      ;
+-------+------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                                                        ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                 ; Launch Clock ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; -2.117 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[5]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.437     ; 0.839      ;
; -1.790 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[9]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.434     ; 0.837      ;
; -1.789 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[10] ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.431     ; 0.839      ;
; -1.789 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[0]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.437     ; 0.839      ;
; -1.788 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[2]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.436     ; 0.835      ;
; -1.788 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[8]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.436     ; 0.835      ;
; -1.785 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[6]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.433     ; 0.839      ;
; -1.783 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[7]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.431     ; 0.840      ;
; -1.778 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[3]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.429     ; 0.838      ;
; -1.777 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[1]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.429     ; 0.838      ;
; -1.776 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[4]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.429     ; 0.837      ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'ApdDel[0]'                                                                                                       ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.099 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk          ; ApdDel[0]   ; 0.500        ; 1.496      ; 1.885      ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'ApdDel[0]'                                                                                                        ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.311 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk          ; ApdDel[0]   ; -0.500       ; 1.748      ; 1.775      ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                                                        ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                                 ; Launch Clock ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; 1.430 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[10] ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.257     ; 0.703      ;
; 1.430 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[7]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.257     ; 0.703      ;
; 1.430 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[3]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.255     ; 0.705      ;
; 1.430 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[4]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.255     ; 0.705      ;
; 1.431 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[1]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.255     ; 0.706      ;
; 1.432 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[2]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.262     ; 0.700      ;
; 1.433 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[8]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.263     ; 0.700      ;
; 1.434 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[9]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.260     ; 0.704      ;
; 1.435 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[6]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.259     ; 0.706      ;
; 1.436 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[5]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.263     ; 0.703      ;
; 1.438 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[0]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.263     ; 0.705      ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'Clk'                                                                                                                                                     ;
+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock ; Clock Edge ; Target                                                                                                                    ;
+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; Clk   ; Rise       ; Clk                                                                                                                       ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~portb_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~portb_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~portb_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_address_reg0 ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg       ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~portb_address_reg0 ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~portb_datain_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~portb_we_reg       ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_address_reg0 ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg       ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~portb_address_reg0 ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~portb_datain_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~portb_we_reg       ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_address_reg0 ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg       ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~portb_address_reg0 ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~portb_datain_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~portb_we_reg       ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~portb_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~portb_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~portb_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg        ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~portb_address_reg0  ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~portb_datain_reg0   ;
; -2.693 ; 1.000        ; 3.693          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~portb_we_reg        ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|ApdsReset                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0000                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0001                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0010                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0011                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0100                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0101                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0110                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0111                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[0]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[10]                                                                                              ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[1]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[2]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[3]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[4]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[5]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[6]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[7]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[8]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[9]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemInc                                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[10]                                                                                 ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[10]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF                                                                                       ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF1                                                                                      ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF2                                                                                      ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF9                                                                                      ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|HighWordOnBus                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|LastCs                                                                                                 ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[0]                                                                                              ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[10]                                                                                             ;
+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ApdDel[0]'                                                                                   ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; ApdDel[0] ; Rise       ; ApdDel[0]                                           ;
; -1.285 ; 1.000        ; 2.285          ; Min Period       ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; 0.183  ; 0.371        ; 0.188          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; 0.312  ; 0.312        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; ApdDel[0]~input|o                                   ;
; 0.335  ; 0.335        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|CDC_CAPT3|clk                                 ;
; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|datad   ;
; 0.377  ; 0.377        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|combout ;
; 0.406  ; 0.626        ; 0.220          ; High Pulse Width ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; ApdDel[0]~input|i                                   ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; ApdDel[0]~input|i                                   ;
; 0.617  ; 0.617        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|combout ;
; 0.647  ; 0.647        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|datad   ;
; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|CDC_CAPT3|clk                                 ;
; 0.688  ; 0.688        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; ApdDel[0]~input|o                                   ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                      ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                 ; Clock Edge ; Target                                  ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+
; 0.404 ; 0.404        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[8]|datac                  ;
; 0.404 ; 0.404        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[9]|datac                  ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[0]|datac                  ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[10]|datac                 ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[1]|datac                  ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[2]|datac                  ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[3]|datac                  ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[4]|datac                  ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[5]|datac                  ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[6]|datac                  ;
; 0.405 ; 0.405        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[7]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[8]  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[9]  ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[0]  ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[10] ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[1]  ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[2]  ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[3]  ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[4]  ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[5]  ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[6]  ;
; 0.411 ; 0.411        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[7]  ;
; 0.463 ; 0.463        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|inclk[0]        ;
; 0.463 ; 0.463        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|outclk          ;
; 0.500 ; 0.500        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3|q                       ;
; 0.500 ; 0.500        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3|q                       ;
; 0.535 ; 0.535        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|inclk[0]        ;
; 0.535 ; 0.535        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|outclk          ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[0]  ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[10] ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[1]  ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[2]  ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[3]  ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[4]  ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[5]  ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[6]  ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[7]  ;
; 0.585 ; 0.585        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[8]  ;
; 0.586 ; 0.586        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[9]  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[0]|datac                  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[10]|datac                 ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[1]|datac                  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[2]|datac                  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[3]|datac                  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[4]|datac                  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[5]|datac                  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[6]|datac                  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[7]|datac                  ;
; 0.591 ; 0.591        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[8]|datac                  ;
; 0.592 ; 0.592        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[9]|datac                  ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+


+-------------------------------------------------------------------------+
; Setup Times                                                             ;
+-------------+------------+-------+-------+------------+-----------------+
; Data Port   ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-------------+------------+-------+-------+------------+-----------------+
; Rcmd[*]     ; Clk        ; 2.197 ; 2.627 ; Rise       ; Clk             ;
;  Rcmd[0]    ; Clk        ; 1.992 ; 2.415 ; Rise       ; Clk             ;
;  Rcmd[1]    ; Clk        ; 2.029 ; 2.444 ; Rise       ; Clk             ;
;  Rcmd[2]    ; Clk        ; 2.197 ; 2.627 ; Rise       ; Clk             ;
; Rcs         ; Clk        ; 1.992 ; 2.384 ; Rise       ; Clk             ;
; Apd[*]      ; Clk        ; 2.669 ; 3.195 ; Fall       ; Clk             ;
;  Apd[0]     ; Clk        ; 2.664 ; 3.195 ; Fall       ; Clk             ;
;  Apd[1]     ; Clk        ; 2.604 ; 3.053 ; Fall       ; Clk             ;
;  Apd[2]     ; Clk        ; 1.922 ; 2.412 ; Fall       ; Clk             ;
;  Apd[3]     ; Clk        ; 2.669 ; 3.132 ; Fall       ; Clk             ;
;  Apd[4]     ; Clk        ; 2.662 ; 3.122 ; Fall       ; Clk             ;
;  Apd[5]     ; Clk        ; 2.451 ; 2.876 ; Fall       ; Clk             ;
;  Apd[6]     ; Clk        ; 2.058 ; 2.486 ; Fall       ; Clk             ;
;  Apd[7]     ; Clk        ; 2.656 ; 3.097 ; Fall       ; Clk             ;
;  Apd[8]     ; Clk        ; 2.379 ; 2.833 ; Fall       ; Clk             ;
;  Apd[9]     ; Clk        ; 2.334 ; 2.798 ; Fall       ; Clk             ;
;  Apd[10]    ; Clk        ; 1.886 ; 2.306 ; Fall       ; Clk             ;
; ApdDel[*]   ; Clk        ; 6.232 ; 6.562 ; Fall       ; Clk             ;
;  ApdDel[0]  ; Clk        ; 0.481 ; 0.542 ; Fall       ; Clk             ;
;  ApdDel[1]  ; Clk        ; 3.816 ; 4.165 ; Fall       ; Clk             ;
;  ApdDel[2]  ; Clk        ; 3.160 ; 3.504 ; Fall       ; Clk             ;
;  ApdDel[3]  ; Clk        ; 6.232 ; 6.562 ; Fall       ; Clk             ;
;  ApdDel[4]  ; Clk        ; 5.820 ; 6.167 ; Fall       ; Clk             ;
;  ApdDel[5]  ; Clk        ; 6.027 ; 6.364 ; Fall       ; Clk             ;
;  ApdDel[6]  ; Clk        ; 6.073 ; 6.366 ; Fall       ; Clk             ;
;  ApdDel[7]  ; Clk        ; 4.574 ; 4.987 ; Fall       ; Clk             ;
;  ApdDel[8]  ; Clk        ; 4.583 ; 4.991 ; Fall       ; Clk             ;
;  ApdDel[9]  ; Clk        ; 4.564 ; 4.910 ; Fall       ; Clk             ;
;  ApdDel[10] ; Clk        ; 4.430 ; 4.776 ; Fall       ; Clk             ;
+-------------+------------+-------+-------+------------+-----------------+


+---------------------------------------------------------------------------+
; Hold Times                                                                ;
+-------------+------------+--------+--------+------------+-----------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-------------+------------+--------+--------+------------+-----------------+
; Rcmd[*]     ; Clk        ; -1.578 ; -1.978 ; Rise       ; Clk             ;
;  Rcmd[0]    ; Clk        ; -1.578 ; -1.978 ; Rise       ; Clk             ;
;  Rcmd[1]    ; Clk        ; -1.614 ; -2.006 ; Rise       ; Clk             ;
;  Rcmd[2]    ; Clk        ; -1.789 ; -2.206 ; Rise       ; Clk             ;
; Rcs         ; Clk        ; -1.577 ; -1.948 ; Rise       ; Clk             ;
; Apd[*]      ; Clk        ; -1.425 ; -1.842 ; Fall       ; Clk             ;
;  Apd[0]     ; Clk        ; -2.133 ; -2.642 ; Fall       ; Clk             ;
;  Apd[1]     ; Clk        ; -2.108 ; -2.558 ; Fall       ; Clk             ;
;  Apd[2]     ; Clk        ; -1.454 ; -1.943 ; Fall       ; Clk             ;
;  Apd[3]     ; Clk        ; -2.170 ; -2.634 ; Fall       ; Clk             ;
;  Apd[4]     ; Clk        ; -2.163 ; -2.625 ; Fall       ; Clk             ;
;  Apd[5]     ; Clk        ; -1.962 ; -2.389 ; Fall       ; Clk             ;
;  Apd[6]     ; Clk        ; -1.584 ; -2.015 ; Fall       ; Clk             ;
;  Apd[7]     ; Clk        ; -2.158 ; -2.601 ; Fall       ; Clk             ;
;  Apd[8]     ; Clk        ; -1.892 ; -2.348 ; Fall       ; Clk             ;
;  Apd[9]     ; Clk        ; -1.856 ; -2.315 ; Fall       ; Clk             ;
;  Apd[10]    ; Clk        ; -1.425 ; -1.842 ; Fall       ; Clk             ;
; ApdDel[*]   ; Clk        ; -0.102 ; -0.182 ; Fall       ; Clk             ;
;  ApdDel[0]  ; Clk        ; -0.102 ; -0.182 ; Fall       ; Clk             ;
;  ApdDel[1]  ; Clk        ; -3.302 ; -3.657 ; Fall       ; Clk             ;
;  ApdDel[2]  ; Clk        ; -2.671 ; -3.022 ; Fall       ; Clk             ;
;  ApdDel[3]  ; Clk        ; -5.621 ; -5.958 ; Fall       ; Clk             ;
;  ApdDel[4]  ; Clk        ; -5.225 ; -5.579 ; Fall       ; Clk             ;
;  ApdDel[5]  ; Clk        ; -5.424 ; -5.768 ; Fall       ; Clk             ;
;  ApdDel[6]  ; Clk        ; -5.469 ; -5.770 ; Fall       ; Clk             ;
;  ApdDel[7]  ; Clk        ; -4.029 ; -4.446 ; Fall       ; Clk             ;
;  ApdDel[8]  ; Clk        ; -4.039 ; -4.450 ; Fall       ; Clk             ;
;  ApdDel[9]  ; Clk        ; -4.020 ; -4.372 ; Fall       ; Clk             ;
;  ApdDel[10] ; Clk        ; -3.897 ; -4.244 ; Fall       ; Clk             ;
+-------------+------------+--------+--------+------------+-----------------+


+-------------------------------------------------------------------------+
; Clock to Output Times                                                   ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; Rdat[*]   ; Clk        ; 12.959 ; 12.253 ; Rise       ; Clk             ;
;  Rdat[0]  ; Clk        ; 11.601 ; 11.315 ; Rise       ; Clk             ;
;  Rdat[1]  ; Clk        ; 11.438 ; 11.133 ; Rise       ; Clk             ;
;  Rdat[2]  ; Clk        ; 11.641 ; 11.363 ; Rise       ; Clk             ;
;  Rdat[3]  ; Clk        ; 11.090 ; 10.762 ; Rise       ; Clk             ;
;  Rdat[4]  ; Clk        ; 11.188 ; 10.847 ; Rise       ; Clk             ;
;  Rdat[5]  ; Clk        ; 11.124 ; 10.806 ; Rise       ; Clk             ;
;  Rdat[6]  ; Clk        ; 12.959 ; 12.253 ; Rise       ; Clk             ;
;  Rdat[7]  ; Clk        ; 10.258 ; 9.950  ; Rise       ; Clk             ;
;  Rdat[8]  ; Clk        ; 11.188 ; 10.857 ; Rise       ; Clk             ;
;  Rdat[9]  ; Clk        ; 10.550 ; 10.255 ; Rise       ; Clk             ;
;  Rdat[10] ; Clk        ; 10.651 ; 10.361 ; Rise       ; Clk             ;
;  Rdat[11] ; Clk        ; 10.802 ; 10.485 ; Rise       ; Clk             ;
;  Rdat[12] ; Clk        ; 10.088 ; 9.769  ; Rise       ; Clk             ;
;  Rdat[13] ; Clk        ; 10.423 ; 10.068 ; Rise       ; Clk             ;
;  Rdat[14] ; Clk        ; 12.859 ; 12.221 ; Rise       ; Clk             ;
;  Rdat[15] ; Clk        ; 10.391 ; 10.099 ; Rise       ; Clk             ;
; Rdat[*]   ; Clk        ; 10.150 ; 9.555  ; Fall       ; Clk             ;
;  Rdat[0]  ; Clk        ; 9.173  ; 8.926  ; Fall       ; Clk             ;
;  Rdat[1]  ; Clk        ; 8.677  ; 8.378  ; Fall       ; Clk             ;
;  Rdat[2]  ; Clk        ; 8.669  ; 8.377  ; Fall       ; Clk             ;
;  Rdat[3]  ; Clk        ; 7.933  ; 7.652  ; Fall       ; Clk             ;
;  Rdat[4]  ; Clk        ; 7.663  ; 7.385  ; Fall       ; Clk             ;
;  Rdat[5]  ; Clk        ; 7.960  ; 7.627  ; Fall       ; Clk             ;
;  Rdat[6]  ; Clk        ; 10.142 ; 9.474  ; Fall       ; Clk             ;
;  Rdat[7]  ; Clk        ; 7.962  ; 7.620  ; Fall       ; Clk             ;
;  Rdat[8]  ; Clk        ; 7.972  ; 7.628  ; Fall       ; Clk             ;
;  Rdat[9]  ; Clk        ; 7.325  ; 7.020  ; Fall       ; Clk             ;
;  Rdat[10] ; Clk        ; 8.046  ; 7.751  ; Fall       ; Clk             ;
;  Rdat[11] ; Clk        ; 8.228  ; 7.892  ; Fall       ; Clk             ;
;  Rdat[12] ; Clk        ; 7.901  ; 7.587  ; Fall       ; Clk             ;
;  Rdat[13] ; Clk        ; 8.291  ; 7.920  ; Fall       ; Clk             ;
;  Rdat[14] ; Clk        ; 10.150 ; 9.555  ; Fall       ; Clk             ;
;  Rdat[15] ; Clk        ; 7.456  ; 7.129  ; Fall       ; Clk             ;
+-----------+------------+--------+--------+------------+-----------------+


+------------------------------------------------------------------------+
; Minimum Clock to Output Times                                          ;
+-----------+------------+--------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+-------+------------+-----------------+
; Rdat[*]   ; Clk        ; 7.700  ; 7.457 ; Rise       ; Clk             ;
;  Rdat[0]  ; Clk        ; 9.193  ; 8.941 ; Rise       ; Clk             ;
;  Rdat[1]  ; Clk        ; 9.060  ; 8.812 ; Rise       ; Clk             ;
;  Rdat[2]  ; Clk        ; 8.536  ; 8.211 ; Rise       ; Clk             ;
;  Rdat[3]  ; Clk        ; 8.266  ; 7.908 ; Rise       ; Clk             ;
;  Rdat[4]  ; Clk        ; 8.019  ; 7.685 ; Rise       ; Clk             ;
;  Rdat[5]  ; Clk        ; 8.311  ; 7.951 ; Rise       ; Clk             ;
;  Rdat[6]  ; Clk        ; 10.475 ; 9.730 ; Rise       ; Clk             ;
;  Rdat[7]  ; Clk        ; 7.982  ; 7.627 ; Rise       ; Clk             ;
;  Rdat[8]  ; Clk        ; 7.991  ; 7.635 ; Rise       ; Clk             ;
;  Rdat[9]  ; Clk        ; 7.700  ; 7.457 ; Rise       ; Clk             ;
;  Rdat[10] ; Clk        ; 8.015  ; 7.689 ; Rise       ; Clk             ;
;  Rdat[11] ; Clk        ; 8.189  ; 7.824 ; Rise       ; Clk             ;
;  Rdat[12] ; Clk        ; 8.052  ; 7.699 ; Rise       ; Clk             ;
;  Rdat[13] ; Clk        ; 8.411  ; 8.024 ; Rise       ; Clk             ;
;  Rdat[14] ; Clk        ; 10.249 ; 9.540 ; Rise       ; Clk             ;
;  Rdat[15] ; Clk        ; 7.938  ; 7.562 ; Rise       ; Clk             ;
; Rdat[*]   ; Clk        ; 7.132  ; 6.837 ; Fall       ; Clk             ;
;  Rdat[0]  ; Clk        ; 8.926  ; 8.591 ; Fall       ; Clk             ;
;  Rdat[1]  ; Clk        ; 8.434  ; 8.144 ; Fall       ; Clk             ;
;  Rdat[2]  ; Clk        ; 8.365  ; 8.140 ; Fall       ; Clk             ;
;  Rdat[3]  ; Clk        ; 7.710  ; 7.393 ; Fall       ; Clk             ;
;  Rdat[4]  ; Clk        ; 7.477  ; 7.163 ; Fall       ; Clk             ;
;  Rdat[5]  ; Clk        ; 7.747  ; 7.425 ; Fall       ; Clk             ;
;  Rdat[6]  ; Clk        ; 9.920  ; 9.216 ; Fall       ; Clk             ;
;  Rdat[7]  ; Clk        ; 7.651  ; 7.388 ; Fall       ; Clk             ;
;  Rdat[8]  ; Clk        ; 7.660  ; 7.396 ; Fall       ; Clk             ;
;  Rdat[9]  ; Clk        ; 7.132  ; 6.837 ; Fall       ; Clk             ;
;  Rdat[10] ; Clk        ; 7.756  ; 7.489 ; Fall       ; Clk             ;
;  Rdat[11] ; Clk        ; 7.932  ; 7.623 ; Fall       ; Clk             ;
;  Rdat[12] ; Clk        ; 7.696  ; 7.369 ; Fall       ; Clk             ;
;  Rdat[13] ; Clk        ; 8.033  ; 7.695 ; Fall       ; Clk             ;
;  Rdat[14] ; Clk        ; 9.948  ; 9.268 ; Fall       ; Clk             ;
;  Rdat[15] ; Clk        ; 7.248  ; 6.931 ; Fall       ; Clk             ;
+-----------+------------+--------+-------+------------+-----------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                ;
+------------+-----------------+------------+------+
; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------+------+
; 124.88 MHz ; 124.88 MHz      ; Clk        ;      ;
+------------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+-------+--------+-------------------+
; Clock ; Slack  ; End Point TNS     ;
+-------+--------+-------------------+
; Clk   ; -7.008 ; -290.522          ;
+-------+--------+-------------------+


+-----------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+-------+-------+-------------------+
; Clock ; Slack ; End Point TNS     ;
+-------+-------+-------------------+
; Clk   ; 0.128 ; 0.000             ;
+-------+-------+-------------------+


+----------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                          ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -1.985 ; -18.493       ;
; ApdDel[0]                             ; 0.242  ; 0.000         ;
+---------------------------------------+--------+---------------+


+---------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                          ;
+---------------------------------------+-------+---------------+
; Clock                                 ; Slack ; End Point TNS ;
+---------------------------------------+-------+---------------+
; ApdDel[0]                             ; 0.239 ; 0.000         ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 1.421 ; 0.000         ;
+---------------------------------------+-------+---------------+


+----------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary               ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; Clk                                   ; -3.000 ; -265.077      ;
; ApdDel[0]                             ; -3.000 ; -4.285        ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.440  ; 0.000         ;
+---------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'Clk'                                                                                                                                                                                                                                                                                             ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                           ; To Node                                                                                                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -7.008 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.972      ;
; -6.976 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.041     ; 7.965      ;
; -6.953 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.917      ;
; -6.951 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.915      ;
; -6.945 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.065     ; 7.910      ;
; -6.943 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.065     ; 7.908      ;
; -6.879 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.070     ; 7.839      ;
; -6.824 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.070     ; 7.784      ;
; -6.822 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.070     ; 7.782      ;
; -6.802 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.076     ; 7.756      ;
; -6.792 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.076     ; 7.746      ;
; -6.780 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.065     ; 7.745      ;
; -6.756 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.068     ; 7.718      ;
; -6.735 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.699      ;
; -6.727 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.691      ;
; -6.725 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.065     ; 7.690      ;
; -6.723 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.065     ; 7.688      ;
; -6.712 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.041     ; 7.701      ;
; -6.701 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.068     ; 7.663      ;
; -6.700 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.041     ; 7.689      ;
; -6.699 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.068     ; 7.661      ;
; -6.635 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.601      ;
; -6.619 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.041     ; 7.608      ;
; -6.610 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.065     ; 7.575      ;
; -6.597 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.062     ; 7.565      ;
; -6.579 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.061     ; 7.548      ;
; -6.575 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 7.538      ;
; -6.567 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.531      ;
; -6.555 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.065     ; 7.520      ;
; -6.553 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.065     ; 7.518      ;
; -6.514 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.069     ; 7.475      ;
; -6.446 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.071     ; 7.405      ;
; -6.437 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.075     ; 7.392      ;
; -6.427 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.075     ; 7.382      ;
; -6.426 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.063     ; 7.393      ;
; -6.418 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.062     ; 7.386      ;
; -6.417 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.041     ; 7.406      ;
; -6.415 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.381      ;
; -6.394 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.072     ; 7.352      ;
; -6.391 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.067     ; 7.354      ;
; -6.391 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.072     ; 7.349      ;
; -6.369 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.077     ; 7.322      ;
; -6.359 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.077     ; 7.312      ;
; -6.344 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.061     ; 7.313      ;
; -6.328 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.294      ;
; -6.323 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.069     ; 7.284      ;
; -6.323 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 7.286      ;
; -6.322 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.041     ; 7.311      ;
; -6.315 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.279      ;
; -6.297 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.067     ; 7.260      ;
; -6.245 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.064     ; 7.211      ;
; -6.220 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.073     ; 7.177      ;
; -6.210 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.073     ; 7.167      ;
; -6.198 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.062     ; 7.166      ;
; -6.194 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.071     ; 7.153      ;
; -6.181 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.061     ; 7.150      ;
; -6.177 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.141      ;
; -6.150 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.041     ; 7.139      ;
; -6.117 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.077     ; 7.070      ;
; -6.107 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.077     ; 7.060      ;
; -6.095 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.066     ; 7.059      ;
; -6.071 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.069     ; 7.032      ;
; -6.062 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.063     ; 7.029      ;
; -6.028 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.062     ; 6.996      ;
; -6.007 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.063     ; 6.974      ;
; -6.005 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.063     ; 6.972      ;
; -5.951 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 6.921      ;
; -5.900 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.041     ; 6.889      ;
; -5.896 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 6.866      ;
; -5.894 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 6.864      ;
; -5.779 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.059     ; 6.750      ;
; -5.745 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.064     ; 6.711      ;
; -5.737 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.065     ; 6.702      ;
; -5.719 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 6.689      ;
; -5.697 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.062     ; 6.665      ;
; -5.682 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.065     ; 6.647      ;
; -5.680 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.065     ; 6.645      ;
; -5.664 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 6.634      ;
; -5.662 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.060     ; 6.632      ;
; -5.623 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.071     ; 6.582      ;
; -5.602 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.056     ; 6.576      ;
; -5.586 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.059     ; 6.557      ;
; -5.568 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.061     ; 6.537      ;
; -5.556 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.061     ; 6.525      ;
; -5.533 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.036     ; 6.527      ;
; -5.467 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.064     ; 6.433      ;
; -5.456 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.036     ; 6.450      ;
; -5.415 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.056     ; 6.389      ;
; -5.405 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.071     ; 6.364      ;
; -5.372 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.064     ; 6.338      ;
; -5.369 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.057     ; 6.342      ;
; -5.356 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.036     ; 6.350      ;
; -5.354 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.059     ; 6.325      ;
; -5.340 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.061     ; 6.309      ;
; -5.313 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.036     ; 6.307      ;
; -5.304 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.066     ; 6.268      ;
; -5.294 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.067     ; 6.257      ;
; -5.265 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.036     ; 6.259      ;
; -5.260 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.072     ; 6.218      ;
; -5.258 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.070     ; 6.218      ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'Clk'                                                                                                                                                             ;
+-------+-------------------------------------------+-------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                 ; To Node                                   ; Launch Clock                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------+-------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+
; 0.128 ; ApdDel[0]                                 ; CoincidenceAsyncInput:inst1|CDC_OFF9      ; ApdDel[0]                             ; Clk         ; 0.000        ; 2.438      ; 2.767      ;
; 0.362 ; CoinCounter:inst2|MemInc                  ; CoinCounter:inst2|MemInc                  ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; CoinCounter:inst2|CoinState.0001          ; CoinCounter:inst2|CoinState.0001          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; RabbitControl:inst|RunEn                  ; RabbitControl:inst|RunEn                  ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; RabbitControl:inst|HighWordOnBus          ; RabbitControl:inst|HighWordOnBus          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; RabbitControl:inst|LastCs                 ; RabbitControl:inst|LastCs                 ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; RabbitControl:inst|TestDataState[1]       ; RabbitControl:inst|TestDataState[1]       ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; CoinCounter:inst2|ApdsReset               ; CoinCounter:inst2|ApdsReset               ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.597      ;
; 0.363 ; RabbitControl:inst|TestDataState[0]       ; RabbitControl:inst|TestDataState[0]       ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.597      ;
; 0.403 ; CoinCounter:inst2|CoinState.0010          ; CoinCounter:inst2|CoinState.0011          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.638      ;
; 0.404 ; CoinCounter:inst2|CoinState.0110          ; CoinCounter:inst2|CoinState.0111          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.639      ;
; 0.405 ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.639      ;
; 0.407 ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.641      ;
; 0.422 ; CoinCounter:inst2|CoinState.0000          ; CoinCounter:inst2|CoinState.0001          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.657      ;
; 0.435 ; RabbitControl:inst|MemAdd[10]             ; RabbitControl:inst|MemAdd[10]             ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.669      ;
; 0.436 ; CoinCounter:inst2|CoinState.0000          ; CoinCounter:inst2|MemInc                  ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.671      ;
; 0.558 ; CoinCounter:inst2|CoinState.0011          ; CoinCounter:inst2|CoinState.0100          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.793      ;
; 0.560 ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.794      ;
; 0.560 ; CoincidenceAsyncInput:inst1|Capture[10]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[10]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.462      ; 0.723      ;
; 0.561 ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.795      ;
; 0.564 ; inst6[2]                                  ; inst7[2]                                  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.798      ;
; 0.572 ; CoincidenceAsyncInput:inst1|Capture[4]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.461      ; 0.734      ;
; 0.580 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]  ; CoinCounter:inst2|MemAdd[7]               ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.814      ;
; 0.582 ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.816      ;
; 0.582 ; CoincidenceAsyncInput:inst1|Capture[9]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.465      ; 0.748      ;
; 0.583 ; CoincidenceAsyncInput:inst1|Capture[2]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.467      ; 0.751      ;
; 0.585 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]  ; CoinCounter:inst2|MemAdd[2]               ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.819      ;
; 0.601 ; CoinCounter:inst2|CoinState.0100          ; CoinCounter:inst2|CoinState.0101          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.836      ;
; 0.601 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]  ; CoinCounter:inst2|MemAdd[9]               ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.835      ;
; 0.608 ; CoinCounter:inst2|CoinState.0111          ; CoinCounter:inst2|MemInc                  ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.843      ;
; 0.618 ; CoincidenceAsyncInput:inst1|CDC_OFF2      ; CoinCounter:inst2|CoinState.0010          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.853      ;
; 0.618 ; RabbitControl:inst|MemAdd[9]              ; RabbitControl:inst|MemAdd[9]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.852      ;
; 0.618 ; RabbitControl:inst|MemAdd[5]              ; RabbitControl:inst|MemAdd[5]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.852      ;
; 0.620 ; RabbitControl:inst|MemAdd[7]              ; RabbitControl:inst|MemAdd[7]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.854      ;
; 0.622 ; RabbitControl:inst|MemAdd[6]              ; RabbitControl:inst|MemAdd[6]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.856      ;
; 0.633 ; RabbitControl:inst|MemAdd[3]              ; RabbitControl:inst|MemAdd[3]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.867      ;
; 0.633 ; RabbitControl:inst|MemAdd[1]              ; RabbitControl:inst|MemAdd[1]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.867      ;
; 0.634 ; RabbitControl:inst|MemAdd[8]              ; RabbitControl:inst|MemAdd[8]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.868      ;
; 0.635 ; RabbitControl:inst|MemAdd[4]              ; RabbitControl:inst|MemAdd[4]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.869      ;
; 0.636 ; CoincidenceAsyncInput:inst1|CDC_OFF2      ; CoinCounter:inst2|CoinState.0101          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.871      ;
; 0.637 ; RabbitControl:inst|TestDataState[1]       ; RabbitControl:inst|TestDataState[0]~0     ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.872      ;
; 0.639 ; RabbitControl:inst|MemAdd[2]              ; RabbitControl:inst|MemAdd[2]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.873      ;
; 0.640 ; ApdDel[0]                                 ; CoincidenceAsyncInput:inst1|CDC_OFF9      ; ApdDel[0]                             ; Clk         ; -0.500       ; 2.438      ; 2.779      ;
; 0.660 ; RabbitControl:inst|MemAdd[0]              ; RabbitControl:inst|MemAdd[0]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.894      ;
; 0.677 ; CoincidenceAsyncInput:inst1|Capture[7]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.462      ; 0.840      ;
; 0.686 ; CoinCounter:inst2|CoinState.0100          ; CoinCounter:inst2|CoinState.0000          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 0.921      ;
; 0.689 ; CoincidenceAsyncInput:inst1|Capture[5]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.469      ; 0.859      ;
; 0.695 ; CoincidenceAsyncInput:inst1|Capture[1]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.462      ; 0.858      ;
; 0.697 ; CoincidenceAsyncInput:inst1|Capture[6]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.465      ; 0.863      ;
; 0.700 ; inst7[2]                                  ; RabbitControl:inst|TestDataState[0]       ; Clk                                   ; Clk         ; -0.500       ; 0.258      ; 0.649      ;
; 0.705 ; CoincidenceAsyncInput:inst1|Capture[0]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.469      ; 0.875      ;
; 0.721 ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.955      ;
; 0.723 ; CoincidenceAsyncInput:inst1|Capture[8]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.467      ; 0.891      ;
; 0.723 ; CoincidenceAsyncInput:inst1|Capture[3]    ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]   ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.461      ; 0.885      ;
; 0.724 ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.958      ;
; 0.736 ; RabbitControl:inst|TestDataState[0]       ; RabbitControl:inst|TestDataState[0]~0     ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.970      ;
; 0.739 ; RabbitControl:inst|MemAdd[6]              ; RabbitControl:inst|MemWr[24]              ; Clk                                   ; Clk         ; 0.000        ; 0.449      ; 1.359      ;
; 0.743 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]  ; CoinCounter:inst2|MemAdd[8]               ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.977      ;
; 0.743 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]  ; CoinCounter:inst2|MemAdd[4]               ; Clk                                   ; Clk         ; 0.000        ; 0.062      ; 0.976      ;
; 0.746 ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.980      ;
; 0.755 ; inst6[1]                                  ; inst7[1]                                  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.989      ;
; 0.761 ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 0.995      ;
; 0.766 ; RabbitControl:inst|MemAdd[0]              ; RabbitControl:inst|MemWr[31]              ; Clk                                   ; Clk         ; 0.000        ; 0.450      ; 1.387      ;
; 0.772 ; CoinCounter:inst2|CoinState.0001          ; CoinCounter:inst2|CoinState.0010          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 1.007      ;
; 0.777 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]  ; CoinCounter:inst2|MemAdd[1]               ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.011      ;
; 0.786 ; RabbitControl:inst|MemAdd[0]              ; RabbitControl:inst|MemWr[30]              ; Clk                                   ; Clk         ; 0.000        ; 0.450      ; 1.407      ;
; 0.799 ; CoinCounter:inst2|CoinState.0111          ; CoinCounter:inst2|CoinState.0000          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 1.034      ;
; 0.812 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]  ; CoinCounter:inst2|MemAdd[6]               ; Clk                                   ; Clk         ; 0.000        ; 0.062      ; 1.045      ;
; 0.815 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]  ; CoinCounter:inst2|MemAdd[3]               ; Clk                                   ; Clk         ; 0.000        ; 0.062      ; 1.048      ;
; 0.833 ; RabbitControl:inst|TestDataState[0]       ; RabbitControl:inst|TestDataState[1]       ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.067      ;
; 0.853 ; CoinCounter:inst2|CoinState.0000          ; CoinCounter:inst2|CoinState.0000          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 1.088      ;
; 0.904 ; RabbitControl:inst|MemAdd[9]              ; RabbitControl:inst|MemAdd[10]             ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.138      ;
; 0.905 ; RabbitControl:inst|MemAdd[5]              ; RabbitControl:inst|MemAdd[6]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.139      ;
; 0.907 ; RabbitControl:inst|MemAdd[7]              ; RabbitControl:inst|MemAdd[8]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.141      ;
; 0.910 ; CoincidenceAsyncInput:inst1|CDC_CAPT[10]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[10] ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.144      ;
; 0.910 ; RabbitControl:inst|MemAdd[6]              ; RabbitControl:inst|MemAdd[7]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.144      ;
; 0.917 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]  ; CoinCounter:inst2|MemAdd[0]               ; Clk                                   ; Clk         ; 0.000        ; 0.062      ; 1.150      ;
; 0.919 ; RabbitControl:inst|LastCs                 ; RabbitControl:inst|HighWordOnBus          ; Clk                                   ; Clk         ; 0.000        ; 0.064      ; 1.154      ;
; 0.919 ; RabbitControl:inst|MemAdd[3]              ; RabbitControl:inst|MemAdd[4]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.153      ;
; 0.919 ; RabbitControl:inst|MemAdd[1]              ; RabbitControl:inst|MemAdd[2]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.153      ;
; 0.921 ; RabbitControl:inst|MemAdd[6]              ; RabbitControl:inst|MemAdd[8]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.155      ;
; 0.922 ; RabbitControl:inst|MemAdd[8]              ; RabbitControl:inst|MemAdd[9]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.156      ;
; 0.923 ; RabbitControl:inst|MemAdd[4]              ; RabbitControl:inst|MemAdd[5]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.157      ;
; 0.927 ; RabbitControl:inst|MemAdd[2]              ; RabbitControl:inst|MemAdd[3]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.161      ;
; 0.927 ; RabbitControl:inst|MemAdd[0]              ; RabbitControl:inst|MemAdd[1]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.161      ;
; 0.928 ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]   ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]  ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.162      ;
; 0.933 ; RabbitControl:inst|MemAdd[8]              ; RabbitControl:inst|MemAdd[10]             ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.167      ;
; 0.934 ; RabbitControl:inst|MemAdd[4]              ; RabbitControl:inst|MemAdd[6]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.168      ;
; 0.935 ; inst7[2]                                  ; RabbitControl:inst|MemWrEn                ; Clk                                   ; Clk         ; -0.500       ; 0.258      ; 0.884      ;
; 0.936 ; inst7[2]                                  ; RabbitControl:inst|TestDataState[1]       ; Clk                                   ; Clk         ; -0.500       ; 0.258      ; 0.885      ;
; 0.938 ; RabbitControl:inst|MemAdd[2]              ; RabbitControl:inst|MemAdd[4]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.172      ;
; 0.938 ; RabbitControl:inst|MemAdd[0]              ; RabbitControl:inst|MemAdd[2]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.172      ;
; 0.940 ; inst7[1]                                  ; RabbitControl:inst|MemWrEn                ; Clk                                   ; Clk         ; -0.500       ; 0.259      ; 0.890      ;
; 0.968 ; RabbitControl:inst|MemAdd[9]              ; RabbitControl:inst|MemWr[24]              ; Clk                                   ; Clk         ; 0.000        ; 0.449      ; 1.588      ;
; 0.979 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[10] ; CoinCounter:inst2|MemAdd[10]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.213      ;
; 0.980 ; RabbitControl:inst|MemAdd[3]              ; RabbitControl:inst|MemWr[13]              ; Clk                                   ; Clk         ; 0.000        ; 0.449      ; 1.600      ;
; 0.985 ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]  ; CoinCounter:inst2|MemAdd[5]               ; Clk                                   ; Clk         ; 0.000        ; 0.062      ; 1.218      ;
; 0.999 ; RabbitControl:inst|RunEn                  ; CoinCounter:inst2|CoinState.0010          ; Clk                                   ; Clk         ; 0.000        ; 0.068      ; 1.238      ;
; 1.004 ; RabbitControl:inst|MemAdd[5]              ; RabbitControl:inst|MemAdd[7]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.238      ;
; 1.006 ; RabbitControl:inst|MemAdd[7]              ; RabbitControl:inst|MemAdd[9]              ; Clk                                   ; Clk         ; 0.000        ; 0.063      ; 1.240      ;
+-------+-------------------------------------------+-------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                                                         ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                 ; Launch Clock ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; -1.985 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[5]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.469     ; 0.758      ;
; -1.657 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[0]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.469     ; 0.758      ;
; -1.656 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[9]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.466     ; 0.756      ;
; -1.655 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[10] ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.463     ; 0.757      ;
; -1.655 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[6]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.465     ; 0.760      ;
; -1.652 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[2]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.468     ; 0.752      ;
; -1.652 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[8]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.468     ; 0.752      ;
; -1.647 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[7]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.463     ; 0.755      ;
; -1.646 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[3]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.462     ; 0.756      ;
; -1.644 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[1]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.462     ; 0.755      ;
; -1.644 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[4]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.462     ; 0.755      ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'ApdDel[0]'                                                                                                        ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.242 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk          ; ApdDel[0]   ; 0.500        ; 1.461      ; 1.708      ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'ApdDel[0]'                                                                                                         ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.239 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk          ; ApdDel[0]   ; -0.500       ; 1.689      ; 1.629      ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                                                         ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                                 ; Launch Clock ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; 1.421 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[10] ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.306     ; 0.645      ;
; 1.421 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[7]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.306     ; 0.645      ;
; 1.421 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[6]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.308     ; 0.643      ;
; 1.421 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[3]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.304     ; 0.647      ;
; 1.422 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[8]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.311     ; 0.641      ;
; 1.422 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[9]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.308     ; 0.644      ;
; 1.422 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[4]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.304     ; 0.648      ;
; 1.423 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[2]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.311     ; 0.642      ;
; 1.423 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[1]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.304     ; 0.649      ;
; 1.426 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[0]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.312     ; 0.644      ;
; 1.427 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[5]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.312     ; 0.645      ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'Clk'                                                                                                                                                      ;
+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock ; Clock Edge ; Target                                                                                                                    ;
+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; Clk   ; Rise       ; Clk                                                                                                                       ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~portb_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~portb_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~portb_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_address_reg0 ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg       ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~portb_address_reg0 ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~portb_datain_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~portb_we_reg       ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_address_reg0 ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg       ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~portb_address_reg0 ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~portb_datain_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~portb_we_reg       ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_address_reg0 ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg       ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~portb_address_reg0 ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~portb_datain_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~portb_we_reg       ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~portb_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~portb_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~portb_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg        ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~portb_address_reg0  ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~portb_datain_reg0   ;
; -2.649 ; 1.000        ; 3.649          ; Min Period ; Clk   ; Rise       ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~portb_we_reg        ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|ApdsReset                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0000                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0001                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0010                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0011                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0100                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0101                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0110                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0111                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[0]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[10]                                                                                              ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[1]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[2]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[3]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[4]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[5]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[6]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[7]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[8]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[9]                                                                                               ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemInc                                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[10]                                                                                 ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[10]                                                                                  ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]                                                                                   ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF                                                                                       ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF1                                                                                      ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF2                                                                                      ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF9                                                                                      ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|HighWordOnBus                                                                                          ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|LastCs                                                                                                 ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[0]                                                                                              ;
; -1.285 ; 1.000        ; 2.285          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[10]                                                                                             ;
+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ApdDel[0]'                                                                                    ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; ApdDel[0] ; Rise       ; ApdDel[0]                                           ;
; -1.285 ; 1.000        ; 2.285          ; Min Period       ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; 0.270  ; 0.488        ; 0.218          ; High Pulse Width ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; 0.312  ; 0.312        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; ApdDel[0]~input|o                                   ;
; 0.321  ; 0.507        ; 0.186          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; 0.382  ; 0.382        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|datad   ;
; 0.416  ; 0.416        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|combout ;
; 0.469  ; 0.469        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|CDC_CAPT3|clk                                 ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; ApdDel[0]~input|i                                   ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; ApdDel[0]~input|i                                   ;
; 0.528  ; 0.528        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|CDC_CAPT3|clk                                 ;
; 0.583  ; 0.583        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|combout ;
; 0.617  ; 0.617        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|datad   ;
; 0.688  ; 0.688        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; ApdDel[0]~input|o                                   ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                       ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                 ; Clock Edge ; Target                                  ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+
; 0.440 ; 0.440        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[2]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[0]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[10]|datac                 ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[1]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[3]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[4]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[5]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[6]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[7]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[8]|datac                  ;
; 0.441 ; 0.441        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[9]|datac                  ;
; 0.445 ; 0.445        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[2]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[0]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[10] ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[1]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[3]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[4]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[5]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[6]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[7]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[8]  ;
; 0.446 ; 0.446        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[9]  ;
; 0.473 ; 0.473        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|inclk[0]        ;
; 0.473 ; 0.473        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|outclk          ;
; 0.500 ; 0.500        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3|q                       ;
; 0.500 ; 0.500        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3|q                       ;
; 0.526 ; 0.526        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|inclk[0]        ;
; 0.526 ; 0.526        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|outclk          ;
; 0.551 ; 0.551        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[10] ;
; 0.551 ; 0.551        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[6]  ;
; 0.551 ; 0.551        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[7]  ;
; 0.551 ; 0.551        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[8]  ;
; 0.552 ; 0.552        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[0]  ;
; 0.552 ; 0.552        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[1]  ;
; 0.552 ; 0.552        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[2]  ;
; 0.552 ; 0.552        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[3]  ;
; 0.552 ; 0.552        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[4]  ;
; 0.552 ; 0.552        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[5]  ;
; 0.552 ; 0.552        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[9]  ;
; 0.556 ; 0.556        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[10]|datac                 ;
; 0.556 ; 0.556        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[6]|datac                  ;
; 0.556 ; 0.556        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[7]|datac                  ;
; 0.556 ; 0.556        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[8]|datac                  ;
; 0.557 ; 0.557        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[0]|datac                  ;
; 0.557 ; 0.557        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[1]|datac                  ;
; 0.557 ; 0.557        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[2]|datac                  ;
; 0.557 ; 0.557        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[3]|datac                  ;
; 0.557 ; 0.557        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[4]|datac                  ;
; 0.557 ; 0.557        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[5]|datac                  ;
; 0.557 ; 0.557        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[9]|datac                  ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+


+-------------------------------------------------------------------------+
; Setup Times                                                             ;
+-------------+------------+-------+-------+------------+-----------------+
; Data Port   ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-------------+------------+-------+-------+------------+-----------------+
; Rcmd[*]     ; Clk        ; 1.912 ; 2.268 ; Rise       ; Clk             ;
;  Rcmd[0]    ; Clk        ; 1.730 ; 2.064 ; Rise       ; Clk             ;
;  Rcmd[1]    ; Clk        ; 1.758 ; 2.095 ; Rise       ; Clk             ;
;  Rcmd[2]    ; Clk        ; 1.912 ; 2.268 ; Rise       ; Clk             ;
; Rcs         ; Clk        ; 1.730 ; 2.033 ; Rise       ; Clk             ;
; Apd[*]      ; Clk        ; 2.363 ; 2.746 ; Fall       ; Clk             ;
;  Apd[0]     ; Clk        ; 2.363 ; 2.746 ; Fall       ; Clk             ;
;  Apd[1]     ; Clk        ; 2.306 ; 2.627 ; Fall       ; Clk             ;
;  Apd[2]     ; Clk        ; 1.661 ; 2.035 ; Fall       ; Clk             ;
;  Apd[3]     ; Clk        ; 2.348 ; 2.686 ; Fall       ; Clk             ;
;  Apd[4]     ; Clk        ; 2.349 ; 2.678 ; Fall       ; Clk             ;
;  Apd[5]     ; Clk        ; 2.147 ; 2.453 ; Fall       ; Clk             ;
;  Apd[6]     ; Clk        ; 1.781 ; 2.108 ; Fall       ; Clk             ;
;  Apd[7]     ; Clk        ; 2.337 ; 2.656 ; Fall       ; Clk             ;
;  Apd[8]     ; Clk        ; 2.072 ; 2.428 ; Fall       ; Clk             ;
;  Apd[9]     ; Clk        ; 2.046 ; 2.401 ; Fall       ; Clk             ;
;  Apd[10]    ; Clk        ; 1.621 ; 1.957 ; Fall       ; Clk             ;
; ApdDel[*]   ; Clk        ; 5.711 ; 5.756 ; Fall       ; Clk             ;
;  ApdDel[0]  ; Clk        ; 0.512 ; 0.487 ; Fall       ; Clk             ;
;  ApdDel[1]  ; Clk        ; 3.428 ; 3.596 ; Fall       ; Clk             ;
;  ApdDel[2]  ; Clk        ; 2.810 ; 3.013 ; Fall       ; Clk             ;
;  ApdDel[3]  ; Clk        ; 5.711 ; 5.756 ; Fall       ; Clk             ;
;  ApdDel[4]  ; Clk        ; 5.309 ; 5.397 ; Fall       ; Clk             ;
;  ApdDel[5]  ; Clk        ; 5.515 ; 5.569 ; Fall       ; Clk             ;
;  ApdDel[6]  ; Clk        ; 5.568 ; 5.578 ; Fall       ; Clk             ;
;  ApdDel[7]  ; Clk        ; 4.140 ; 4.342 ; Fall       ; Clk             ;
;  ApdDel[8]  ; Clk        ; 4.152 ; 4.349 ; Fall       ; Clk             ;
;  ApdDel[9]  ; Clk        ; 4.144 ; 4.272 ; Fall       ; Clk             ;
;  ApdDel[10] ; Clk        ; 4.014 ; 4.147 ; Fall       ; Clk             ;
+-------------+------------+-------+-------+------------+-----------------+


+---------------------------------------------------------------------------+
; Hold Times                                                                ;
+-------------+------------+--------+--------+------------+-----------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-------------+------------+--------+--------+------------+-----------------+
; Rcmd[*]     ; Clk        ; -1.361 ; -1.676 ; Rise       ; Clk             ;
;  Rcmd[0]    ; Clk        ; -1.361 ; -1.676 ; Rise       ; Clk             ;
;  Rcmd[1]    ; Clk        ; -1.388 ; -1.706 ; Rise       ; Clk             ;
;  Rcmd[2]    ; Clk        ; -1.549 ; -1.893 ; Rise       ; Clk             ;
; Rcs         ; Clk        ; -1.360 ; -1.646 ; Rise       ; Clk             ;
; Apd[*]      ; Clk        ; -1.211 ; -1.540 ; Fall       ; Clk             ;
;  Apd[0]     ; Clk        ; -1.887 ; -2.253 ; Fall       ; Clk             ;
;  Apd[1]     ; Clk        ; -1.865 ; -2.184 ; Fall       ; Clk             ;
;  Apd[2]     ; Clk        ; -1.245 ; -1.616 ; Fall       ; Clk             ;
;  Apd[3]     ; Clk        ; -1.906 ; -2.239 ; Fall       ; Clk             ;
;  Apd[4]     ; Clk        ; -1.907 ; -2.232 ; Fall       ; Clk             ;
;  Apd[5]     ; Clk        ; -1.712 ; -2.017 ; Fall       ; Clk             ;
;  Apd[6]     ; Clk        ; -1.363 ; -1.685 ; Fall       ; Clk             ;
;  Apd[7]     ; Clk        ; -1.895 ; -2.210 ; Fall       ; Clk             ;
;  Apd[8]     ; Clk        ; -1.641 ; -1.992 ; Fall       ; Clk             ;
;  Apd[9]     ; Clk        ; -1.618 ; -1.967 ; Fall       ; Clk             ;
;  Apd[10]    ; Clk        ; -1.211 ; -1.540 ; Fall       ; Clk             ;
; ApdDel[*]   ; Clk        ; -0.170 ; -0.158 ; Fall       ; Clk             ;
;  ApdDel[0]  ; Clk        ; -0.170 ; -0.158 ; Fall       ; Clk             ;
;  ApdDel[1]  ; Clk        ; -2.967 ; -3.142 ; Fall       ; Clk             ;
;  ApdDel[2]  ; Clk        ; -2.374 ; -2.582 ; Fall       ; Clk             ;
;  ApdDel[3]  ; Clk        ; -5.157 ; -5.216 ; Fall       ; Clk             ;
;  ApdDel[4]  ; Clk        ; -4.772 ; -4.870 ; Fall       ; Clk             ;
;  ApdDel[5]  ; Clk        ; -4.970 ; -5.035 ; Fall       ; Clk             ;
;  ApdDel[6]  ; Clk        ; -5.021 ; -5.045 ; Fall       ; Clk             ;
;  ApdDel[7]  ; Clk        ; -3.650 ; -3.858 ; Fall       ; Clk             ;
;  ApdDel[8]  ; Clk        ; -3.662 ; -3.865 ; Fall       ; Clk             ;
;  ApdDel[9]  ; Clk        ; -3.655 ; -3.791 ; Fall       ; Clk             ;
;  ApdDel[10] ; Clk        ; -3.535 ; -3.670 ; Fall       ; Clk             ;
+-------------+------------+--------+--------+------------+-----------------+


+-------------------------------------------------------------------------+
; Clock to Output Times                                                   ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; Rdat[*]   ; Clk        ; 12.282 ; 11.479 ; Rise       ; Clk             ;
;  Rdat[0]  ; Clk        ; 10.876 ; 10.484 ; Rise       ; Clk             ;
;  Rdat[1]  ; Clk        ; 10.734 ; 10.307 ; Rise       ; Clk             ;
;  Rdat[2]  ; Clk        ; 10.921 ; 10.517 ; Rise       ; Clk             ;
;  Rdat[3]  ; Clk        ; 10.409 ; 9.954  ; Rise       ; Clk             ;
;  Rdat[4]  ; Clk        ; 10.489 ; 10.058 ; Rise       ; Clk             ;
;  Rdat[5]  ; Clk        ; 10.438 ; 9.999  ; Rise       ; Clk             ;
;  Rdat[6]  ; Clk        ; 12.282 ; 11.479 ; Rise       ; Clk             ;
;  Rdat[7]  ; Clk        ; 9.613  ; 9.251  ; Rise       ; Clk             ;
;  Rdat[8]  ; Clk        ; 10.488 ; 10.077 ; Rise       ; Clk             ;
;  Rdat[9]  ; Clk        ; 9.900  ; 9.527  ; Rise       ; Clk             ;
;  Rdat[10] ; Clk        ; 9.982  ; 9.641  ; Rise       ; Clk             ;
;  Rdat[11] ; Clk        ; 10.125 ; 9.739  ; Rise       ; Clk             ;
;  Rdat[12] ; Clk        ; 9.474  ; 9.074  ; Rise       ; Clk             ;
;  Rdat[13] ; Clk        ; 9.792  ; 9.364  ; Rise       ; Clk             ;
;  Rdat[14] ; Clk        ; 12.189 ; 11.471 ; Rise       ; Clk             ;
;  Rdat[15] ; Clk        ; 9.753  ; 9.379  ; Rise       ; Clk             ;
; Rdat[*]   ; Clk        ; 9.775  ; 9.070  ; Fall       ; Clk             ;
;  Rdat[0]  ; Clk        ; 8.721  ; 8.342  ; Fall       ; Clk             ;
;  Rdat[1]  ; Clk        ; 8.238  ; 7.876  ; Fall       ; Clk             ;
;  Rdat[2]  ; Clk        ; 8.199  ; 7.899  ; Fall       ; Clk             ;
;  Rdat[3]  ; Clk        ; 7.562  ; 7.178  ; Fall       ; Clk             ;
;  Rdat[4]  ; Clk        ; 7.307  ; 6.943  ; Fall       ; Clk             ;
;  Rdat[5]  ; Clk        ; 7.575  ; 7.187  ; Fall       ; Clk             ;
;  Rdat[6]  ; Clk        ; 9.747  ; 9.004  ; Fall       ; Clk             ;
;  Rdat[7]  ; Clk        ; 7.535  ; 7.223  ; Fall       ; Clk             ;
;  Rdat[8]  ; Clk        ; 7.547  ; 7.230  ; Fall       ; Clk             ;
;  Rdat[9]  ; Clk        ; 6.975  ; 6.637  ; Fall       ; Clk             ;
;  Rdat[10] ; Clk        ; 7.601  ; 7.349  ; Fall       ; Clk             ;
;  Rdat[11] ; Clk        ; 7.773  ; 7.460  ; Fall       ; Clk             ;
;  Rdat[12] ; Clk        ; 7.543  ; 7.146  ; Fall       ; Clk             ;
;  Rdat[13] ; Clk        ; 7.852  ; 7.503  ; Fall       ; Clk             ;
;  Rdat[14] ; Clk        ; 9.775  ; 9.070  ; Fall       ; Clk             ;
;  Rdat[15] ; Clk        ; 7.094  ; 6.734  ; Fall       ; Clk             ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Rdat[*]   ; Clk        ; 7.333 ; 6.980 ; Rise       ; Clk             ;
;  Rdat[0]  ; Clk        ; 8.727 ; 8.333 ; Rise       ; Clk             ;
;  Rdat[1]  ; Clk        ; 8.598 ; 8.200 ; Rise       ; Clk             ;
;  Rdat[2]  ; Clk        ; 8.052 ; 7.732 ; Rise       ; Clk             ;
;  Rdat[3]  ; Clk        ; 7.805 ; 7.449 ; Rise       ; Clk             ;
;  Rdat[4]  ; Clk        ; 7.554 ; 7.249 ; Rise       ; Clk             ;
;  Rdat[5]  ; Clk        ; 7.832 ; 7.487 ; Rise       ; Clk             ;
;  Rdat[6]  ; Clk        ; 9.990 ; 9.274 ; Rise       ; Clk             ;
;  Rdat[7]  ; Clk        ; 7.530 ; 7.214 ; Rise       ; Clk             ;
;  Rdat[8]  ; Clk        ; 7.541 ; 7.221 ; Rise       ; Clk             ;
;  Rdat[9]  ; Clk        ; 7.333 ; 6.980 ; Rise       ; Clk             ;
;  Rdat[10] ; Clk        ; 7.555 ; 7.284 ; Rise       ; Clk             ;
;  Rdat[11] ; Clk        ; 7.721 ; 7.392 ; Rise       ; Clk             ;
;  Rdat[12] ; Clk        ; 7.589 ; 7.271 ; Rise       ; Clk             ;
;  Rdat[13] ; Clk        ; 7.932 ; 7.584 ; Rise       ; Clk             ;
;  Rdat[14] ; Clk        ; 9.783 ; 9.107 ; Rise       ; Clk             ;
;  Rdat[15] ; Clk        ; 7.485 ; 7.144 ; Rise       ; Clk             ;
; Rdat[*]   ; Clk        ; 6.814 ; 6.473 ; Fall       ; Clk             ;
;  Rdat[0]  ; Clk        ; 8.436 ; 8.098 ; Fall       ; Clk             ;
;  Rdat[1]  ; Clk        ; 8.003 ; 7.640 ; Fall       ; Clk             ;
;  Rdat[2]  ; Clk        ; 7.979 ; 7.636 ; Fall       ; Clk             ;
;  Rdat[3]  ; Clk        ; 7.374 ; 6.993 ; Fall       ; Clk             ;
;  Rdat[4]  ; Clk        ; 7.114 ; 6.783 ; Fall       ; Clk             ;
;  Rdat[5]  ; Clk        ; 7.368 ; 6.979 ; Fall       ; Clk             ;
;  Rdat[6]  ; Clk        ; 9.558 ; 8.818 ; Fall       ; Clk             ;
;  Rdat[7]  ; Clk        ; 7.300 ; 6.967 ; Fall       ; Clk             ;
;  Rdat[8]  ; Clk        ; 7.311 ; 6.974 ; Fall       ; Clk             ;
;  Rdat[9]  ; Clk        ; 6.814 ; 6.473 ; Fall       ; Clk             ;
;  Rdat[10] ; Clk        ; 7.397 ; 7.056 ; Fall       ; Clk             ;
;  Rdat[11] ; Clk        ; 7.564 ; 7.163 ; Fall       ; Clk             ;
;  Rdat[12] ; Clk        ; 7.293 ; 6.957 ; Fall       ; Clk             ;
;  Rdat[13] ; Clk        ; 7.674 ; 7.236 ; Fall       ; Clk             ;
;  Rdat[14] ; Clk        ; 9.530 ; 8.870 ; Fall       ; Clk             ;
;  Rdat[15] ; Clk        ; 6.932 ; 6.569 ; Fall       ; Clk             ;
+-----------+------------+-------+-------+------------+-----------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+-------+--------+-------------------+
; Clock ; Slack  ; End Point TNS     ;
+-------+--------+-------------------+
; Clk   ; -3.164 ; -119.891          ;
+-------+--------+-------------------+


+-----------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+-------+--------+------------------+
; Clock ; Slack  ; End Point TNS    ;
+-------+--------+------------------+
; Clk   ; -0.051 ; -0.051           ;
+-------+--------+------------------+


+----------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                          ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -1.201 ; -11.486       ;
; ApdDel[0]                             ; -0.294 ; -0.294        ;
+---------------------------------------+--------+---------------+


+---------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                          ;
+---------------------------------------+-------+---------------+
; Clock                                 ; Slack ; End Point TNS ;
+---------------------------------------+-------+---------------+
; ApdDel[0]                             ; 0.924 ; 0.000         ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 1.337 ; 0.000         ;
+---------------------------------------+-------+---------------+


+----------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary               ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; Clk                                   ; -3.000 ; -206.969      ;
; ApdDel[0]                             ; -3.000 ; -4.918        ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.410  ; 0.000         ;
+---------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'Clk'                                                                                                                                                                                                                                                                                             ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                           ; To Node                                                                                                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -3.164 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.046     ; 4.127      ;
; -3.155 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.045     ; 4.119      ;
; -3.142 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.045     ; 4.106      ;
; -3.119 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.030     ; 4.098      ;
; -3.117 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.046     ; 4.080      ;
; -3.108 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.045     ; 4.072      ;
; -3.072 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.048     ; 4.033      ;
; -3.059 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.044     ; 4.024      ;
; -3.050 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.047     ; 4.012      ;
; -3.046 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.051     ; 4.004      ;
; -3.046 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.030     ; 4.025      ;
; -3.045 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.051     ; 4.003      ;
; -3.045 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.045     ; 4.009      ;
; -3.030 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.047     ; 3.992      ;
; -3.025 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.048     ; 3.986      ;
; -3.023 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.988      ;
; -3.018 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.042     ; 3.985      ;
; -3.013 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.978      ;
; -3.009 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.977      ;
; -3.008 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.046     ; 3.971      ;
; -2.998 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.030     ; 3.977      ;
; -2.998 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.045     ; 3.962      ;
; -2.986 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.045     ; 3.950      ;
; -2.983 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.047     ; 3.945      ;
; -2.977 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.942      ;
; -2.922 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.048     ; 3.883      ;
; -2.921 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.048     ; 3.882      ;
; -2.918 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.883      ;
; -2.914 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.045     ; 3.878      ;
; -2.912 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.030     ; 3.891      ;
; -2.912 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.030     ; 3.891      ;
; -2.899 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.867      ;
; -2.894 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.047     ; 3.856      ;
; -2.892 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.857      ;
; -2.890 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.051     ; 3.848      ;
; -2.889 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.051     ; 3.847      ;
; -2.884 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.043     ; 3.850      ;
; -2.867 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.045     ; 3.831      ;
; -2.853 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.030     ; 3.832      ;
; -2.852 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.046     ; 3.815      ;
; -2.841 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.045     ; 3.805      ;
; -2.835 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.047     ; 3.797      ;
; -2.832 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.797      ;
; -2.831 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.051     ; 3.789      ;
; -2.830 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.051     ; 3.788      ;
; -2.808 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.773      ;
; -2.799 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.764      ;
; -2.793 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.046     ; 3.756      ;
; -2.790 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.043     ; 3.756      ;
; -2.768 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.736      ;
; -2.749 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.047     ; 3.711      ;
; -2.745 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.051     ; 3.703      ;
; -2.744 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.051     ; 3.702      ;
; -2.736 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.701      ;
; -2.722 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.687      ;
; -2.707 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.046     ; 3.670      ;
; -2.707 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.046     ; 3.670      ;
; -2.703 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.050     ; 3.662      ;
; -2.702 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk          ; Clk         ; 1.000        ; -0.050     ; 3.661      ;
; -2.700 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.665      ;
; -2.680 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.043     ; 3.646      ;
; -2.678 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.043     ; 3.644      ;
; -2.677 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.642      ;
; -2.653 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.618      ;
; -2.650 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.030     ; 3.629      ;
; -2.594 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.042     ; 3.561      ;
; -2.577 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.030     ; 3.556      ;
; -2.572 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.540      ;
; -2.554 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.040     ; 3.523      ;
; -2.549 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk          ; Clk         ; 1.000        ; -0.043     ; 3.515      ;
; -2.547 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.042     ; 3.514      ;
; -2.522 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.043     ; 3.488      ;
; -2.493 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.042     ; 3.460      ;
; -2.471 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.439      ;
; -2.463 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.043     ; 3.429      ;
; -2.448 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.038     ; 3.419      ;
; -2.446 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.042     ; 3.413      ;
; -2.416 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.384      ;
; -2.401 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.048     ; 3.362      ;
; -2.401 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.027     ; 3.383      ;
; -2.393 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.045     ; 3.357      ;
; -2.377 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.043     ; 3.343      ;
; -2.373 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.338      ;
; -2.368 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.336      ;
; -2.357 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.325      ;
; -2.347 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.038     ; 3.318      ;
; -2.346 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.045     ; 3.310      ;
; -2.320 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.027     ; 3.302      ;
; -2.301 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.027     ; 3.283      ;
; -2.277 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.045     ; 3.241      ;
; -2.275 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.243      ;
; -2.261 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.048     ; 3.222      ;
; -2.257 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.027     ; 3.239      ;
; -2.256 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.041     ; 3.224      ;
; -2.245 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.048     ; 3.206      ;
; -2.233 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.027     ; 3.215      ;
; -2.229 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk          ; Clk         ; 1.000        ; -0.040     ; 3.198      ;
; -2.215 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.044     ; 3.180      ;
; -2.214 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.027     ; 3.196      ;
; -2.204 ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_datain_reg0  ; Clk          ; Clk         ; 1.000        ; -0.042     ; 3.171      ;
+--------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'Clk'                                                                                                                                                            ;
+--------+------------------------------------------+------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                ; To Node                                  ; Launch Clock                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------+------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+
; -0.051 ; ApdDel[0]                                ; CoincidenceAsyncInput:inst1|CDC_OFF9     ; ApdDel[0]                             ; Clk         ; -0.500       ; 1.727      ; 1.290      ;
; 0.069  ; ApdDel[0]                                ; CoincidenceAsyncInput:inst1|CDC_OFF9     ; ApdDel[0]                             ; Clk         ; 0.000        ; 1.727      ; 1.910      ;
; 0.116  ; inst7[2]                                 ; RabbitControl:inst|TestDataState[0]      ; Clk                                   ; Clk         ; -0.500       ; 0.609      ; 0.329      ;
; 0.123  ; CoincidenceAsyncInput:inst1|Capture[10]  ; CoincidenceAsyncInput:inst1|CDC_CAPT[10] ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.627      ; 0.364      ;
; 0.126  ; CoincidenceAsyncInput:inst1|Capture[4]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.626      ; 0.366      ;
; 0.134  ; CoincidenceAsyncInput:inst1|Capture[2]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.632      ; 0.380      ;
; 0.136  ; CoincidenceAsyncInput:inst1|Capture[9]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.629      ; 0.379      ;
; 0.182  ; CoincidenceAsyncInput:inst1|Capture[6]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.629      ; 0.425      ;
; 0.184  ; RabbitControl:inst|TestDataState[0]      ; RabbitControl:inst|TestDataState[0]      ; Clk                                   ; Clk         ; 0.000        ; 0.039      ; 0.307      ;
; 0.185  ; CoinCounter:inst2|MemInc                 ; CoinCounter:inst2|MemInc                 ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; CoinCounter:inst2|CoinState.0001         ; CoinCounter:inst2|CoinState.0001         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; RabbitControl:inst|RunEn                 ; RabbitControl:inst|RunEn                 ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; RabbitControl:inst|HighWordOnBus         ; RabbitControl:inst|HighWordOnBus         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; RabbitControl:inst|LastCs                ; RabbitControl:inst|LastCs                ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; RabbitControl:inst|TestDataState[1]      ; RabbitControl:inst|TestDataState[1]      ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.307      ;
; 0.185  ; CoinCounter:inst2|ApdsReset              ; CoinCounter:inst2|ApdsReset              ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.307      ;
; 0.186  ; CoincidenceAsyncInput:inst1|Capture[7]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.627      ; 0.427      ;
; 0.188  ; CoincidenceAsyncInput:inst1|Capture[1]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.625      ; 0.427      ;
; 0.188  ; CoincidenceAsyncInput:inst1|Capture[0]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.633      ; 0.435      ;
; 0.190  ; CoinCounter:inst2|CoinState.0010         ; CoinCounter:inst2|CoinState.0011         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.312      ;
; 0.192  ; CoinCounter:inst2|CoinState.0110         ; CoinCounter:inst2|CoinState.0111         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.314      ;
; 0.192  ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4] ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.314      ;
; 0.193  ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3] ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.315      ;
; 0.195  ; CoincidenceAsyncInput:inst1|Capture[5]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.633      ; 0.442      ;
; 0.201  ; CoincidenceAsyncInput:inst1|Capture[3]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.625      ; 0.440      ;
; 0.210  ; CoinCounter:inst2|CoinState.0000         ; CoinCounter:inst2|MemInc                 ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.332      ;
; 0.215  ; CoinCounter:inst2|CoinState.0000         ; CoinCounter:inst2|CoinState.0001         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.337      ;
; 0.215  ; CoincidenceAsyncInput:inst1|Capture[8]   ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk         ; -0.500       ; 0.632      ; 0.461      ;
; 0.219  ; RabbitControl:inst|MemAdd[10]            ; RabbitControl:inst|MemAdd[10]            ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.341      ;
; 0.229  ; inst7[2]                                 ; RabbitControl:inst|MemWrEn               ; Clk                                   ; Clk         ; -0.500       ; 0.607      ; 0.440      ;
; 0.230  ; inst7[2]                                 ; RabbitControl:inst|TestDataState[1]      ; Clk                                   ; Clk         ; -0.500       ; 0.607      ; 0.441      ;
; 0.241  ; inst7[1]                                 ; RabbitControl:inst|MemWrEn               ; Clk                                   ; Clk         ; -0.500       ; 0.608      ; 0.453      ;
; 0.260  ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6] ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.382      ;
; 0.262  ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0] ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.384      ;
; 0.264  ; inst6[2]                                 ; inst7[2]                                 ; Clk                                   ; Clk         ; 0.000        ; 0.036      ; 0.384      ;
; 0.267  ; CoinCounter:inst2|CoinState.0011         ; CoinCounter:inst2|CoinState.0100         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.389      ;
; 0.271  ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5] ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.393      ;
; 0.272  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7] ; CoinCounter:inst2|MemAdd[7]              ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.393      ;
; 0.276  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2] ; CoinCounter:inst2|MemAdd[2]              ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.397      ;
; 0.282  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9] ; CoinCounter:inst2|MemAdd[9]              ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.403      ;
; 0.298  ; inst9                                    ; RabbitControl:inst|LastCs                ; Clk                                   ; Clk         ; -0.500       ; 0.608      ; 0.510      ;
; 0.300  ; CoinCounter:inst2|CoinState.0100         ; CoinCounter:inst2|CoinState.0101         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.422      ;
; 0.303  ; CoinCounter:inst2|CoinState.0111         ; CoinCounter:inst2|MemInc                 ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.425      ;
; 0.305  ; inst9                                    ; RabbitControl:inst|RunEn                 ; Clk                                   ; Clk         ; -0.500       ; 0.608      ; 0.517      ;
; 0.308  ; CoincidenceAsyncInput:inst1|CDC_OFF2     ; CoinCounter:inst2|CoinState.0010         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.430      ;
; 0.309  ; RabbitControl:inst|MemAdd[9]             ; RabbitControl:inst|MemAdd[9]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.431      ;
; 0.309  ; RabbitControl:inst|MemAdd[7]             ; RabbitControl:inst|MemAdd[7]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.431      ;
; 0.309  ; RabbitControl:inst|MemAdd[6]             ; RabbitControl:inst|MemAdd[6]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.431      ;
; 0.309  ; RabbitControl:inst|MemAdd[5]             ; RabbitControl:inst|MemAdd[5]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.431      ;
; 0.312  ; inst7[0]                                 ; RabbitControl:inst|HighWordOnBus         ; Clk                                   ; Clk         ; -0.500       ; 0.608      ; 0.524      ;
; 0.314  ; RabbitControl:inst|TestDataState[1]      ; RabbitControl:inst|TestDataState[0]~0    ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.436      ;
; 0.314  ; CoincidenceAsyncInput:inst1|CDC_OFF2     ; CoinCounter:inst2|CoinState.0101         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.436      ;
; 0.317  ; RabbitControl:inst|MemAdd[8]             ; RabbitControl:inst|MemAdd[8]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.439      ;
; 0.318  ; RabbitControl:inst|MemAdd[3]             ; RabbitControl:inst|MemAdd[3]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.440      ;
; 0.319  ; RabbitControl:inst|MemAdd[1]             ; RabbitControl:inst|MemAdd[1]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.441      ;
; 0.320  ; RabbitControl:inst|MemAdd[4]             ; RabbitControl:inst|MemAdd[4]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.442      ;
; 0.322  ; RabbitControl:inst|MemAdd[2]             ; RabbitControl:inst|MemAdd[2]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.444      ;
; 0.332  ; RabbitControl:inst|MemAdd[0]             ; RabbitControl:inst|MemAdd[0]             ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.454      ;
; 0.339  ; CoinCounter:inst2|CoinState.0100         ; CoinCounter:inst2|CoinState.0000         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.461      ;
; 0.344  ; inst7[2]                                 ; RabbitControl:inst|TestDataState[0]~0    ; Clk                                   ; Clk         ; -0.500       ; 0.607      ; 0.555      ;
; 0.345  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8] ; CoinCounter:inst2|MemAdd[8]              ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.466      ;
; 0.347  ; RabbitControl:inst|MemAdd[6]             ; RabbitControl:inst|MemWr[24]             ; Clk                                   ; Clk         ; 0.000        ; 0.268      ; 0.699      ;
; 0.348  ; inst6[1]                                 ; inst7[1]                                 ; Clk                                   ; Clk         ; 0.000        ; 0.035      ; 0.467      ;
; 0.354  ; RabbitControl:inst|TestDataState[0]      ; RabbitControl:inst|TestDataState[0]~0    ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.475      ;
; 0.355  ; inst7[2]                                 ; RabbitControl:inst|RunEn                 ; Clk                                   ; Clk         ; -0.500       ; 0.607      ; 0.566      ;
; 0.358  ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9] ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.479      ;
; 0.359  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1] ; CoinCounter:inst2|MemAdd[1]              ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.480      ;
; 0.360  ; RabbitControl:inst|MemAdd[0]             ; RabbitControl:inst|MemWr[31]             ; Clk                                   ; Clk         ; 0.000        ; 0.268      ; 0.712      ;
; 0.362  ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8] ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.483      ;
; 0.369  ; inst7[2]                                 ; RabbitControl:inst|MemWr[14]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.804      ;
; 0.369  ; inst7[2]                                 ; RabbitControl:inst|MemWr[13]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.804      ;
; 0.369  ; inst7[2]                                 ; RabbitControl:inst|MemWr[24]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.804      ;
; 0.369  ; inst7[2]                                 ; RabbitControl:inst|MemWr[18]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.804      ;
; 0.369  ; inst7[2]                                 ; RabbitControl:inst|MemWr[19]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.804      ;
; 0.369  ; inst7[2]                                 ; RabbitControl:inst|MemWr[16]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.804      ;
; 0.369  ; inst7[2]                                 ; RabbitControl:inst|MemWr[17]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.804      ;
; 0.369  ; RabbitControl:inst|MemAdd[0]             ; RabbitControl:inst|MemWr[30]             ; Clk                                   ; Clk         ; 0.000        ; 0.268      ; 0.721      ;
; 0.370  ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2] ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.491      ;
; 0.370  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4] ; CoinCounter:inst2|MemAdd[4]              ; Clk                                   ; Clk         ; 0.000        ; 0.036      ; 0.490      ;
; 0.372  ; CoinCounter:inst2|CoinState.0001         ; CoinCounter:inst2|CoinState.0010         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.494      ;
; 0.373  ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1] ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.494      ;
; 0.384  ; CoinCounter:inst2|CoinState.0111         ; CoinCounter:inst2|CoinState.0000         ; Clk                                   ; Clk         ; 0.000        ; 0.038      ; 0.506      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[28]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[29]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[26]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[27]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[25]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[22]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[23]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[21]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[30]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.385  ; inst7[2]                                 ; RabbitControl:inst|MemWr[31]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.820      ;
; 0.392  ; inst7[0]                                 ; RabbitControl:inst|TestDataState[0]~0    ; Clk                                   ; Clk         ; -0.500       ; 0.608      ; 0.604      ;
; 0.399  ; RabbitControl:inst|TestDataState[0]      ; RabbitControl:inst|TestDataState[1]      ; Clk                                   ; Clk         ; 0.000        ; 0.037      ; 0.520      ;
; 0.407  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3] ; CoinCounter:inst2|MemAdd[3]              ; Clk                                   ; Clk         ; 0.000        ; 0.036      ; 0.527      ;
; 0.408  ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6] ; CoinCounter:inst2|MemAdd[6]              ; Clk                                   ; Clk         ; 0.000        ; 0.036      ; 0.528      ;
; 0.412  ; inst7[2]                                 ; RabbitControl:inst|MemWr[12]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.847      ;
; 0.412  ; inst7[2]                                 ; RabbitControl:inst|MemWr[20]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.847      ;
; 0.412  ; inst7[2]                                 ; RabbitControl:inst|MemWr[15]             ; Clk                                   ; Clk         ; -0.500       ; 0.831      ; 0.847      ;
; 0.415  ; inst7[1]                                 ; RabbitControl:inst|RunEn                 ; Clk                                   ; Clk         ; -0.500       ; 0.608      ; 0.627      ;
+--------+------------------------------------------+------------------------------------------+---------------------------------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                                                         ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                 ; Launch Clock ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; -1.201 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[5]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.633     ; 0.399      ;
; -1.032 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[2]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.632     ; 0.398      ;
; -1.032 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[8]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.632     ; 0.398      ;
; -1.032 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[9]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.629     ; 0.400      ;
; -1.030 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[10] ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.627     ; 0.400      ;
; -1.030 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[0]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.633     ; 0.397      ;
; -1.027 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[7]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.627     ; 0.401      ;
; -1.027 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[6]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.629     ; 0.399      ;
; -1.026 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[3]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.625     ; 0.402      ;
; -1.025 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[4]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.626     ; 0.401      ;
; -1.024 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[1]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0.500        ; -0.625     ; 0.401      ;
+--------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'ApdDel[0]'                                                                                                         ;
+--------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; -0.294 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk          ; ApdDel[0]   ; 0.500        ; 0.189      ; 0.960      ;
+--------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'ApdDel[0]'                                                                                                         ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.924 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk          ; ApdDel[0]   ; -0.500       ; 0.317      ; 0.855      ;
+-------+-----------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                                                         ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                                 ; Launch Clock ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+
; 1.337 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[10] ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.535     ; 0.332      ;
; 1.337 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[4]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.533     ; 0.334      ;
; 1.338 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[9]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.537     ; 0.331      ;
; 1.338 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[7]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.535     ; 0.333      ;
; 1.338 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[1]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.533     ; 0.335      ;
; 1.338 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[6]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.537     ; 0.331      ;
; 1.338 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[3]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.533     ; 0.335      ;
; 1.341 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[2]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.540     ; 0.331      ;
; 1.341 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[8]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.540     ; 0.331      ;
; 1.342 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[0]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.541     ; 0.331      ;
; 1.342 ; CoinCounter:inst2|ApdsReset ; CoincidenceAsyncInput:inst1|Capture[5]  ; Clk          ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; -0.500       ; -0.541     ; 0.331      ;
+-------+-----------------------------+-----------------------------------------+--------------+---------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'Clk'                                                                      ;
+--------+--------------+----------------+------------+-------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------+-------+------------+-------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; Clk   ; Rise       ; Clk                                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|ApdsReset               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0000          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0001          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0010          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0011          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0100          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0101          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0110          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|CoinState.0111          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[0]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[10]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[1]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[2]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[3]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[4]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[5]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[6]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[7]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[8]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemAdd[9]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoinCounter:inst2|MemInc                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[10]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF1      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF2      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; CoincidenceAsyncInput:inst1|CDC_OFF9      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|HighWordOnBus          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|LastCs                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[0]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[10]             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[1]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[2]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[3]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[4]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[5]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[6]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[7]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[8]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemAdd[9]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWrEn                ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[0]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[10]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[11]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[12]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[13]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[14]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[15]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[16]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[17]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[18]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[19]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[1]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[20]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[21]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[22]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[23]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[24]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[25]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[26]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[27]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[28]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[29]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[2]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[30]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[31]              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[3]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[4]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[5]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[6]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[7]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[8]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|MemWr[9]               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|RunEn                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|TestDataState[0]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|TestDataState[0]~0     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Fall       ; RabbitControl:inst|TestDataState[1]       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Rise       ; inst6[0]                                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; Clk   ; Rise       ; inst6[1]                                  ;
+--------+--------------+----------------+------------+-------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ApdDel[0]'                                                                                    ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; ApdDel[0] ; Rise       ; ApdDel[0]                                           ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; -0.428 ; -0.244       ; 0.184          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; -0.248 ; -0.248       ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|CDC_CAPT3|clk                                 ;
; -0.094 ; -0.094       ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|datad   ;
; -0.089 ; -0.089       ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|combout ;
; -0.059 ; -0.059       ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; ApdDel[0]~input|o                                   ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; ApdDel[0]~input|i                                   ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ApdDel[0] ; Rise       ; ApdDel[0]~input|i                                   ;
; 1.019  ; 1.235        ; 0.216          ; High Pulse Width ; ApdDel[0] ; Rise       ; CoincidenceAsyncInput:inst1|CDC_CAPT3               ;
; 1.059  ; 1.059        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; ApdDel[0]~input|o                                   ;
; 1.088  ; 1.088        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|combout ;
; 1.092  ; 1.092        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|inst4|lpm_or_component|or_node[0][10]|datad   ;
; 1.241  ; 1.241        ; 0.000          ; High Pulse Width ; ApdDel[0] ; Rise       ; inst1|CDC_CAPT3|clk                                 ;
+--------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CoincidenceAsyncInput:inst1|CDC_CAPT3'                                                                       ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                 ; Clock Edge ; Target                                  ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[0]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[10]|datac                 ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[1]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[2]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[3]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[4]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[5]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[6]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[7]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[8]|datac                  ;
; 0.410 ; 0.410        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[9]|datac                  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[0]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[10] ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[1]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[2]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[3]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[4]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[5]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[6]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[7]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[8]  ;
; 0.414 ; 0.414        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[9]  ;
; 0.474 ; 0.474        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|inclk[0]        ;
; 0.474 ; 0.474        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|outclk          ;
; 0.500 ; 0.500        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3|q                       ;
; 0.500 ; 0.500        ; 0.000          ; Low Pulse Width  ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3|q                       ;
; 0.525 ; 0.525        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|inclk[0]        ;
; 0.525 ; 0.525        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|CDC_CAPT3~clkctrl|outclk          ;
; 0.582 ; 0.582        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[0]  ;
; 0.582 ; 0.582        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[1]  ;
; 0.582 ; 0.582        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[3]  ;
; 0.582 ; 0.582        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[5]  ;
; 0.582 ; 0.582        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[6]  ;
; 0.582 ; 0.582        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[8]  ;
; 0.582 ; 0.582        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[9]  ;
; 0.583 ; 0.583        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[10] ;
; 0.583 ; 0.583        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[2]  ;
; 0.583 ; 0.583        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[4]  ;
; 0.583 ; 0.583        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; CoincidenceAsyncInput:inst1|Capture[7]  ;
; 0.586 ; 0.586        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[0]|datac                  ;
; 0.586 ; 0.586        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[1]|datac                  ;
; 0.586 ; 0.586        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[3]|datac                  ;
; 0.586 ; 0.586        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[5]|datac                  ;
; 0.586 ; 0.586        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[6]|datac                  ;
; 0.586 ; 0.586        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[8]|datac                  ;
; 0.586 ; 0.586        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[9]|datac                  ;
; 0.587 ; 0.587        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[10]|datac                 ;
; 0.587 ; 0.587        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[2]|datac                  ;
; 0.587 ; 0.587        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[4]|datac                  ;
; 0.587 ; 0.587        ; 0.000          ; High Pulse Width ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Rise       ; inst1|Capture[7]|datac                  ;
+-------+--------------+----------------+------------------+---------------------------------------+------------+-----------------------------------------+


+--------------------------------------------------------------------------+
; Setup Times                                                              ;
+-------------+------------+--------+-------+------------+-----------------+
; Data Port   ; Clock Port ; Rise   ; Fall  ; Clock Edge ; Clock Reference ;
+-------------+------------+--------+-------+------------+-----------------+
; Rcmd[*]     ; Clk        ; 1.124  ; 1.872 ; Rise       ; Clk             ;
;  Rcmd[0]    ; Clk        ; 1.033  ; 1.786 ; Rise       ; Clk             ;
;  Rcmd[1]    ; Clk        ; 1.045  ; 1.804 ; Rise       ; Clk             ;
;  Rcmd[2]    ; Clk        ; 1.124  ; 1.872 ; Rise       ; Clk             ;
; Rcs         ; Clk        ; 1.008  ; 1.764 ; Rise       ; Clk             ;
; Apd[*]      ; Clk        ; 0.889  ; 1.760 ; Fall       ; Clk             ;
;  Apd[0]     ; Clk        ; 0.889  ; 1.760 ; Fall       ; Clk             ;
;  Apd[1]     ; Clk        ; 0.849  ; 1.691 ; Fall       ; Clk             ;
;  Apd[2]     ; Clk        ; 0.548  ; 1.345 ; Fall       ; Clk             ;
;  Apd[3]     ; Clk        ; 0.853  ; 1.677 ; Fall       ; Clk             ;
;  Apd[4]     ; Clk        ; 0.857  ; 1.667 ; Fall       ; Clk             ;
;  Apd[5]     ; Clk        ; 0.741  ; 1.541 ; Fall       ; Clk             ;
;  Apd[6]     ; Clk        ; 0.560  ; 1.357 ; Fall       ; Clk             ;
;  Apd[7]     ; Clk        ; 0.853  ; 1.665 ; Fall       ; Clk             ;
;  Apd[8]     ; Clk        ; 0.725  ; 1.520 ; Fall       ; Clk             ;
;  Apd[9]     ; Clk        ; 0.709  ; 1.494 ; Fall       ; Clk             ;
;  Apd[10]    ; Clk        ; 0.471  ; 1.225 ; Fall       ; Clk             ;
; ApdDel[*]   ; Clk        ; 2.534  ; 3.494 ; Fall       ; Clk             ;
;  ApdDel[0]  ; Clk        ; -0.339 ; 0.276 ; Fall       ; Clk             ;
;  ApdDel[1]  ; Clk        ; 1.366  ; 2.169 ; Fall       ; Clk             ;
;  ApdDel[2]  ; Clk        ; 1.075  ; 1.853 ; Fall       ; Clk             ;
;  ApdDel[3]  ; Clk        ; 2.534  ; 3.494 ; Fall       ; Clk             ;
;  ApdDel[4]  ; Clk        ; 2.313  ; 3.250 ; Fall       ; Clk             ;
;  ApdDel[5]  ; Clk        ; 2.414  ; 3.362 ; Fall       ; Clk             ;
;  ApdDel[6]  ; Clk        ; 2.439  ; 3.406 ; Fall       ; Clk             ;
;  ApdDel[7]  ; Clk        ; 1.756  ; 2.645 ; Fall       ; Clk             ;
;  ApdDel[8]  ; Clk        ; 1.767  ; 2.654 ; Fall       ; Clk             ;
;  ApdDel[9]  ; Clk        ; 1.742  ; 2.629 ; Fall       ; Clk             ;
;  ApdDel[10] ; Clk        ; 1.668  ; 2.506 ; Fall       ; Clk             ;
+-------------+------------+--------+-------+------------+-----------------+


+---------------------------------------------------------------------------+
; Hold Times                                                                ;
+-------------+------------+--------+--------+------------+-----------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-------------+------------+--------+--------+------------+-----------------+
; Rcmd[*]     ; Clk        ; -0.829 ; -1.568 ; Rise       ; Clk             ;
;  Rcmd[0]    ; Clk        ; -0.829 ; -1.568 ; Rise       ; Clk             ;
;  Rcmd[1]    ; Clk        ; -0.839 ; -1.584 ; Rise       ; Clk             ;
;  Rcmd[2]    ; Clk        ; -0.921 ; -1.663 ; Rise       ; Clk             ;
; Rcs         ; Clk        ; -0.804 ; -1.547 ; Rise       ; Clk             ;
; Apd[*]      ; Clk        ; -0.237 ; -0.994 ; Fall       ; Clk             ;
;  Apd[0]     ; Clk        ; -0.628 ; -1.483 ; Fall       ; Clk             ;
;  Apd[1]     ; Clk        ; -0.603 ; -1.442 ; Fall       ; Clk             ;
;  Apd[2]     ; Clk        ; -0.312 ; -1.108 ; Fall       ; Clk             ;
;  Apd[3]     ; Clk        ; -0.607 ; -1.428 ; Fall       ; Clk             ;
;  Apd[4]     ; Clk        ; -0.612 ; -1.418 ; Fall       ; Clk             ;
;  Apd[5]     ; Clk        ; -0.499 ; -1.297 ; Fall       ; Clk             ;
;  Apd[6]     ; Clk        ; -0.326 ; -1.121 ; Fall       ; Clk             ;
;  Apd[7]     ; Clk        ; -0.607 ; -1.416 ; Fall       ; Clk             ;
;  Apd[8]     ; Clk        ; -0.484 ; -1.278 ; Fall       ; Clk             ;
;  Apd[9]     ; Clk        ; -0.467 ; -1.252 ; Fall       ; Clk             ;
;  Apd[10]    ; Clk        ; -0.237 ; -0.994 ; Fall       ; Clk             ;
; ApdDel[*]   ; Clk        ; 0.521  ; -0.099 ; Fall       ; Clk             ;
;  ApdDel[0]  ; Clk        ; 0.521  ; -0.099 ; Fall       ; Clk             ;
;  ApdDel[1]  ; Clk        ; -1.116 ; -1.917 ; Fall       ; Clk             ;
;  ApdDel[2]  ; Clk        ; -0.837 ; -1.613 ; Fall       ; Clk             ;
;  ApdDel[3]  ; Clk        ; -2.236 ; -3.188 ; Fall       ; Clk             ;
;  ApdDel[4]  ; Clk        ; -2.026 ; -2.955 ; Fall       ; Clk             ;
;  ApdDel[5]  ; Clk        ; -2.122 ; -3.062 ; Fall       ; Clk             ;
;  ApdDel[6]  ; Clk        ; -2.146 ; -3.105 ; Fall       ; Clk             ;
;  ApdDel[7]  ; Clk        ; -1.490 ; -2.374 ; Fall       ; Clk             ;
;  ApdDel[8]  ; Clk        ; -1.502 ; -2.383 ; Fall       ; Clk             ;
;  ApdDel[9]  ; Clk        ; -1.476 ; -2.358 ; Fall       ; Clk             ;
;  ApdDel[10] ; Clk        ; -1.404 ; -2.240 ; Fall       ; Clk             ;
+-------------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Rdat[*]   ; Clk        ; 6.914 ; 6.470 ; Rise       ; Clk             ;
;  Rdat[0]  ; Clk        ; 5.610 ; 5.772 ; Rise       ; Clk             ;
;  Rdat[1]  ; Clk        ; 5.525 ; 5.674 ; Rise       ; Clk             ;
;  Rdat[2]  ; Clk        ; 5.630 ; 5.777 ; Rise       ; Clk             ;
;  Rdat[3]  ; Clk        ; 5.316 ; 5.414 ; Rise       ; Clk             ;
;  Rdat[4]  ; Clk        ; 5.394 ; 5.475 ; Rise       ; Clk             ;
;  Rdat[5]  ; Clk        ; 5.363 ; 5.461 ; Rise       ; Clk             ;
;  Rdat[6]  ; Clk        ; 6.914 ; 6.470 ; Rise       ; Clk             ;
;  Rdat[7]  ; Clk        ; 4.945 ; 4.984 ; Rise       ; Clk             ;
;  Rdat[8]  ; Clk        ; 5.402 ; 5.493 ; Rise       ; Clk             ;
;  Rdat[9]  ; Clk        ; 5.117 ; 5.155 ; Rise       ; Clk             ;
;  Rdat[10] ; Clk        ; 5.155 ; 5.209 ; Rise       ; Clk             ;
;  Rdat[11] ; Clk        ; 5.220 ; 5.285 ; Rise       ; Clk             ;
;  Rdat[12] ; Clk        ; 4.849 ; 4.878 ; Rise       ; Clk             ;
;  Rdat[13] ; Clk        ; 5.001 ; 5.031 ; Rise       ; Clk             ;
;  Rdat[14] ; Clk        ; 6.896 ; 6.445 ; Rise       ; Clk             ;
;  Rdat[15] ; Clk        ; 5.010 ; 5.053 ; Rise       ; Clk             ;
; Rdat[*]   ; Clk        ; 6.353 ; 5.874 ; Fall       ; Clk             ;
;  Rdat[0]  ; Clk        ; 5.219 ; 5.364 ; Fall       ; Clk             ;
;  Rdat[1]  ; Clk        ; 4.989 ; 5.083 ; Fall       ; Clk             ;
;  Rdat[2]  ; Clk        ; 4.979 ; 5.002 ; Fall       ; Clk             ;
;  Rdat[3]  ; Clk        ; 4.569 ; 4.592 ; Fall       ; Clk             ;
;  Rdat[4]  ; Clk        ; 4.444 ; 4.451 ; Fall       ; Clk             ;
;  Rdat[5]  ; Clk        ; 4.614 ; 4.633 ; Fall       ; Clk             ;
;  Rdat[6]  ; Clk        ; 6.336 ; 5.844 ; Fall       ; Clk             ;
;  Rdat[7]  ; Clk        ; 4.635 ; 4.589 ; Fall       ; Clk             ;
;  Rdat[8]  ; Clk        ; 4.638 ; 4.593 ; Fall       ; Clk             ;
;  Rdat[9]  ; Clk        ; 4.288 ; 4.278 ; Fall       ; Clk             ;
;  Rdat[10] ; Clk        ; 4.692 ; 4.639 ; Fall       ; Clk             ;
;  Rdat[11] ; Clk        ; 4.762 ; 4.721 ; Fall       ; Clk             ;
;  Rdat[12] ; Clk        ; 4.578 ; 4.578 ; Fall       ; Clk             ;
;  Rdat[13] ; Clk        ; 4.770 ; 4.735 ; Fall       ; Clk             ;
;  Rdat[14] ; Clk        ; 6.353 ; 5.874 ; Fall       ; Clk             ;
;  Rdat[15] ; Clk        ; 4.355 ; 4.339 ; Fall       ; Clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Rdat[*]   ; Clk        ; 3.924 ; 3.980 ; Rise       ; Clk             ;
;  Rdat[0]  ; Clk        ; 4.657 ; 4.883 ; Rise       ; Clk             ;
;  Rdat[1]  ; Clk        ; 4.603 ; 4.818 ; Rise       ; Clk             ;
;  Rdat[2]  ; Clk        ; 4.418 ; 4.353 ; Rise       ; Clk             ;
;  Rdat[3]  ; Clk        ; 4.254 ; 4.132 ; Rise       ; Clk             ;
;  Rdat[4]  ; Clk        ; 4.138 ; 4.007 ; Rise       ; Clk             ;
;  Rdat[5]  ; Clk        ; 4.309 ; 4.217 ; Rise       ; Clk             ;
;  Rdat[6]  ; Clk        ; 6.022 ; 5.384 ; Rise       ; Clk             ;
;  Rdat[7]  ; Clk        ; 4.147 ; 4.045 ; Rise       ; Clk             ;
;  Rdat[8]  ; Clk        ; 4.150 ; 4.049 ; Rise       ; Clk             ;
;  Rdat[9]  ; Clk        ; 3.924 ; 4.005 ; Rise       ; Clk             ;
;  Rdat[10] ; Clk        ; 4.185 ; 4.069 ; Rise       ; Clk             ;
;  Rdat[11] ; Clk        ; 4.252 ; 4.147 ; Rise       ; Clk             ;
;  Rdat[12] ; Clk        ; 4.184 ; 4.050 ; Rise       ; Clk             ;
;  Rdat[13] ; Clk        ; 4.350 ; 4.222 ; Rise       ; Clk             ;
;  Rdat[14] ; Clk        ; 5.926 ; 5.289 ; Rise       ; Clk             ;
;  Rdat[15] ; Clk        ; 4.119 ; 3.980 ; Rise       ; Clk             ;
; Rdat[*]   ; Clk        ; 4.136 ; 4.132 ; Fall       ; Clk             ;
;  Rdat[0]  ; Clk        ; 5.026 ; 5.105 ; Fall       ; Clk             ;
;  Rdat[1]  ; Clk        ; 4.791 ; 4.887 ; Fall       ; Clk             ;
;  Rdat[2]  ; Clk        ; 4.737 ; 4.817 ; Fall       ; Clk             ;
;  Rdat[3]  ; Clk        ; 4.384 ; 4.386 ; Fall       ; Clk             ;
;  Rdat[4]  ; Clk        ; 4.276 ; 4.262 ; Fall       ; Clk             ;
;  Rdat[5]  ; Clk        ; 4.431 ; 4.455 ; Fall       ; Clk             ;
;  Rdat[6]  ; Clk        ; 6.151 ; 5.637 ; Fall       ; Clk             ;
;  Rdat[7]  ; Clk        ; 4.391 ; 4.436 ; Fall       ; Clk             ;
;  Rdat[8]  ; Clk        ; 4.394 ; 4.440 ; Fall       ; Clk             ;
;  Rdat[9]  ; Clk        ; 4.136 ; 4.132 ; Fall       ; Clk             ;
;  Rdat[10] ; Clk        ; 4.444 ; 4.483 ; Fall       ; Clk             ;
;  Rdat[11] ; Clk        ; 4.512 ; 4.561 ; Fall       ; Clk             ;
;  Rdat[12] ; Clk        ; 4.399 ; 4.366 ; Fall       ; Clk             ;
;  Rdat[13] ; Clk        ; 4.542 ; 4.556 ; Fall       ; Clk             ;
;  Rdat[14] ; Clk        ; 6.185 ; 5.642 ; Fall       ; Clk             ;
;  Rdat[15] ; Clk        ; 4.177 ; 4.168 ; Fall       ; Clk             ;
+-----------+------------+-------+-------+------------+-----------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                   ;
+----------------------------------------+----------+--------+----------+---------+---------------------+
; Clock                                  ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
+----------------------------------------+----------+--------+----------+---------+---------------------+
; Worst-case Slack                       ; -7.821   ; -0.051 ; -2.117   ; 0.239   ; -3.000              ;
;  ApdDel[0]                             ; N/A      ; N/A    ; -0.294   ; 0.239   ; -3.000              ;
;  Clk                                   ; -7.821   ; -0.051 ; N/A      ; N/A     ; -3.000              ;
;  CoincidenceAsyncInput:inst1|CDC_CAPT3 ; N/A      ; N/A    ; -2.117   ; 1.337   ; 0.404               ;
; Design-wide TNS                        ; -326.565 ; -0.051 ; -19.96   ; 0.0     ; -271.474            ;
;  ApdDel[0]                             ; N/A      ; N/A    ; -0.294   ; 0.000   ; -4.918              ;
;  Clk                                   ; -326.565 ; -0.051 ; N/A      ; N/A     ; -267.189            ;
;  CoincidenceAsyncInput:inst1|CDC_CAPT3 ; N/A      ; N/A    ; -19.960  ; 0.000   ; 0.000               ;
+----------------------------------------+----------+--------+----------+---------+---------------------+


+-------------------------------------------------------------------------+
; Setup Times                                                             ;
+-------------+------------+-------+-------+------------+-----------------+
; Data Port   ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-------------+------------+-------+-------+------------+-----------------+
; Rcmd[*]     ; Clk        ; 2.197 ; 2.627 ; Rise       ; Clk             ;
;  Rcmd[0]    ; Clk        ; 1.992 ; 2.415 ; Rise       ; Clk             ;
;  Rcmd[1]    ; Clk        ; 2.029 ; 2.444 ; Rise       ; Clk             ;
;  Rcmd[2]    ; Clk        ; 2.197 ; 2.627 ; Rise       ; Clk             ;
; Rcs         ; Clk        ; 1.992 ; 2.384 ; Rise       ; Clk             ;
; Apd[*]      ; Clk        ; 2.669 ; 3.195 ; Fall       ; Clk             ;
;  Apd[0]     ; Clk        ; 2.664 ; 3.195 ; Fall       ; Clk             ;
;  Apd[1]     ; Clk        ; 2.604 ; 3.053 ; Fall       ; Clk             ;
;  Apd[2]     ; Clk        ; 1.922 ; 2.412 ; Fall       ; Clk             ;
;  Apd[3]     ; Clk        ; 2.669 ; 3.132 ; Fall       ; Clk             ;
;  Apd[4]     ; Clk        ; 2.662 ; 3.122 ; Fall       ; Clk             ;
;  Apd[5]     ; Clk        ; 2.451 ; 2.876 ; Fall       ; Clk             ;
;  Apd[6]     ; Clk        ; 2.058 ; 2.486 ; Fall       ; Clk             ;
;  Apd[7]     ; Clk        ; 2.656 ; 3.097 ; Fall       ; Clk             ;
;  Apd[8]     ; Clk        ; 2.379 ; 2.833 ; Fall       ; Clk             ;
;  Apd[9]     ; Clk        ; 2.334 ; 2.798 ; Fall       ; Clk             ;
;  Apd[10]    ; Clk        ; 1.886 ; 2.306 ; Fall       ; Clk             ;
; ApdDel[*]   ; Clk        ; 6.232 ; 6.562 ; Fall       ; Clk             ;
;  ApdDel[0]  ; Clk        ; 0.512 ; 0.542 ; Fall       ; Clk             ;
;  ApdDel[1]  ; Clk        ; 3.816 ; 4.165 ; Fall       ; Clk             ;
;  ApdDel[2]  ; Clk        ; 3.160 ; 3.504 ; Fall       ; Clk             ;
;  ApdDel[3]  ; Clk        ; 6.232 ; 6.562 ; Fall       ; Clk             ;
;  ApdDel[4]  ; Clk        ; 5.820 ; 6.167 ; Fall       ; Clk             ;
;  ApdDel[5]  ; Clk        ; 6.027 ; 6.364 ; Fall       ; Clk             ;
;  ApdDel[6]  ; Clk        ; 6.073 ; 6.366 ; Fall       ; Clk             ;
;  ApdDel[7]  ; Clk        ; 4.574 ; 4.987 ; Fall       ; Clk             ;
;  ApdDel[8]  ; Clk        ; 4.583 ; 4.991 ; Fall       ; Clk             ;
;  ApdDel[9]  ; Clk        ; 4.564 ; 4.910 ; Fall       ; Clk             ;
;  ApdDel[10] ; Clk        ; 4.430 ; 4.776 ; Fall       ; Clk             ;
+-------------+------------+-------+-------+------------+-----------------+


+---------------------------------------------------------------------------+
; Hold Times                                                                ;
+-------------+------------+--------+--------+------------+-----------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-------------+------------+--------+--------+------------+-----------------+
; Rcmd[*]     ; Clk        ; -0.829 ; -1.568 ; Rise       ; Clk             ;
;  Rcmd[0]    ; Clk        ; -0.829 ; -1.568 ; Rise       ; Clk             ;
;  Rcmd[1]    ; Clk        ; -0.839 ; -1.584 ; Rise       ; Clk             ;
;  Rcmd[2]    ; Clk        ; -0.921 ; -1.663 ; Rise       ; Clk             ;
; Rcs         ; Clk        ; -0.804 ; -1.547 ; Rise       ; Clk             ;
; Apd[*]      ; Clk        ; -0.237 ; -0.994 ; Fall       ; Clk             ;
;  Apd[0]     ; Clk        ; -0.628 ; -1.483 ; Fall       ; Clk             ;
;  Apd[1]     ; Clk        ; -0.603 ; -1.442 ; Fall       ; Clk             ;
;  Apd[2]     ; Clk        ; -0.312 ; -1.108 ; Fall       ; Clk             ;
;  Apd[3]     ; Clk        ; -0.607 ; -1.428 ; Fall       ; Clk             ;
;  Apd[4]     ; Clk        ; -0.612 ; -1.418 ; Fall       ; Clk             ;
;  Apd[5]     ; Clk        ; -0.499 ; -1.297 ; Fall       ; Clk             ;
;  Apd[6]     ; Clk        ; -0.326 ; -1.121 ; Fall       ; Clk             ;
;  Apd[7]     ; Clk        ; -0.607 ; -1.416 ; Fall       ; Clk             ;
;  Apd[8]     ; Clk        ; -0.484 ; -1.278 ; Fall       ; Clk             ;
;  Apd[9]     ; Clk        ; -0.467 ; -1.252 ; Fall       ; Clk             ;
;  Apd[10]    ; Clk        ; -0.237 ; -0.994 ; Fall       ; Clk             ;
; ApdDel[*]   ; Clk        ; 0.521  ; -0.099 ; Fall       ; Clk             ;
;  ApdDel[0]  ; Clk        ; 0.521  ; -0.099 ; Fall       ; Clk             ;
;  ApdDel[1]  ; Clk        ; -1.116 ; -1.917 ; Fall       ; Clk             ;
;  ApdDel[2]  ; Clk        ; -0.837 ; -1.613 ; Fall       ; Clk             ;
;  ApdDel[3]  ; Clk        ; -2.236 ; -3.188 ; Fall       ; Clk             ;
;  ApdDel[4]  ; Clk        ; -2.026 ; -2.955 ; Fall       ; Clk             ;
;  ApdDel[5]  ; Clk        ; -2.122 ; -3.062 ; Fall       ; Clk             ;
;  ApdDel[6]  ; Clk        ; -2.146 ; -3.105 ; Fall       ; Clk             ;
;  ApdDel[7]  ; Clk        ; -1.490 ; -2.374 ; Fall       ; Clk             ;
;  ApdDel[8]  ; Clk        ; -1.502 ; -2.383 ; Fall       ; Clk             ;
;  ApdDel[9]  ; Clk        ; -1.476 ; -2.358 ; Fall       ; Clk             ;
;  ApdDel[10] ; Clk        ; -1.404 ; -2.240 ; Fall       ; Clk             ;
+-------------+------------+--------+--------+------------+-----------------+


+-------------------------------------------------------------------------+
; Clock to Output Times                                                   ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; Rdat[*]   ; Clk        ; 12.959 ; 12.253 ; Rise       ; Clk             ;
;  Rdat[0]  ; Clk        ; 11.601 ; 11.315 ; Rise       ; Clk             ;
;  Rdat[1]  ; Clk        ; 11.438 ; 11.133 ; Rise       ; Clk             ;
;  Rdat[2]  ; Clk        ; 11.641 ; 11.363 ; Rise       ; Clk             ;
;  Rdat[3]  ; Clk        ; 11.090 ; 10.762 ; Rise       ; Clk             ;
;  Rdat[4]  ; Clk        ; 11.188 ; 10.847 ; Rise       ; Clk             ;
;  Rdat[5]  ; Clk        ; 11.124 ; 10.806 ; Rise       ; Clk             ;
;  Rdat[6]  ; Clk        ; 12.959 ; 12.253 ; Rise       ; Clk             ;
;  Rdat[7]  ; Clk        ; 10.258 ; 9.950  ; Rise       ; Clk             ;
;  Rdat[8]  ; Clk        ; 11.188 ; 10.857 ; Rise       ; Clk             ;
;  Rdat[9]  ; Clk        ; 10.550 ; 10.255 ; Rise       ; Clk             ;
;  Rdat[10] ; Clk        ; 10.651 ; 10.361 ; Rise       ; Clk             ;
;  Rdat[11] ; Clk        ; 10.802 ; 10.485 ; Rise       ; Clk             ;
;  Rdat[12] ; Clk        ; 10.088 ; 9.769  ; Rise       ; Clk             ;
;  Rdat[13] ; Clk        ; 10.423 ; 10.068 ; Rise       ; Clk             ;
;  Rdat[14] ; Clk        ; 12.859 ; 12.221 ; Rise       ; Clk             ;
;  Rdat[15] ; Clk        ; 10.391 ; 10.099 ; Rise       ; Clk             ;
; Rdat[*]   ; Clk        ; 10.150 ; 9.555  ; Fall       ; Clk             ;
;  Rdat[0]  ; Clk        ; 9.173  ; 8.926  ; Fall       ; Clk             ;
;  Rdat[1]  ; Clk        ; 8.677  ; 8.378  ; Fall       ; Clk             ;
;  Rdat[2]  ; Clk        ; 8.669  ; 8.377  ; Fall       ; Clk             ;
;  Rdat[3]  ; Clk        ; 7.933  ; 7.652  ; Fall       ; Clk             ;
;  Rdat[4]  ; Clk        ; 7.663  ; 7.385  ; Fall       ; Clk             ;
;  Rdat[5]  ; Clk        ; 7.960  ; 7.627  ; Fall       ; Clk             ;
;  Rdat[6]  ; Clk        ; 10.142 ; 9.474  ; Fall       ; Clk             ;
;  Rdat[7]  ; Clk        ; 7.962  ; 7.620  ; Fall       ; Clk             ;
;  Rdat[8]  ; Clk        ; 7.972  ; 7.628  ; Fall       ; Clk             ;
;  Rdat[9]  ; Clk        ; 7.325  ; 7.020  ; Fall       ; Clk             ;
;  Rdat[10] ; Clk        ; 8.046  ; 7.751  ; Fall       ; Clk             ;
;  Rdat[11] ; Clk        ; 8.228  ; 7.892  ; Fall       ; Clk             ;
;  Rdat[12] ; Clk        ; 7.901  ; 7.587  ; Fall       ; Clk             ;
;  Rdat[13] ; Clk        ; 8.291  ; 7.920  ; Fall       ; Clk             ;
;  Rdat[14] ; Clk        ; 10.150 ; 9.555  ; Fall       ; Clk             ;
;  Rdat[15] ; Clk        ; 7.456  ; 7.129  ; Fall       ; Clk             ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Rdat[*]   ; Clk        ; 3.924 ; 3.980 ; Rise       ; Clk             ;
;  Rdat[0]  ; Clk        ; 4.657 ; 4.883 ; Rise       ; Clk             ;
;  Rdat[1]  ; Clk        ; 4.603 ; 4.818 ; Rise       ; Clk             ;
;  Rdat[2]  ; Clk        ; 4.418 ; 4.353 ; Rise       ; Clk             ;
;  Rdat[3]  ; Clk        ; 4.254 ; 4.132 ; Rise       ; Clk             ;
;  Rdat[4]  ; Clk        ; 4.138 ; 4.007 ; Rise       ; Clk             ;
;  Rdat[5]  ; Clk        ; 4.309 ; 4.217 ; Rise       ; Clk             ;
;  Rdat[6]  ; Clk        ; 6.022 ; 5.384 ; Rise       ; Clk             ;
;  Rdat[7]  ; Clk        ; 4.147 ; 4.045 ; Rise       ; Clk             ;
;  Rdat[8]  ; Clk        ; 4.150 ; 4.049 ; Rise       ; Clk             ;
;  Rdat[9]  ; Clk        ; 3.924 ; 4.005 ; Rise       ; Clk             ;
;  Rdat[10] ; Clk        ; 4.185 ; 4.069 ; Rise       ; Clk             ;
;  Rdat[11] ; Clk        ; 4.252 ; 4.147 ; Rise       ; Clk             ;
;  Rdat[12] ; Clk        ; 4.184 ; 4.050 ; Rise       ; Clk             ;
;  Rdat[13] ; Clk        ; 4.350 ; 4.222 ; Rise       ; Clk             ;
;  Rdat[14] ; Clk        ; 5.926 ; 5.289 ; Rise       ; Clk             ;
;  Rdat[15] ; Clk        ; 4.119 ; 3.980 ; Rise       ; Clk             ;
; Rdat[*]   ; Clk        ; 4.136 ; 4.132 ; Fall       ; Clk             ;
;  Rdat[0]  ; Clk        ; 5.026 ; 5.105 ; Fall       ; Clk             ;
;  Rdat[1]  ; Clk        ; 4.791 ; 4.887 ; Fall       ; Clk             ;
;  Rdat[2]  ; Clk        ; 4.737 ; 4.817 ; Fall       ; Clk             ;
;  Rdat[3]  ; Clk        ; 4.384 ; 4.386 ; Fall       ; Clk             ;
;  Rdat[4]  ; Clk        ; 4.276 ; 4.262 ; Fall       ; Clk             ;
;  Rdat[5]  ; Clk        ; 4.431 ; 4.455 ; Fall       ; Clk             ;
;  Rdat[6]  ; Clk        ; 6.151 ; 5.637 ; Fall       ; Clk             ;
;  Rdat[7]  ; Clk        ; 4.391 ; 4.436 ; Fall       ; Clk             ;
;  Rdat[8]  ; Clk        ; 4.394 ; 4.440 ; Fall       ; Clk             ;
;  Rdat[9]  ; Clk        ; 4.136 ; 4.132 ; Fall       ; Clk             ;
;  Rdat[10] ; Clk        ; 4.444 ; 4.483 ; Fall       ; Clk             ;
;  Rdat[11] ; Clk        ; 4.512 ; 4.561 ; Fall       ; Clk             ;
;  Rdat[12] ; Clk        ; 4.399 ; 4.366 ; Fall       ; Clk             ;
;  Rdat[13] ; Clk        ; 4.542 ; 4.556 ; Fall       ; Clk             ;
;  Rdat[14] ; Clk        ; 6.185 ; 5.642 ; Fall       ; Clk             ;
;  Rdat[15] ; Clk        ; 4.177 ; 4.168 ; Fall       ; Clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+---------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C  ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+---------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Rdat[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rdat[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+---------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; Clk                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Rcmd[2]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Rcmd[1]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Rcs                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Rcmd[0]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[9]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[8]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[10]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[10]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[9]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[8]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[7]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[6]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[5]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[4]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[3]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Rdat[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.91e-07 V                   ; 3.09 V              ; -0.00202 V          ; 0.166 V                              ; 0.034 V                              ; 1.37e-09 s                  ; 9.74e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.91e-07 V                  ; 3.09 V             ; -0.00202 V         ; 0.166 V                             ; 0.034 V                             ; 1.37e-09 s                 ; 9.74e-10 s                 ; No                        ; Yes                       ;
; Rdat[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.91e-07 V                   ; 3.1 V               ; -0.0218 V           ; 0.283 V                              ; 0.313 V                              ; 6.36e-09 s                  ; 4.71e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 9.91e-07 V                  ; 3.1 V              ; -0.0218 V          ; 0.283 V                             ; 0.313 V                             ; 6.36e-09 s                 ; 4.71e-09 s                 ; No                        ; No                        ;
; Rdat[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.91e-07 V                   ; 3.1 V               ; -0.0119 V           ; 0.26 V                               ; 0.085 V                              ; 1.58e-09 s                  ; 1.42e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 9.91e-07 V                  ; 3.1 V              ; -0.0119 V          ; 0.26 V                              ; 0.085 V                             ; 1.58e-09 s                 ; 1.42e-09 s                 ; No                        ; No                        ;
; Rdat[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.1 V               ; -0.0212 V           ; 0.285 V                              ; 0.317 V                              ; 6.37e-09 s                  ; 4.73e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 1.48e-06 V                  ; 3.1 V              ; -0.0212 V          ; 0.285 V                             ; 0.317 V                             ; 6.37e-09 s                 ; 4.73e-09 s                 ; No                        ; No                        ;
; Rdat[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; Rdat[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-06 V                   ; 3.09 V              ; -0.00171 V          ; 0.172 V                              ; 0.036 V                              ; 1.39e-09 s                  ; 1.01e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-06 V                  ; 3.09 V             ; -0.00171 V         ; 0.172 V                             ; 0.036 V                             ; 1.39e-09 s                 ; 1.01e-09 s                 ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.08e-07 V                   ; 3.15 V              ; -0.0428 V           ; 0.277 V                              ; 0.019 V                              ; 3.54e-10 s                  ; 4.84e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.08e-07 V                  ; 3.15 V             ; -0.0428 V          ; 0.277 V                             ; 0.019 V                             ; 3.54e-10 s                 ; 4.84e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.91e-07 V                   ; 3.1 V               ; -0.0119 V           ; 0.26 V                               ; 0.085 V                              ; 1.58e-09 s                  ; 1.42e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 9.91e-07 V                  ; 3.1 V              ; -0.0119 V          ; 0.26 V                              ; 0.085 V                             ; 1.58e-09 s                 ; 1.42e-09 s                 ; No                        ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Rdat[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.47 V              ; -0.0475 V           ; 0.207 V                              ; 0.053 V                              ; 8.3e-10 s                   ; 7.51e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.24e-07 V                  ; 3.47 V             ; -0.0475 V          ; 0.207 V                             ; 0.053 V                             ; 8.3e-10 s                  ; 7.51e-10 s                 ; No                        ; Yes                       ;
; Rdat[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.51 V              ; -0.051 V            ; 0.293 V                              ; 0.232 V                              ; 4.57e-09 s                  ; 3.62e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.51 V             ; -0.051 V           ; 0.293 V                             ; 0.232 V                             ; 4.57e-09 s                 ; 3.62e-09 s                 ; No                        ; No                        ;
; Rdat[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.5 V               ; -0.0496 V           ; 0.345 V                              ; 0.134 V                              ; 9.52e-10 s                  ; 8.7e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.24e-07 V                  ; 3.5 V              ; -0.0496 V          ; 0.345 V                             ; 0.134 V                             ; 9.52e-10 s                 ; 8.7e-10 s                  ; No                        ; Yes                       ;
; Rdat[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.5 V               ; -0.0505 V           ; 0.295 V                              ; 0.232 V                              ; 4.57e-09 s                  ; 3.63e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.5 V              ; -0.0505 V          ; 0.295 V                             ; 0.232 V                             ; 4.57e-09 s                 ; 3.63e-09 s                 ; No                        ; No                        ;
; Rdat[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; Rdat[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.47 V              ; -0.0417 V           ; 0.217 V                              ; 0.055 V                              ; 8.41e-10 s                  ; 7.6e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.83e-07 V                  ; 3.47 V             ; -0.0417 V          ; 0.217 V                             ; 0.055 V                             ; 8.41e-10 s                 ; 7.6e-10 s                  ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.53e-08 V                   ; 4.06 V              ; -0.514 V            ; 0.288 V                              ; 0.256 V                              ; 2.5e-10 s                   ; 2.81e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.53e-08 V                  ; 4.06 V             ; -0.514 V           ; 0.288 V                             ; 0.256 V                             ; 2.5e-10 s                  ; 2.81e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.5 V               ; -0.0496 V           ; 0.345 V                              ; 0.134 V                              ; 9.52e-10 s                  ; 8.7e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.24e-07 V                  ; 3.5 V              ; -0.0496 V          ; 0.345 V                             ; 0.134 V                             ; 9.52e-10 s                 ; 8.7e-10 s                  ; No                        ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+----------------------------------------------------------------------------------------------+
; Setup Transfers                                                                              ;
+---------------------------------------+----------+----------+----------+----------+----------+
; From Clock                            ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------------------------+----------+----------+----------+----------+----------+
; ApdDel[0]                             ; Clk      ; 0        ; 0        ; 1        ; 1        ;
; Clk                                   ; Clk      ; 788      ; 224      ; 294      ; 2126     ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk      ; 0        ; 0        ; 11       ; 0        ;
+---------------------------------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+----------------------------------------------------------------------------------------------+
; Hold Transfers                                                                               ;
+---------------------------------------+----------+----------+----------+----------+----------+
; From Clock                            ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------------------------+----------+----------+----------+----------+----------+
; ApdDel[0]                             ; Clk      ; 0        ; 0        ; 1        ; 1        ;
; Clk                                   ; Clk      ; 788      ; 224      ; 294      ; 2126     ;
; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; Clk      ; 0        ; 0        ; 11       ; 0        ;
+---------------------------------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                             ;
+------------+---------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+---------------------------------------+----------+----------+----------+----------+
; Clk        ; ApdDel[0]                             ; 0        ; 1        ; 0        ; 0        ;
; Clk        ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0        ; 11       ; 0        ; 0        ;
+------------+---------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                              ;
+------------+---------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+---------------------------------------+----------+----------+----------+----------+
; Clk        ; ApdDel[0]                             ; 0        ; 1        ; 0        ; 0        ;
; Clk        ; CoincidenceAsyncInput:inst1|CDC_CAPT3 ; 0        ; 11       ; 0        ; 0        ;
+------------+---------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 25    ; 25   ;
; Unconstrained Input Port Paths  ; 36    ; 36   ;
; Unconstrained Output Ports      ; 16    ; 16   ;
; Unconstrained Output Port Paths ; 96    ; 96   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Info: Processing started: Tue Nov 04 14:03:10 2014
Info: Command: quartus_sta CoincidenceCounter -c CoincidenceCounter
Info (P0): qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Core supply voltage is 1.2V
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Warning (335093): TimeQuest Timing Analyzer is analyzing 22 combinational loops as latches.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'CoincidenceCounter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name Clk Clk
    Info (332105): create_clock -period 1.000 -name ApdDel[0] ApdDel[0]
    Info (332105): create_clock -period 1.000 -name CoincidenceAsyncInput:inst1|CDC_CAPT3 CoincidenceAsyncInput:inst1|CDC_CAPT3
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (P0): Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (P0): Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -7.821
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -7.821            -326.565 Clk 
Info (332146): Worst-case hold slack is 0.152
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.152               0.000 Clk 
Info (332146): Worst-case recovery slack is -2.117
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.117             -19.960 CoincidenceAsyncInput:inst1|CDC_CAPT3 
    Info (332119):     0.099               0.000 ApdDel[0] 
Info (332146): Worst-case removal slack is 0.311
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.311               0.000 ApdDel[0] 
    Info (332119):     1.430               0.000 CoincidenceAsyncInput:inst1|CDC_CAPT3 
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000            -267.189 Clk 
    Info (332119):    -3.000              -4.285 ApdDel[0] 
    Info (332119):     0.404               0.000 CoincidenceAsyncInput:inst1|CDC_CAPT3 
Info (P0): Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -7.008
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -7.008            -290.522 Clk 
Info (332146): Worst-case hold slack is 0.128
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.128               0.000 Clk 
Info (332146): Worst-case recovery slack is -1.985
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.985             -18.493 CoincidenceAsyncInput:inst1|CDC_CAPT3 
    Info (332119):     0.242               0.000 ApdDel[0] 
Info (332146): Worst-case removal slack is 0.239
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.239               0.000 ApdDel[0] 
    Info (332119):     1.421               0.000 CoincidenceAsyncInput:inst1|CDC_CAPT3 
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000            -265.077 Clk 
    Info (332119):    -3.000              -4.285 ApdDel[0] 
    Info (332119):     0.440               0.000 CoincidenceAsyncInput:inst1|CDC_CAPT3 
Info (P0): Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.164
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.164            -119.891 Clk 
Info (332146): Worst-case hold slack is -0.051
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.051              -0.051 Clk 
Info (332146): Worst-case recovery slack is -1.201
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.201             -11.486 CoincidenceAsyncInput:inst1|CDC_CAPT3 
    Info (332119):    -0.294              -0.294 ApdDel[0] 
Info (332146): Worst-case removal slack is 0.924
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.924               0.000 ApdDel[0] 
    Info (332119):     1.337               0.000 CoincidenceAsyncInput:inst1|CDC_CAPT3 
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000            -206.969 Clk 
    Info (332119):    -3.000              -4.918 ApdDel[0] 
    Info (332119):     0.410               0.000 CoincidenceAsyncInput:inst1|CDC_CAPT3 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 496 megabytes
    Info: Processing ended: Tue Nov 04 14:03:14 2014
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:03


