Classic Timing Analyzer report for CoincidenceCounter
Wed Aug 18 13:13:25 2010
Quartus II Version 9.1 Build 222 10/21/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'Clk'
  7. Clock Hold: 'Clk'
  8. tsu
  9. tco
 10. th
 11. Board Trace Model Assignments
 12. Input Transition Times
 13. Slow Corner Signal Integrity Metrics
 14. Fast Corner Signal Integrity Metrics
 15. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                         ;
+------------------------------+----------+-----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack    ; Required Time                     ; Actual Time                      ; From                                                                                                               ; To                                                                                                                 ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+----------+-----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A      ; None                              ; 4.066 ns                         ; Apd[6]                                                                                                             ; CoincidenceAsyncInput:inst1|CDC_OFF                                                                                ; --         ; Clk      ; 0            ;
; Worst-case tco               ; N/A      ; None                              ; 13.783 ns                        ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_we_reg ; Rdat[6]                                                                                                            ; Clk        ; --       ; 0            ;
; Worst-case th                ; N/A      ; None                              ; -1.301 ns                        ; ApdDel[7]                                                                                                          ; CoincidenceAsyncInput:inst1|CDC_OFF9                                                                               ; --         ; Clk      ; 0            ;
; Clock Setup: 'Clk'           ; 0.781 ns ; 100.00 MHz ( period = 10.000 ns ) ; 108.47 MHz ( period = 9.219 ns ) ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg ; Clk        ; Clk      ; 0            ;
; Clock Hold: 'Clk'            ; 0.579 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; CoinCounter:inst2|CoinState.0001                                                                                   ; CoinCounter:inst2|CoinState.0001                                                                                   ; Clk        ; Clk      ; 0            ;
; Total number of failed paths ;          ;                                   ;                                  ;                                                                                                                    ;                                                                                                                    ;            ;          ; 0            ;
+------------------------------+----------+-----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+-----+-------------+
; Option                                                                                               ; Setting            ; From ; To  ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+-----+-------------+
; Device Name                                                                                          ; EP3C10E144C7       ;      ;     ;             ;
; Timing Models                                                                                        ; Final              ;      ;     ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;     ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;     ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;     ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;     ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;     ;             ;
; fmax Requirement                                                                                     ; 100 MHz            ;      ;     ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;     ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;     ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;     ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;     ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;     ;             ;
; Nominal Core Supply Voltage                                                                          ; 1.2V               ;      ;     ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;     ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;     ;             ;
; Number of paths to report                                                                            ; 200                ;      ;     ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;     ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;     ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;     ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;     ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;     ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;     ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;     ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; On                 ;      ;     ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;     ;             ;
; Clock Settings                                                                                       ; MasterClk          ;      ; Clk ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+-----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clk             ; MasterClk          ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[7]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[9]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[8]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[10]      ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[5]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[4]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[6]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[3]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[2]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[1]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ApdDel[0]       ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clk'                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                ; To                                                                                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 0.781 ns                                ; 108.47 MHz ( period = 9.219 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.790 ns                  ; 9.009 ns                ;
; 0.827 ns                                ; 109.02 MHz ( period = 9.173 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.796 ns                  ; 8.969 ns                ;
; 0.853 ns                                ; 109.33 MHz ( period = 9.147 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 8.941 ns                ;
; 0.859 ns                                ; 109.40 MHz ( period = 9.141 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.936 ns                ;
; 0.862 ns                                ; 109.43 MHz ( period = 9.138 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.789 ns                  ; 8.927 ns                ;
; 0.922 ns                                ; 110.16 MHz ( period = 9.078 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.790 ns                  ; 8.868 ns                ;
; 0.931 ns                                ; 110.27 MHz ( period = 9.069 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.796 ns                  ; 8.865 ns                ;
; 0.992 ns                                ; 111.01 MHz ( period = 9.008 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.791 ns                  ; 8.799 ns                ;
; 1.027 ns                                ; 111.45 MHz ( period = 8.973 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.789 ns                  ; 8.762 ns                ;
; 1.038 ns                                ; 111.58 MHz ( period = 8.962 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.797 ns                  ; 8.759 ns                ;
; 1.064 ns                                ; 111.91 MHz ( period = 8.936 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.731 ns                ;
; 1.070 ns                                ; 111.98 MHz ( period = 8.930 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.796 ns                  ; 8.726 ns                ;
; 1.073 ns                                ; 112.02 MHz ( period = 8.927 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.722 ns                ;
; 1.073 ns                                ; 112.02 MHz ( period = 8.927 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.790 ns                  ; 8.717 ns                ;
; 1.091 ns                                ; 112.25 MHz ( period = 8.909 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.704 ns                ;
; 1.099 ns                                ; 112.35 MHz ( period = 8.901 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.793 ns                  ; 8.694 ns                ;
; 1.105 ns                                ; 112.42 MHz ( period = 8.895 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 8.689 ns                ;
; 1.108 ns                                ; 112.46 MHz ( period = 8.892 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.788 ns                  ; 8.680 ns                ;
; 1.133 ns                                ; 112.78 MHz ( period = 8.867 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.791 ns                  ; 8.658 ns                ;
; 1.137 ns                                ; 112.83 MHz ( period = 8.863 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.801 ns                  ; 8.664 ns                ;
; 1.142 ns                                ; 112.89 MHz ( period = 8.858 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.797 ns                  ; 8.655 ns                ;
; 1.163 ns                                ; 113.16 MHz ( period = 8.837 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.799 ns                  ; 8.636 ns                ;
; 1.168 ns                                ; 113.22 MHz ( period = 8.832 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.789 ns                  ; 8.621 ns                ;
; 1.169 ns                                ; 113.24 MHz ( period = 8.831 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.800 ns                  ; 8.631 ns                ;
; 1.172 ns                                ; 113.28 MHz ( period = 8.828 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 8.622 ns                ;
; 1.177 ns                                ; 113.34 MHz ( period = 8.823 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.618 ns                ;
; 1.211 ns                                ; 113.78 MHz ( period = 8.789 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.789 ns                  ; 8.578 ns                ;
; 1.232 ns                                ; 114.05 MHz ( period = 8.768 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.563 ns                ;
; 1.241 ns                                ; 114.17 MHz ( period = 8.759 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.801 ns                  ; 8.560 ns                ;
; 1.257 ns                                ; 114.38 MHz ( period = 8.743 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.538 ns                ;
; 1.268 ns                                ; 114.52 MHz ( period = 8.732 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.796 ns                  ; 8.528 ns                ;
; 1.283 ns                                ; 114.72 MHz ( period = 8.717 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.793 ns                  ; 8.510 ns                ;
; 1.289 ns                                ; 114.80 MHz ( period = 8.711 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 8.505 ns                ;
; 1.292 ns                                ; 114.84 MHz ( period = 8.708 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.788 ns                  ; 8.496 ns                ;
; 1.352 ns                                ; 115.63 MHz ( period = 8.648 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.789 ns                  ; 8.437 ns                ;
; 1.360 ns                                ; 115.74 MHz ( period = 8.640 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.796 ns                  ; 8.436 ns                ;
; 1.361 ns                                ; 115.75 MHz ( period = 8.639 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.434 ns                ;
; 1.406 ns                                ; 116.36 MHz ( period = 8.594 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.802 ns                  ; 8.396 ns                ;
; 1.432 ns                                ; 116.71 MHz ( period = 8.568 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.800 ns                  ; 8.368 ns                ;
; 1.438 ns                                ; 116.80 MHz ( period = 8.562 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.801 ns                  ; 8.363 ns                ;
; 1.441 ns                                ; 116.84 MHz ( period = 8.559 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.354 ns                ;
; 1.468 ns                                ; 117.21 MHz ( period = 8.532 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.789 ns                  ; 8.321 ns                ;
; 1.479 ns                                ; 117.36 MHz ( period = 8.521 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.797 ns                  ; 8.318 ns                ;
; 1.501 ns                                ; 117.66 MHz ( period = 8.499 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.796 ns                  ; 8.295 ns                ;
; 1.510 ns                                ; 117.79 MHz ( period = 8.490 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.802 ns                  ; 8.292 ns                ;
; 1.514 ns                                ; 117.84 MHz ( period = 8.486 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.281 ns                ;
; 1.514 ns                                ; 117.84 MHz ( period = 8.486 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.281 ns                ;
; 1.540 ns                                ; 118.20 MHz ( period = 8.460 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.793 ns                  ; 8.253 ns                ;
; 1.546 ns                                ; 118.29 MHz ( period = 8.454 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 8.248 ns                ;
; 1.549 ns                                ; 118.33 MHz ( period = 8.451 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.788 ns                  ; 8.239 ns                ;
; 1.568 ns                                ; 118.60 MHz ( period = 8.432 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.227 ns                ;
; 1.578 ns                                ; 118.74 MHz ( period = 8.422 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.801 ns                  ; 8.223 ns                ;
; 1.609 ns                                ; 119.18 MHz ( period = 8.391 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.789 ns                  ; 8.180 ns                ;
; 1.614 ns                                ; 119.25 MHz ( period = 8.386 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.801 ns                  ; 8.187 ns                ;
; 1.618 ns                                ; 119.30 MHz ( period = 8.382 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.177 ns                ;
; 1.640 ns                                ; 119.62 MHz ( period = 8.360 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.799 ns                  ; 8.159 ns                ;
; 1.646 ns                                ; 119.70 MHz ( period = 8.354 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.800 ns                  ; 8.154 ns                ;
; 1.649 ns                                ; 119.75 MHz ( period = 8.351 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 8.145 ns                ;
; 1.698 ns                                ; 120.45 MHz ( period = 8.302 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.097 ns                ;
; 1.709 ns                                ; 120.61 MHz ( period = 8.291 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 8.086 ns                ;
; 1.718 ns                                ; 120.74 MHz ( period = 8.282 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg      ; Clk        ; Clk      ; 10.000 ns                   ; 9.801 ns                  ; 8.083 ns                ;
; 1.739 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[17]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 3.047 ns                ;
; 1.739 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[1]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 3.047 ns                ;
; 1.739 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[19]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 3.047 ns                ;
; 1.739 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[18]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 3.047 ns                ;
; 1.739 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[7]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 3.047 ns                ;
; 1.739 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[13]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 3.047 ns                ;
; 1.739 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[12]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 3.047 ns                ;
; 1.739 ns                                ; 153.33 MHz ( period = 6.522 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[15]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 3.047 ns                ;
; 1.798 ns                                ; 156.15 MHz ( period = 6.404 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[0]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.987 ns                ;
; 1.798 ns                                ; 156.15 MHz ( period = 6.404 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[6]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.987 ns                ;
; 1.798 ns                                ; 156.15 MHz ( period = 6.404 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[24]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.987 ns                ;
; 1.798 ns                                ; 156.15 MHz ( period = 6.404 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[9]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.987 ns                ;
; 1.800 ns                                ; 156.25 MHz ( period = 6.400 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[2]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.984 ns                ;
; 1.800 ns                                ; 156.25 MHz ( period = 6.400 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[5]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.984 ns                ;
; 1.800 ns                                ; 156.25 MHz ( period = 6.400 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[4]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.984 ns                ;
; 1.800 ns                                ; 156.25 MHz ( period = 6.400 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[11]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.984 ns                ;
; 1.800 ns                                ; 156.25 MHz ( period = 6.400 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[10]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.984 ns                ;
; 1.822 ns                                ; 122.28 MHz ( period = 8.178 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 7.972 ns                ;
; 1.847 ns                                ; 122.65 MHz ( period = 8.153 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.802 ns                  ; 7.955 ns                ;
; 1.947 ns                                ; 124.18 MHz ( period = 8.053 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.800 ns                  ; 7.853 ns                ;
; 1.955 ns                                ; 124.30 MHz ( period = 8.045 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 7.840 ns                ;
; 1.956 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[17]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.829 ns                ;
; 1.956 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[1]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.829 ns                ;
; 1.956 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[19]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.829 ns                ;
; 1.956 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[18]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.829 ns                ;
; 1.956 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[7]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.829 ns                ;
; 1.956 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[13]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.829 ns                ;
; 1.956 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[12]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.829 ns                ;
; 1.956 ns                                ; 164.26 MHz ( period = 6.088 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[15]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.829 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[10]                                                                                            ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[9]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[8]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[7]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[6]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[5]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[4]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[3]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[2]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[1]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 1.985 ns                                ; 165.84 MHz ( period = 6.030 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemAdd[0]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.799 ns                ;
; 2.015 ns                                ; 167.50 MHz ( period = 5.970 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[0]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.769 ns                ;
; 2.015 ns                                ; 167.50 MHz ( period = 5.970 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[6]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.769 ns                ;
; 2.015 ns                                ; 167.50 MHz ( period = 5.970 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[24]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.769 ns                ;
; 2.015 ns                                ; 167.50 MHz ( period = 5.970 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[9]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.769 ns                ;
; 2.017 ns                                ; 167.62 MHz ( period = 5.966 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[2]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.766 ns                ;
; 2.017 ns                                ; 167.62 MHz ( period = 5.966 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[5]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.766 ns                ;
; 2.017 ns                                ; 167.62 MHz ( period = 5.966 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[4]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.766 ns                ;
; 2.017 ns                                ; 167.62 MHz ( period = 5.966 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[11]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.766 ns                ;
; 2.017 ns                                ; 167.62 MHz ( period = 5.966 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[10]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.766 ns                ;
; 2.029 ns                                ; 168.29 MHz ( period = 5.942 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[3]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.756 ns                ;
; 2.033 ns                                ; 125.52 MHz ( period = 7.967 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.795 ns                  ; 7.762 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[21]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[20]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[23]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[22]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[25]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[27]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[26]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[29]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[28]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[31]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.039 ns                                ; 168.86 MHz ( period = 5.922 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[30]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.786 ns                  ; 2.747 ns                ;
; 2.055 ns                                ; 125.87 MHz ( period = 7.945 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_we_reg ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg       ; Clk        ; Clk      ; 10.000 ns                   ; 9.801 ns                  ; 7.746 ns                ;
; 2.068 ns                                ; 126.07 MHz ( period = 7.932 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.793 ns                  ; 7.725 ns                ;
; 2.073 ns                                ; 170.82 MHz ( period = 5.854 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[16]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.712 ns                ;
; 2.073 ns                                ; 170.82 MHz ( period = 5.854 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[8]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.712 ns                ;
; 2.073 ns                                ; 170.82 MHz ( period = 5.854 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemWr[14]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.712 ns                ;
; 2.108 ns                                ; 126.71 MHz ( period = 7.892 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.793 ns                  ; 7.685 ns                ;
; 2.124 ns                                ; 173.85 MHz ( period = 5.752 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[17]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.661 ns                ;
; 2.124 ns                                ; 173.85 MHz ( period = 5.752 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[1]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.661 ns                ;
; 2.124 ns                                ; 173.85 MHz ( period = 5.752 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[19]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.661 ns                ;
; 2.124 ns                                ; 173.85 MHz ( period = 5.752 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[18]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.661 ns                ;
; 2.124 ns                                ; 173.85 MHz ( period = 5.752 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[7]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.661 ns                ;
; 2.124 ns                                ; 173.85 MHz ( period = 5.752 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[13]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.661 ns                ;
; 2.124 ns                                ; 173.85 MHz ( period = 5.752 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[12]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.661 ns                ;
; 2.124 ns                                ; 173.85 MHz ( period = 5.752 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[15]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.661 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[10]                                                                                            ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[9]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[8]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[7]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[6]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[5]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[4]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[3]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[2]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[1]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.129 ns                                ; 174.16 MHz ( period = 5.742 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemAdd[0]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.655 ns                ;
; 2.132 ns                                ; 127.10 MHz ( period = 7.868 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.799 ns                  ; 7.667 ns                ;
; 2.158 ns                                ; 127.52 MHz ( period = 7.842 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.801 ns                  ; 7.643 ns                ;
; 2.183 ns                                ; 177.49 MHz ( period = 5.634 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[0]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.601 ns                ;
; 2.183 ns                                ; 177.49 MHz ( period = 5.634 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[6]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.601 ns                ;
; 2.183 ns                                ; 177.49 MHz ( period = 5.634 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[24]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.601 ns                ;
; 2.183 ns                                ; 177.49 MHz ( period = 5.634 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[9]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.601 ns                ;
; 2.185 ns                                ; 177.62 MHz ( period = 5.630 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[2]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.598 ns                ;
; 2.185 ns                                ; 177.62 MHz ( period = 5.630 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[5]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.598 ns                ;
; 2.185 ns                                ; 177.62 MHz ( period = 5.630 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[4]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.598 ns                ;
; 2.185 ns                                ; 177.62 MHz ( period = 5.630 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[11]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.598 ns                ;
; 2.185 ns                                ; 177.62 MHz ( period = 5.630 ns )                    ; inst7[0]                                                                                                            ; RabbitControl:inst|MemWr[10]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.783 ns                  ; 2.598 ns                ;
; 2.193 ns                                ; 128.09 MHz ( period = 7.807 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.799 ns                  ; 7.606 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[10]                                                                                            ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[9]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[8]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[7]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[6]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[5]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[4]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[3]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[2]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[1]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.236 ns                                ; 180.90 MHz ( period = 5.528 ns )                    ; inst7[2]                                                                                                            ; RabbitControl:inst|MemAdd[0]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.549 ns                ;
; 2.246 ns                                ; 181.55 MHz ( period = 5.508 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[3]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.538 ns                ;
; 2.252 ns                                ; 129.07 MHz ( period = 7.748 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.793 ns                  ; 7.541 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[21]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[20]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[23]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[22]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[25]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[27]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[26]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[29]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[28]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[31]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.256 ns                                ; 182.22 MHz ( period = 5.488 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[30]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.529 ns                ;
; 2.257 ns                                ; 129.15 MHz ( period = 7.743 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.805 ns                  ; 7.548 ns                ;
; 2.274 ns                                ; 183.42 MHz ( period = 5.452 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[17]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.511 ns                ;
; 2.274 ns                                ; 183.42 MHz ( period = 5.452 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[1]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.511 ns                ;
; 2.274 ns                                ; 183.42 MHz ( period = 5.452 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[19]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.511 ns                ;
; 2.274 ns                                ; 183.42 MHz ( period = 5.452 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[18]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.511 ns                ;
; 2.274 ns                                ; 183.42 MHz ( period = 5.452 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[7]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.511 ns                ;
; 2.274 ns                                ; 183.42 MHz ( period = 5.452 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[13]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.511 ns                ;
; 2.274 ns                                ; 183.42 MHz ( period = 5.452 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[12]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.511 ns                ;
; 2.274 ns                                ; 183.42 MHz ( period = 5.452 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[15]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.785 ns                  ; 2.511 ns                ;
; 2.290 ns                                ; 184.50 MHz ( period = 5.420 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[16]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.494 ns                ;
; 2.290 ns                                ; 184.50 MHz ( period = 5.420 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[8]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.494 ns                ;
; 2.290 ns                                ; 184.50 MHz ( period = 5.420 ns )                    ; inst9                                                                                                               ; RabbitControl:inst|MemWr[14]                                                                                             ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.494 ns                ;
; 2.319 ns                                ; 130.19 MHz ( period = 7.681 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~porta_datain_reg0 ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 7.475 ns                ;
; 2.329 ns                                ; 130.36 MHz ( period = 7.671 ns )                    ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_datain_reg0  ; Clk        ; Clk      ; 10.000 ns                   ; 9.794 ns                  ; 7.465 ns                ;
; 2.333 ns                                ; 187.48 MHz ( period = 5.334 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[0]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.451 ns                ;
; 2.333 ns                                ; 187.48 MHz ( period = 5.334 ns )                    ; inst7[1]                                                                                                            ; RabbitControl:inst|MemWr[6]                                                                                              ; Clk        ; Clk      ; 5.000 ns                    ; 4.784 ns                  ; 2.451 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                     ;                                                                                                                          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'Clk'                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                           ; From                                                ; To                                        ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; 0.579 ns                                ; CoinCounter:inst2|CoinState.0001                    ; CoinCounter:inst2|CoinState.0001          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.533 ns                 ;
; 0.579 ns                                ; CoinCounter:inst2|ApdsReset                         ; CoinCounter:inst2|ApdsReset               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.533 ns                 ;
; 0.579 ns                                ; RabbitControl:inst|HighWordOnBus                    ; RabbitControl:inst|HighWordOnBus          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.533 ns                 ;
; 0.579 ns                                ; RabbitControl:inst|TestDataState[1]                 ; RabbitControl:inst|TestDataState[1]       ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.533 ns                 ;
; 0.579 ns                                ; RabbitControl:inst|TestDataState[0]                 ; RabbitControl:inst|TestDataState[0]       ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.533 ns                 ;
; 0.579 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|LastCs                 ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.533 ns                 ;
; 0.579 ns                                ; CoinCounter:inst2|MemInc                            ; CoinCounter:inst2|MemInc                  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.533 ns                 ;
; 0.631 ns                                ; CoincidenceAsyncInput:inst1|CDC_OFF9                ; CoincidenceAsyncInput:inst1|CDC_OFF2      ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.585 ns                 ;
; 0.632 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]            ; CoinCounter:inst2|MemAdd[2]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.586 ns                 ;
; 0.633 ns                                ; CoinCounter:inst2|CoinState.0011                    ; CoinCounter:inst2|CoinState.0100          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.587 ns                 ;
; 0.634 ns                                ; CoinCounter:inst2|CoinState.0010                    ; CoinCounter:inst2|CoinState.0011          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.588 ns                 ;
; 0.644 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]            ; CoinCounter:inst2|MemAdd[8]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.598 ns                 ;
; 0.647 ns                                ; CoinCounter:inst2|CoinState.0100                    ; CoinCounter:inst2|CoinState.0000          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.601 ns                 ;
; 0.668 ns                                ; CoinCounter:inst2|CoinState.0000                    ; CoinCounter:inst2|MemInc                  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.622 ns                 ;
; 0.668 ns                                ; RabbitControl:inst|MemAdd[10]                       ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.622 ns                 ;
; 0.669 ns                                ; RabbitControl:inst|TestDataState[1]                 ; RabbitControl:inst|TestDataState[0]~0     ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.623 ns                 ;
; 0.775 ns                                ; CoincidenceAsyncInput:inst1|CDC_OFF                 ; CoincidenceAsyncInput:inst1|CDC_OFF1      ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 0.730 ns                 ;
; 0.777 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[8]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[8]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.731 ns                 ;
; 0.778 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[3]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.732 ns                 ;
; 0.780 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[10]            ; CoincidenceAsyncInput:inst1|CDC_CAPT1[10] ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.734 ns                 ;
; 0.781 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[4]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.735 ns                 ;
; 0.782 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[6]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.736 ns                 ;
; 0.783 ns                                ; CoinCounter:inst2|CoinState.0111                    ; CoinCounter:inst2|CoinState.0000          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.737 ns                 ;
; 0.785 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[9]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.739 ns                 ;
; 0.785 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]            ; CoinCounter:inst2|MemAdd[5]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 0.740 ns                 ;
; 0.786 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[0]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.740 ns                 ;
; 0.788 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[7]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.742 ns                 ;
; 0.790 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[4]            ; CoinCounter:inst2|MemAdd[4]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 0.745 ns                 ;
; 0.814 ns                                ; CoinCounter:inst2|CoinState.0001                    ; CoinCounter:inst2|CoinState.0010          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.768 ns                 ;
; 0.815 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[0]            ; CoinCounter:inst2|MemAdd[0]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 0.770 ns                 ;
; 0.817 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[6]            ; CoinCounter:inst2|MemAdd[6]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 0.772 ns                 ;
; 0.820 ns                                ; RabbitControl:inst|TestDataState[0]                 ; RabbitControl:inst|TestDataState[0]~0     ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.774 ns                 ;
; 0.844 ns                                ; CoinCounter:inst2|CoinState.0000                    ; CoinCounter:inst2|ApdsReset               ; Clk        ; Clk      ; 0.000 ns                   ; -0.047 ns                  ; 0.797 ns                 ;
; 0.934 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]            ; CoinCounter:inst2|MemAdd[1]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.888 ns                 ;
; 0.937 ns                                ; CoinCounter:inst2|CoinState.0110                    ; CoinCounter:inst2|CoinState.0111          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.891 ns                 ;
; 0.945 ns                                ; CoinCounter:inst2|CoinState.0100                    ; CoinCounter:inst2|CoinState.0101          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.899 ns                 ;
; 0.957 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|CoinState.0110          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.911 ns                 ;
; 0.957 ns                                ; RabbitControl:inst|TestDataState[0]                 ; RabbitControl:inst|TestDataState[1]       ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.911 ns                 ;
; 0.967 ns                                ; CoinCounter:inst2|CoinState.0111                    ; CoinCounter:inst2|MemInc                  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.921 ns                 ;
; 0.974 ns                                ; inst6[2]                                            ; inst7[2]                                  ; Clk        ; Clk      ; 0.000 ns                   ; -0.047 ns                  ; 0.927 ns                 ;
; 0.974 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[0]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.928 ns                 ;
; 0.978 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[2]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.932 ns                 ;
; 0.986 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[1]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.940 ns                 ;
; 0.991 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemAdd[4]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.945 ns                 ;
; 0.992 ns                                ; RabbitControl:inst|MemAdd[8]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.946 ns                 ;
; 0.992 ns                                ; RabbitControl:inst|MemAdd[5]                        ; RabbitControl:inst|MemAdd[5]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.946 ns                 ;
; 0.999 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemAdd[6]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.953 ns                 ;
; 1.002 ns                                ; RabbitControl:inst|MemAdd[7]                        ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.956 ns                 ;
; 1.004 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemAdd[3]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.958 ns                 ;
; 1.005 ns                                ; RabbitControl:inst|MemAdd[9]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 0.959 ns                 ;
; 1.034 ns                                ; CoincidenceAsyncInput:inst1|CDC_OFF1                ; CoinCounter:inst2|CoinState.0010          ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 0.989 ns                 ;
; 1.051 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[9]            ; CoinCounter:inst2|MemAdd[9]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.043 ns                  ; 1.008 ns                 ;
; 1.088 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[7]            ; CoinCounter:inst2|MemAdd[7]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.043 ns                  ; 1.045 ns                 ;
; 1.094 ns                                ; inst8                                               ; inst9                                     ; Clk        ; Clk      ; 0.000 ns                   ; -0.049 ns                  ; 1.045 ns                 ;
; 1.095 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[3]            ; CoinCounter:inst2|MemAdd[3]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.047 ns                  ; 1.048 ns                 ;
; 1.125 ns                                ; CoinCounter:inst2|CoinState.0001                    ; CoinCounter:inst2|ApdsReset               ; Clk        ; Clk      ; 0.000 ns                   ; -0.047 ns                  ; 1.078 ns                 ;
; 1.142 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[5]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[5]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.096 ns                 ;
; 1.145 ns                                ; CoinCounter:inst2|CoinState.0000                    ; CoinCounter:inst2|CoinState.0001          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.099 ns                 ;
; 1.190 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[1]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[1]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.144 ns                 ;
; 1.201 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT[2]             ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.155 ns                 ;
; 1.234 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemWr[0]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.188 ns                 ;
; 1.241 ns                                ; inst6[1]                                            ; inst7[1]                                  ; Clk        ; Clk      ; 0.000 ns                   ; -0.049 ns                  ; 1.192 ns                 ;
; 1.248 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemWr[24]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.202 ns                 ;
; 1.274 ns                                ; RabbitControl:inst|RunEn                            ; CoinCounter:inst2|CoinState.0010          ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.229 ns                 ;
; 1.276 ns                                ; RabbitControl:inst|RunEn                            ; CoinCounter:inst2|CoinState.0110          ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.231 ns                 ;
; 1.303 ns                                ; CoincidenceAsyncInput:inst1|CDC_OFF1                ; CoinCounter:inst2|CoinState.0001          ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.258 ns                 ;
; 1.339 ns                                ; CoincidenceAsyncInput:inst1|CDC_OFF2                ; CoinCounter:inst2|CoinState.0110          ; Clk        ; Clk      ; 0.000 ns                   ; -0.051 ns                  ; 1.288 ns                 ;
; 1.343 ns                                ; CoincidenceAsyncInput:inst1|CDC_OFF2                ; CoinCounter:inst2|CoinState.0101          ; Clk        ; Clk      ; 0.000 ns                   ; -0.051 ns                  ; 1.292 ns                 ;
; 1.381 ns                                ; CoinCounter:inst2|CoinState.0000                    ; CoinCounter:inst2|CoinState.0000          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.335 ns                 ;
; 1.427 ns                                ; inst6[0]                                            ; inst7[0]                                  ; Clk        ; Clk      ; 0.000 ns                   ; -0.049 ns                  ; 1.378 ns                 ;
; 1.440 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[10]           ; CoinCounter:inst2|MemAdd[10]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.395 ns                 ;
; 1.444 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemWr[14]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.398 ns                 ;
; 1.446 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemWr[16]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.400 ns                 ;
; 1.447 ns                                ; RabbitControl:inst|RunEn                            ; CoinCounter:inst2|CoinState.0001          ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.402 ns                 ;
; 1.458 ns                                ; RabbitControl:inst|TestDataState[1]                 ; RabbitControl:inst|MemWrEn                ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.413 ns                 ;
; 1.478 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[24]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.432 ns                 ;
; 1.498 ns                                ; RabbitControl:inst|MemWrEn                          ; RabbitControl:inst|MemWrEn                ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.452 ns                 ;
; 1.506 ns                                ; CoinCounter:inst2|CoinState.0001                    ; CoinCounter:inst2|CoinState.0000          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.460 ns                 ;
; 1.536 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemWr[24]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.490 ns                 ;
; 1.556 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]            ; CoinCounter:inst2|CoinState.0101          ; Clk        ; Clk      ; 0.000 ns                   ; -0.044 ns                  ; 1.512 ns                 ;
; 1.586 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|CoinState.0101          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.540 ns                 ;
; 1.594 ns                                ; CoincidenceAsyncInput:inst1|CDC_OFF2                ; CoinCounter:inst2|CoinState.0010          ; Clk        ; Clk      ; 0.000 ns                   ; -0.051 ns                  ; 1.543 ns                 ;
; 1.594 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[1]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.548 ns                 ;
; 1.597 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[2]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.551 ns                 ;
; 1.598 ns                                ; RabbitControl:inst|MemAdd[5]                        ; RabbitControl:inst|MemAdd[6]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.552 ns                 ;
; 1.598 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[3]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.552 ns                 ;
; 1.609 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[1]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.564 ns                 ;
; 1.609 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.563 ns                 ;
; 1.610 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemAdd[4]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.564 ns                 ;
; 1.611 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemAdd[5]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.565 ns                 ;
; 1.612 ns                                ; RabbitControl:inst|MemAdd[8]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.566 ns                 ;
; 1.613 ns                                ; RabbitControl:inst|MemAdd[7]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.567 ns                 ;
; 1.616 ns                                ; RabbitControl:inst|MemAdd[9]                        ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.570 ns                 ;
; 1.627 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|CoinState.0000          ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.581 ns                 ;
; 1.632 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemWr[21]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.587 ns                 ;
; 1.632 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemWr[22]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.587 ns                 ;
; 1.633 ns                                ; RabbitControl:inst|RunEn                            ; RabbitControl:inst|RunEn                  ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.587 ns                 ;
; 1.635 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemWr[26]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.590 ns                 ;
; 1.637 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemWr[25]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.592 ns                 ;
; 1.638 ns                                ; RabbitControl:inst|TestDataState[0]                 ; RabbitControl:inst|MemWrEn                ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.593 ns                 ;
; 1.660 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[2]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.614 ns                 ;
; 1.661 ns                                ; CoincidenceAsyncInput:inst1|CDC_CAPT1[2]            ; CoinCounter:inst2|CoinState.0000          ; Clk        ; Clk      ; 0.000 ns                   ; -0.044 ns                  ; 1.617 ns                 ;
; 1.663 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[3]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.617 ns                 ;
; 1.664 ns                                ; RabbitControl:inst|MemAdd[5]                        ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.618 ns                 ;
; 1.664 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[4]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.618 ns                 ;
; 1.675 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.629 ns                 ;
; 1.676 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemAdd[5]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.630 ns                 ;
; 1.677 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemAdd[6]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.631 ns                 ;
; 1.678 ns                                ; RabbitControl:inst|MemAdd[8]                        ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.632 ns                 ;
; 1.679 ns                                ; RabbitControl:inst|MemAdd[7]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.633 ns                 ;
; 1.721 ns                                ; CoincidenceAsyncInput:inst1|CDC_OFF2                ; CoinCounter:inst2|CoinState.0001          ; Clk        ; Clk      ; 0.000 ns                   ; -0.051 ns                  ; 1.670 ns                 ;
; 1.726 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[3]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.680 ns                 ;
; 1.729 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[4]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.683 ns                 ;
; 1.730 ns                                ; RabbitControl:inst|MemAdd[5]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.684 ns                 ;
; 1.730 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[5]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.684 ns                 ;
; 1.741 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.695 ns                 ;
; 1.742 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemAdd[6]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.696 ns                 ;
; 1.743 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.697 ns                 ;
; 1.745 ns                                ; RabbitControl:inst|MemAdd[7]                        ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.699 ns                 ;
; 1.749 ns                                ; RabbitControl:inst|MemAdd[8]                        ; RabbitControl:inst|MemWr[16]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.703 ns                 ;
; 1.754 ns                                ; RabbitControl:inst|MemAdd[8]                        ; RabbitControl:inst|MemWr[14]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.708 ns                 ;
; 1.781 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[30]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.736 ns                 ;
; 1.792 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[4]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.746 ns                 ;
; 1.795 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[5]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.749 ns                 ;
; 1.796 ns                                ; RabbitControl:inst|MemAdd[5]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.750 ns                 ;
; 1.796 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[6]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.750 ns                 ;
; 1.807 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[22]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.762 ns                 ;
; 1.807 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.761 ns                 ;
; 1.808 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.762 ns                 ;
; 1.809 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.763 ns                 ;
; 1.823 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemWr[6]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.777 ns                 ;
; 1.828 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[31]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.783 ns                 ;
; 1.856 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|HighWordOnBus          ; Clk        ; Clk      ; 0.000 ns                   ; -0.047 ns                  ; 1.809 ns                 ;
; 1.858 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[26]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.813 ns                 ;
; 1.858 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[5]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.812 ns                 ;
; 1.861 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[6]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.815 ns                 ;
; 1.862 ns                                ; RabbitControl:inst|MemAdd[5]                        ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.816 ns                 ;
; 1.862 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.816 ns                 ;
; 1.867 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|MemAdd[9]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.821 ns                 ;
; 1.867 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|MemAdd[7]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.821 ns                 ;
; 1.867 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|MemAdd[6]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.821 ns                 ;
; 1.867 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|MemAdd[4]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.821 ns                 ;
; 1.869 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemWr[13]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.824 ns                 ;
; 1.871 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemWr[31]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.826 ns                 ;
; 1.871 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemWr[30]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.826 ns                 ;
; 1.874 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.828 ns                 ;
; 1.875 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.829 ns                 ;
; 1.879 ns                                ; RabbitControl:inst|MemAdd[10]                       ; RabbitControl:inst|MemWr[16]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.833 ns                 ;
; 1.880 ns                                ; RabbitControl:inst|MemAdd[10]                       ; RabbitControl:inst|MemWr[14]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.834 ns                 ;
; 1.912 ns                                ; RabbitControl:inst|RunEn                            ; CoinCounter:inst2|CoinState.0101          ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.867 ns                 ;
; 1.914 ns                                ; RabbitControl:inst|MemAdd[7]                        ; RabbitControl:inst|MemWr[16]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.868 ns                 ;
; 1.917 ns                                ; RabbitControl:inst|MemAdd[7]                        ; RabbitControl:inst|MemWr[14]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.871 ns                 ;
; 1.921 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemWr[15]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.876 ns                 ;
; 1.922 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemWr[13]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.877 ns                 ;
; 1.924 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[6]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.878 ns                 ;
; 1.926 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[23]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.881 ns                 ;
; 1.927 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.881 ns                 ;
; 1.928 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.882 ns                 ;
; 1.932 ns                                ; RabbitControl:inst|MemAdd[8]                        ; RabbitControl:inst|MemWr[8]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.886 ns                 ;
; 1.940 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.894 ns                 ;
; 1.941 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.895 ns                 ;
; 1.950 ns                                ; RabbitControl:inst|MemAdd[6]                        ; RabbitControl:inst|MemWr[8]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.904 ns                 ;
; 1.957 ns                                ; RabbitControl:inst|MemAdd[7]                        ; RabbitControl:inst|MemWr[6]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.911 ns                 ;
; 1.965 ns                                ; RabbitControl:inst|MemAdd[9]                        ; RabbitControl:inst|MemWr[14]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.919 ns                 ;
; 1.971 ns                                ; RabbitControl:inst|MemAdd[9]                        ; RabbitControl:inst|MemWr[16]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.925 ns                 ;
; 1.975 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[20]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.930 ns                 ;
; 1.976 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[27]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.931 ns                 ;
; 1.979 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[29]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.934 ns                 ;
; 1.990 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.944 ns                 ;
; 1.993 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.947 ns                 ;
; 1.994 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[19]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.949 ns                 ;
; 1.994 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.948 ns                 ;
; 2.006 ns                                ; RabbitControl:inst|MemAdd[3]                        ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.960 ns                 ;
; 2.027 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|MemAdd[5]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.047 ns                  ; 1.980 ns                 ;
; 2.027 ns                                ; CoinCounter:inst2|CoinState.0101                    ; CoinCounter:inst2|MemAdd[0]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.047 ns                  ; 1.980 ns                 ;
; 2.038 ns                                ; RabbitControl:inst|MemAdd[8]                        ; RabbitControl:inst|MemWr[24]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 1.992 ns                 ;
; 2.041 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[25]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 1.996 ns                 ;
; 2.045 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[21]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 2.000 ns                 ;
; 2.050 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemWr[2]               ; Clk        ; Clk      ; 0.000 ns                   ; -0.047 ns                  ; 2.003 ns                 ;
; 2.056 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 2.010 ns                 ;
; 2.059 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 2.013 ns                 ;
; 2.060 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 2.014 ns                 ;
; 2.093 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemWr[17]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 2.048 ns                 ;
; 2.095 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[12]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 2.050 ns                 ;
; 2.095 ns                                ; RabbitControl:inst|MemAdd[1]                        ; RabbitControl:inst|MemWr[15]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 2.050 ns                 ;
; 2.098 ns                                ; RabbitControl:inst|MemAdd[5]                        ; RabbitControl:inst|MemWr[16]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 2.052 ns                 ;
; 2.101 ns                                ; RabbitControl:inst|MemAdd[5]                        ; RabbitControl:inst|MemWr[14]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 2.055 ns                 ;
; 2.104 ns                                ; RabbitControl:inst|MemAdd[2]                        ; RabbitControl:inst|MemWr[17]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 2.059 ns                 ;
; 2.115 ns                                ; RabbitControl:inst|MemAdd[4]                        ; RabbitControl:inst|MemWr[19]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.045 ns                  ; 2.070 ns                 ;
; 2.122 ns                                ; RabbitControl:inst|MemAdd[0]                        ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.046 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[10]             ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[9]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[8]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[7]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[6]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[5]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[4]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[3]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[2]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; 2.124 ns                                ; RabbitControl:inst|LastCs                           ; RabbitControl:inst|MemAdd[1]              ; Clk        ; Clk      ; 0.000 ns                   ; -0.048 ns                  ; 2.076 ns                 ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                           ;            ;          ;                            ;                            ;                          ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+--------------------------------------------------------------------------------------------------+
; tsu                                                                                              ;
+-------+--------------+------------+------------+--------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From       ; To                                   ; To Clock ;
+-------+--------------+------------+------------+--------------------------------------+----------+
; N/A   ; None         ; 4.066 ns   ; Apd[6]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.851 ns   ; Apd[1]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.840 ns   ; Apd[3]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.735 ns   ; Apd[0]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.712 ns   ; Apd[8]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.512 ns   ; Apd[10]    ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.418 ns   ; Apd[5]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.355 ns   ; Apd[9]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.330 ns   ; Apd[4]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.276 ns   ; ApdDel[0]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 3.219 ns   ; Apd[7]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 3.199 ns   ; ApdDel[3]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 3.121 ns   ; ApdDel[6]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 2.888 ns   ; ApdDel[1]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 2.729 ns   ; Apd[2]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A   ; None         ; 2.484 ns   ; ApdDel[4]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 2.374 ns   ; ApdDel[5]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 2.183 ns   ; Rcmd[2]    ; inst6[2]                             ; Clk      ;
; N/A   ; None         ; 2.122 ns   ; Rcmd[0]    ; inst6[0]                             ; Clk      ;
; N/A   ; None         ; 2.119 ns   ; Rcmd[1]    ; inst6[1]                             ; Clk      ;
; N/A   ; None         ; 2.071 ns   ; Rcs        ; inst8                                ; Clk      ;
; N/A   ; None         ; 2.065 ns   ; ApdDel[10] ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 2.003 ns   ; ApdDel[2]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 1.818 ns   ; ApdDel[8]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 1.700 ns   ; ApdDel[9]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A   ; None         ; 1.469 ns   ; ApdDel[7]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
+-------+--------------+------------+------------+--------------------------------------+----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                             ;
+-------+--------------+------------+---------------------------------------------------------------------------------------------------------------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                                                                ; To       ; From Clock ;
+-------+--------------+------------+---------------------------------------------------------------------------------------------------------------------+----------+------------+
; N/A   ; None         ; 13.783 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_we_reg  ; Rdat[6]  ; Clk        ;
; N/A   ; None         ; 13.429 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~portb_we_reg ; Rdat[14] ; Clk        ;
; N/A   ; None         ; 11.794 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~portb_we_reg ; Rdat[10] ; Clk        ;
; N/A   ; None         ; 11.716 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a14~portb_we_reg ; Rdat[15] ; Clk        ;
; N/A   ; None         ; 11.545 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~portb_we_reg  ; Rdat[1]  ; Clk        ;
; N/A   ; None         ; 11.530 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a10~portb_we_reg ; Rdat[11] ; Clk        ;
; N/A   ; None         ; 11.519 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~portb_we_reg  ; Rdat[3]  ; Clk        ;
; N/A   ; None         ; 11.513 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a0~portb_we_reg  ; Rdat[0]  ; Clk        ;
; N/A   ; None         ; 11.485 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~portb_we_reg  ; Rdat[2]  ; Clk        ;
; N/A   ; None         ; 11.265 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_we_reg  ; Rdat[7]  ; Clk        ;
; N/A   ; None         ; 11.148 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~portb_we_reg ; Rdat[12] ; Clk        ;
; N/A   ; None         ; 11.125 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a12~portb_we_reg ; Rdat[13] ; Clk        ;
; N/A   ; None         ; 11.099 ns  ; inst7[2]                                                                                                            ; Rdat[6]  ; Clk        ;
; N/A   ; None         ; 11.082 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~portb_we_reg  ; Rdat[8]  ; Clk        ;
; N/A   ; None         ; 10.985 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a8~portb_we_reg  ; Rdat[9]  ; Clk        ;
; N/A   ; None         ; 10.779 ns  ; inst7[2]                                                                                                            ; Rdat[14] ; Clk        ;
; N/A   ; None         ; 10.748 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_we_reg  ; Rdat[4]  ; Clk        ;
; N/A   ; None         ; 10.664 ns  ; lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a4~portb_we_reg  ; Rdat[5]  ; Clk        ;
; N/A   ; None         ; 10.639 ns  ; inst9                                                                                                               ; Rdat[6]  ; Clk        ;
; N/A   ; None         ; 10.623 ns  ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[6]  ; Clk        ;
; N/A   ; None         ; 10.540 ns  ; inst7[0]                                                                                                            ; Rdat[6]  ; Clk        ;
; N/A   ; None         ; 10.412 ns  ; inst7[1]                                                                                                            ; Rdat[6]  ; Clk        ;
; N/A   ; None         ; 10.319 ns  ; inst9                                                                                                               ; Rdat[14] ; Clk        ;
; N/A   ; None         ; 10.303 ns  ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[14] ; Clk        ;
; N/A   ; None         ; 10.220 ns  ; inst7[0]                                                                                                            ; Rdat[14] ; Clk        ;
; N/A   ; None         ; 10.092 ns  ; inst7[1]                                                                                                            ; Rdat[14] ; Clk        ;
; N/A   ; None         ; 9.982 ns   ; inst7[2]                                                                                                            ; Rdat[2]  ; Clk        ;
; N/A   ; None         ; 9.859 ns   ; inst7[2]                                                                                                            ; Rdat[3]  ; Clk        ;
; N/A   ; None         ; 9.541 ns   ; inst7[2]                                                                                                            ; Rdat[4]  ; Clk        ;
; N/A   ; None         ; 9.522 ns   ; inst9                                                                                                               ; Rdat[2]  ; Clk        ;
; N/A   ; None         ; 9.521 ns   ; inst7[2]                                                                                                            ; Rdat[13] ; Clk        ;
; N/A   ; None         ; 9.468 ns   ; inst7[2]                                                                                                            ; Rdat[5]  ; Clk        ;
; N/A   ; None         ; 9.423 ns   ; inst7[0]                                                                                                            ; Rdat[2]  ; Clk        ;
; N/A   ; None         ; 9.399 ns   ; inst9                                                                                                               ; Rdat[3]  ; Clk        ;
; N/A   ; None         ; 9.300 ns   ; inst7[0]                                                                                                            ; Rdat[3]  ; Clk        ;
; N/A   ; None         ; 9.295 ns   ; inst7[1]                                                                                                            ; Rdat[2]  ; Clk        ;
; N/A   ; None         ; 9.259 ns   ; inst7[2]                                                                                                            ; Rdat[12] ; Clk        ;
; N/A   ; None         ; 9.237 ns   ; inst7[2]                                                                                                            ; Rdat[7]  ; Clk        ;
; N/A   ; None         ; 9.225 ns   ; inst7[2]                                                                                                            ; Rdat[8]  ; Clk        ;
; N/A   ; None         ; 9.207 ns   ; inst7[2]                                                                                                            ; Rdat[9]  ; Clk        ;
; N/A   ; None         ; 9.203 ns   ; inst7[2]                                                                                                            ; Rdat[0]  ; Clk        ;
; N/A   ; None         ; 9.172 ns   ; inst7[1]                                                                                                            ; Rdat[3]  ; Clk        ;
; N/A   ; None         ; 9.089 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[2]  ; Clk        ;
; N/A   ; None         ; 9.081 ns   ; inst9                                                                                                               ; Rdat[4]  ; Clk        ;
; N/A   ; None         ; 9.061 ns   ; inst9                                                                                                               ; Rdat[13] ; Clk        ;
; N/A   ; None         ; 9.045 ns   ; inst7[2]                                                                                                            ; Rdat[10] ; Clk        ;
; N/A   ; None         ; 9.026 ns   ; inst7[2]                                                                                                            ; Rdat[1]  ; Clk        ;
; N/A   ; None         ; 9.008 ns   ; inst9                                                                                                               ; Rdat[5]  ; Clk        ;
; N/A   ; None         ; 9.000 ns   ; inst7[2]                                                                                                            ; Rdat[15] ; Clk        ;
; N/A   ; None         ; 8.982 ns   ; inst7[0]                                                                                                            ; Rdat[4]  ; Clk        ;
; N/A   ; None         ; 8.965 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[3]  ; Clk        ;
; N/A   ; None         ; 8.962 ns   ; inst7[0]                                                                                                            ; Rdat[13] ; Clk        ;
; N/A   ; None         ; 8.909 ns   ; inst7[0]                                                                                                            ; Rdat[5]  ; Clk        ;
; N/A   ; None         ; 8.854 ns   ; inst7[1]                                                                                                            ; Rdat[4]  ; Clk        ;
; N/A   ; None         ; 8.834 ns   ; inst7[1]                                                                                                            ; Rdat[13] ; Clk        ;
; N/A   ; None         ; 8.799 ns   ; inst9                                                                                                               ; Rdat[12] ; Clk        ;
; N/A   ; None         ; 8.781 ns   ; inst7[1]                                                                                                            ; Rdat[5]  ; Clk        ;
; N/A   ; None         ; 8.777 ns   ; inst9                                                                                                               ; Rdat[7]  ; Clk        ;
; N/A   ; None         ; 8.766 ns   ; inst7[2]                                                                                                            ; Rdat[11] ; Clk        ;
; N/A   ; None         ; 8.765 ns   ; inst9                                                                                                               ; Rdat[8]  ; Clk        ;
; N/A   ; None         ; 8.747 ns   ; inst9                                                                                                               ; Rdat[9]  ; Clk        ;
; N/A   ; None         ; 8.743 ns   ; inst9                                                                                                               ; Rdat[0]  ; Clk        ;
; N/A   ; None         ; 8.711 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[0]  ; Clk        ;
; N/A   ; None         ; 8.700 ns   ; inst7[0]                                                                                                            ; Rdat[12] ; Clk        ;
; N/A   ; None         ; 8.678 ns   ; inst7[0]                                                                                                            ; Rdat[7]  ; Clk        ;
; N/A   ; None         ; 8.666 ns   ; inst7[0]                                                                                                            ; Rdat[8]  ; Clk        ;
; N/A   ; None         ; 8.648 ns   ; inst7[0]                                                                                                            ; Rdat[9]  ; Clk        ;
; N/A   ; None         ; 8.644 ns   ; inst7[0]                                                                                                            ; Rdat[0]  ; Clk        ;
; N/A   ; None         ; 8.623 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[4]  ; Clk        ;
; N/A   ; None         ; 8.585 ns   ; inst9                                                                                                               ; Rdat[10] ; Clk        ;
; N/A   ; None         ; 8.573 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[5]  ; Clk        ;
; N/A   ; None         ; 8.572 ns   ; inst7[1]                                                                                                            ; Rdat[12] ; Clk        ;
; N/A   ; None         ; 8.566 ns   ; inst9                                                                                                               ; Rdat[1]  ; Clk        ;
; N/A   ; None         ; 8.551 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[12] ; Clk        ;
; N/A   ; None         ; 8.550 ns   ; inst7[1]                                                                                                            ; Rdat[7]  ; Clk        ;
; N/A   ; None         ; 8.540 ns   ; inst9                                                                                                               ; Rdat[15] ; Clk        ;
; N/A   ; None         ; 8.538 ns   ; inst7[1]                                                                                                            ; Rdat[8]  ; Clk        ;
; N/A   ; None         ; 8.520 ns   ; inst7[1]                                                                                                            ; Rdat[9]  ; Clk        ;
; N/A   ; None         ; 8.516 ns   ; inst7[1]                                                                                                            ; Rdat[0]  ; Clk        ;
; N/A   ; None         ; 8.486 ns   ; inst7[0]                                                                                                            ; Rdat[10] ; Clk        ;
; N/A   ; None         ; 8.467 ns   ; inst7[0]                                                                                                            ; Rdat[1]  ; Clk        ;
; N/A   ; None         ; 8.441 ns   ; inst7[0]                                                                                                            ; Rdat[15] ; Clk        ;
; N/A   ; None         ; 8.358 ns   ; inst7[1]                                                                                                            ; Rdat[10] ; Clk        ;
; N/A   ; None         ; 8.339 ns   ; inst7[1]                                                                                                            ; Rdat[1]  ; Clk        ;
; N/A   ; None         ; 8.313 ns   ; inst7[1]                                                                                                            ; Rdat[15] ; Clk        ;
; N/A   ; None         ; 8.308 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[8]  ; Clk        ;
; N/A   ; None         ; 8.308 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[13] ; Clk        ;
; N/A   ; None         ; 8.306 ns   ; inst9                                                                                                               ; Rdat[11] ; Clk        ;
; N/A   ; None         ; 8.299 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[9]  ; Clk        ;
; N/A   ; None         ; 8.253 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[10] ; Clk        ;
; N/A   ; None         ; 8.250 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[1]  ; Clk        ;
; N/A   ; None         ; 8.208 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[15] ; Clk        ;
; N/A   ; None         ; 8.207 ns   ; inst7[0]                                                                                                            ; Rdat[11] ; Clk        ;
; N/A   ; None         ; 8.079 ns   ; inst7[1]                                                                                                            ; Rdat[11] ; Clk        ;
; N/A   ; None         ; 8.024 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[7]  ; Clk        ;
; N/A   ; None         ; 7.975 ns   ; RabbitControl:inst|HighWordOnBus                                                                                    ; Rdat[11] ; Clk        ;
+-------+--------------+------------+---------------------------------------------------------------------------------------------------------------------+----------+------------+


+--------------------------------------------------------------------------------------------------------+
; th                                                                                                     ;
+---------------+-------------+-----------+------------+--------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                                   ; To Clock ;
+---------------+-------------+-----------+------------+--------------------------------------+----------+
; N/A           ; None        ; -1.301 ns ; ApdDel[7]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -1.532 ns ; ApdDel[9]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -1.650 ns ; ApdDel[8]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -1.835 ns ; ApdDel[2]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -1.897 ns ; ApdDel[10] ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -1.903 ns ; Rcs        ; inst8                                ; Clk      ;
; N/A           ; None        ; -1.951 ns ; Rcmd[1]    ; inst6[1]                             ; Clk      ;
; N/A           ; None        ; -1.954 ns ; Rcmd[0]    ; inst6[0]                             ; Clk      ;
; N/A           ; None        ; -2.015 ns ; Rcmd[2]    ; inst6[2]                             ; Clk      ;
; N/A           ; None        ; -2.206 ns ; ApdDel[5]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -2.316 ns ; ApdDel[4]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -2.561 ns ; Apd[2]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -2.720 ns ; ApdDel[1]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -2.953 ns ; ApdDel[6]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -3.031 ns ; ApdDel[3]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -3.051 ns ; Apd[7]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.108 ns ; ApdDel[0]  ; CoincidenceAsyncInput:inst1|CDC_OFF9 ; Clk      ;
; N/A           ; None        ; -3.162 ns ; Apd[4]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.187 ns ; Apd[9]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.250 ns ; Apd[5]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.344 ns ; Apd[10]    ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.544 ns ; Apd[8]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.567 ns ; Apd[0]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.672 ns ; Apd[3]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.683 ns ; Apd[1]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
; N/A           ; None        ; -3.898 ns ; Apd[6]     ; CoincidenceAsyncInput:inst1|CDC_OFF  ; Clk      ;
+---------------+-------------+-----------+------------+--------------------------------------+----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                     ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+---------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C  ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+---------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Rdat[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Rdat[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; 5e-12 F ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+---------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; Clk                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Rcs                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Rcmd[2]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Rcmd[1]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Rcmd[0]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[10]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[9]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[8]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ApdDel[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[10]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[9]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[8]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[7]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[6]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[5]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[4]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[3]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; Apd[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Rdat[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.91e-007 V                  ; 3.09 V              ; -0.00202 V          ; 0.166 V                              ; 0.034 V                              ; 1.37e-009 s                 ; 9.74e-010 s                 ; No                         ; Yes                        ; 3.08 V                      ; 9.91e-007 V                 ; 3.09 V             ; -0.00202 V         ; 0.166 V                             ; 0.034 V                             ; 1.37e-009 s                ; 9.74e-010 s                ; No                        ; Yes                       ;
; Rdat[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.91e-007 V                  ; 3.1 V               ; -0.0218 V           ; 0.283 V                              ; 0.313 V                              ; 6.36e-009 s                 ; 4.71e-009 s                 ; No                         ; No                         ; 3.08 V                      ; 9.91e-007 V                 ; 3.1 V              ; -0.0218 V          ; 0.283 V                             ; 0.313 V                             ; 6.36e-009 s                ; 4.71e-009 s                ; No                        ; No                        ;
; Rdat[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.91e-007 V                  ; 3.1 V               ; -0.0119 V           ; 0.26 V                               ; 0.085 V                              ; 1.58e-009 s                 ; 1.42e-009 s                 ; No                         ; No                         ; 3.08 V                      ; 9.91e-007 V                 ; 3.1 V              ; -0.0119 V          ; 0.26 V                              ; 0.085 V                             ; 1.58e-009 s                ; 1.42e-009 s                ; No                        ; No                        ;
; Rdat[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.1 V               ; -0.0212 V           ; 0.285 V                              ; 0.317 V                              ; 6.37e-009 s                 ; 4.73e-009 s                 ; No                         ; No                         ; 3.08 V                      ; 1.48e-006 V                 ; 3.1 V              ; -0.0212 V          ; 0.285 V                             ; 0.317 V                             ; 6.37e-009 s                ; 4.73e-009 s                ; No                        ; No                        ;
; Rdat[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; Rdat[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.48e-006 V                  ; 3.09 V              ; -0.0017 V           ; 0.172 V                              ; 0.036 V                              ; 1.39e-009 s                 ; 1.01e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 1.48e-006 V                 ; 3.09 V             ; -0.0017 V          ; 0.172 V                             ; 0.036 V                             ; 1.39e-009 s                ; 1.01e-009 s                ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.08e-007 V                  ; 3.15 V              ; -0.0428 V           ; 0.277 V                              ; 0.019 V                              ; 3.54e-010 s                 ; 4.84e-010 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 5.08e-007 V                 ; 3.15 V             ; -0.0428 V          ; 0.277 V                             ; 0.019 V                             ; 3.54e-010 s                ; 4.84e-010 s                ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.91e-007 V                  ; 3.1 V               ; -0.0119 V           ; 0.26 V                               ; 0.085 V                              ; 1.58e-009 s                 ; 1.42e-009 s                 ; No                         ; No                         ; 3.08 V                      ; 9.91e-007 V                 ; 3.1 V              ; -0.0119 V          ; 0.26 V                              ; 0.085 V                             ; 1.58e-009 s                ; 1.42e-009 s                ; No                        ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 222 10/21/2009 SJ Web Edition
    Info: Processing started: Wed Aug 18 13:13:24 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CoincidenceCounter -c CoincidenceCounter --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[1]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[1]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[2]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[5]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[7]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[2]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[3]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[4]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[5]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[6]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[7]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[8]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[9]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[10]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Capture[0]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[3]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[4]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[6]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[8]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[9]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[10]" is a latch
    Warning: Node "CoincidenceAsyncInput:inst1|Stretch[0]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "ApdDel[7]" is an undefined clock
    Info: Assuming node "ApdDel[9]" is an undefined clock
    Info: Assuming node "ApdDel[8]" is an undefined clock
    Info: Assuming node "ApdDel[10]" is an undefined clock
    Info: Assuming node "ApdDel[5]" is an undefined clock
    Info: Assuming node "ApdDel[4]" is an undefined clock
    Info: Assuming node "ApdDel[6]" is an undefined clock
    Info: Assuming node "ApdDel[3]" is an undefined clock
    Info: Assuming node "ApdDel[2]" is an undefined clock
    Info: Assuming node "ApdDel[1]" is an undefined clock
    Info: Assuming node "ApdDel[0]" is an undefined clock
Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~0" as buffer
    Info: Detected gated clock "CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~1" as buffer
    Info: Detected gated clock "CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~2" as buffer
    Info: Detected gated clock "CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]" as buffer
    Info: Detected ripple clock "CoincidenceAsyncInput:inst1|CDC_CAPT3" as buffer
Info: Slack time is 781 ps for clock "Clk" between source memory "lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg" and destination memory "lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg"
    Info: Fmax is 108.47 MHz (period= 9.219 ns)
    Info: + Largest memory to memory requirement is 9.790 ns
        Info: + Setup relationship between source and destination is 10.000 ns
            Info: + Latch edge is 10.000 ns
                Info: Clock period of Destination clock "Clk" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "Clk" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is -0.005 ns
            Info: + Shortest clock path from clock "Clk" to destination memory is 3.019 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_22; Fanout = 1; CLK Node = 'Clk'
                Info: 2: + IC(0.000 ns) + CELL(0.947 ns) = 0.947 ns; Loc. = IOIBUF_X0_Y11_N1; Fanout = 1; COMB Node = 'Clk~input'
                Info: 3: + IC(0.203 ns) + CELL(0.000 ns) = 1.150 ns; Loc. = CLKCTRL_G4; Fanout = 153; COMB Node = 'Clk~inputclkctrl'
                Info: 4: + IC(0.870 ns) + CELL(0.999 ns) = 3.019 ns; Loc. = M9K_X27_Y11_N0; Fanout = 4; MEM Node = 'lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg'
                Info: Total cell delay = 1.946 ns ( 64.46 % )
                Info: Total interconnect delay = 1.073 ns ( 35.54 % )
            Info: - Longest clock path from clock "Clk" to source memory is 3.024 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_22; Fanout = 1; CLK Node = 'Clk'
                Info: 2: + IC(0.000 ns) + CELL(0.947 ns) = 0.947 ns; Loc. = IOIBUF_X0_Y11_N1; Fanout = 1; COMB Node = 'Clk~input'
                Info: 3: + IC(0.203 ns) + CELL(0.000 ns) = 1.150 ns; Loc. = CLKCTRL_G4; Fanout = 153; COMB Node = 'Clk~inputclkctrl'
                Info: 4: + IC(0.875 ns) + CELL(0.999 ns) = 3.024 ns; Loc. = M9K_X27_Y15_N0; Fanout = 4; MEM Node = 'lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg'
                Info: Total cell delay = 1.946 ns ( 64.35 % )
                Info: Total interconnect delay = 1.078 ns ( 35.65 % )
        Info: - Micro clock to output delay of source is 0.263 ns
        Info: - Micro setup delay of destination is -0.058 ns
    Info: - Longest memory to memory delay is 9.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X27_Y15_N0; Fanout = 4; MEM Node = 'lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a2~porta_we_reg'
        Info: 2: + IC(0.000 ns) + CELL(2.849 ns) = 2.849 ns; Loc. = M9K_X27_Y15_N0; Fanout = 2; MEM Node = 'lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_a[2]'
        Info: 3: + IC(1.117 ns) + CELL(0.509 ns) = 4.475 ns; Loc. = LCCOMB_X28_Y13_N2; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~3'
        Info: 4: + IC(0.000 ns) + CELL(0.066 ns) = 4.541 ns; Loc. = LCCOMB_X28_Y13_N4; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~5'
        Info: 5: + IC(0.000 ns) + CELL(0.066 ns) = 4.607 ns; Loc. = LCCOMB_X28_Y13_N6; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~7'
        Info: 6: + IC(0.000 ns) + CELL(0.066 ns) = 4.673 ns; Loc. = LCCOMB_X28_Y13_N8; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~9'
        Info: 7: + IC(0.000 ns) + CELL(0.066 ns) = 4.739 ns; Loc. = LCCOMB_X28_Y13_N10; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~11'
        Info: 8: + IC(0.000 ns) + CELL(0.066 ns) = 4.805 ns; Loc. = LCCOMB_X28_Y13_N12; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~13'
        Info: 9: + IC(0.000 ns) + CELL(0.066 ns) = 4.871 ns; Loc. = LCCOMB_X28_Y13_N14; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~15'
        Info: 10: + IC(0.000 ns) + CELL(0.066 ns) = 4.937 ns; Loc. = LCCOMB_X28_Y13_N16; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~17'
        Info: 11: + IC(0.000 ns) + CELL(0.066 ns) = 5.003 ns; Loc. = LCCOMB_X28_Y13_N18; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~19'
        Info: 12: + IC(0.000 ns) + CELL(0.066 ns) = 5.069 ns; Loc. = LCCOMB_X28_Y13_N20; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~21'
        Info: 13: + IC(0.000 ns) + CELL(0.066 ns) = 5.135 ns; Loc. = LCCOMB_X28_Y13_N22; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~23'
        Info: 14: + IC(0.000 ns) + CELL(0.066 ns) = 5.201 ns; Loc. = LCCOMB_X28_Y13_N24; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~25'
        Info: 15: + IC(0.000 ns) + CELL(0.066 ns) = 5.267 ns; Loc. = LCCOMB_X28_Y13_N26; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~27'
        Info: 16: + IC(0.000 ns) + CELL(0.066 ns) = 5.333 ns; Loc. = LCCOMB_X28_Y13_N28; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~29'
        Info: 17: + IC(0.000 ns) + CELL(0.066 ns) = 5.399 ns; Loc. = LCCOMB_X28_Y13_N30; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~31'
        Info: 18: + IC(0.000 ns) + CELL(0.066 ns) = 5.465 ns; Loc. = LCCOMB_X28_Y12_N0; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~33'
        Info: 19: + IC(0.000 ns) + CELL(0.066 ns) = 5.531 ns; Loc. = LCCOMB_X28_Y12_N2; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~35'
        Info: 20: + IC(0.000 ns) + CELL(0.066 ns) = 5.597 ns; Loc. = LCCOMB_X28_Y12_N4; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~37'
        Info: 21: + IC(0.000 ns) + CELL(0.066 ns) = 5.663 ns; Loc. = LCCOMB_X28_Y12_N6; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~39'
        Info: 22: + IC(0.000 ns) + CELL(0.066 ns) = 5.729 ns; Loc. = LCCOMB_X28_Y12_N8; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~41'
        Info: 23: + IC(0.000 ns) + CELL(0.066 ns) = 5.795 ns; Loc. = LCCOMB_X28_Y12_N10; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~43'
        Info: 24: + IC(0.000 ns) + CELL(0.066 ns) = 5.861 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~45'
        Info: 25: + IC(0.000 ns) + CELL(0.066 ns) = 5.927 ns; Loc. = LCCOMB_X28_Y12_N14; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~47'
        Info: 26: + IC(0.000 ns) + CELL(0.066 ns) = 5.993 ns; Loc. = LCCOMB_X28_Y12_N16; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~49'
        Info: 27: + IC(0.000 ns) + CELL(0.066 ns) = 6.059 ns; Loc. = LCCOMB_X28_Y12_N18; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~51'
        Info: 28: + IC(0.000 ns) + CELL(0.066 ns) = 6.125 ns; Loc. = LCCOMB_X28_Y12_N20; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~53'
        Info: 29: + IC(0.000 ns) + CELL(0.066 ns) = 6.191 ns; Loc. = LCCOMB_X28_Y12_N22; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~55'
        Info: 30: + IC(0.000 ns) + CELL(0.066 ns) = 6.257 ns; Loc. = LCCOMB_X28_Y12_N24; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~57'
        Info: 31: + IC(0.000 ns) + CELL(0.066 ns) = 6.323 ns; Loc. = LCCOMB_X28_Y12_N26; Fanout = 2; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~59'
        Info: 32: + IC(0.000 ns) + CELL(0.066 ns) = 6.389 ns; Loc. = LCCOMB_X28_Y12_N28; Fanout = 1; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~61'
        Info: 33: + IC(0.000 ns) + CELL(0.536 ns) = 6.925 ns; Loc. = LCCOMB_X28_Y12_N30; Fanout = 8; COMB Node = 'lpm_add_sub0:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_api:auto_generated|op_1~62'
        Info: 34: + IC(0.749 ns) + CELL(0.285 ns) = 7.959 ns; Loc. = LCCOMB_X28_Y11_N28; Fanout = 1; COMB Node = 'inst10~_Duplicate_11'
        Info: 35: + IC(0.590 ns) + CELL(0.460 ns) = 9.009 ns; Loc. = M9K_X27_Y11_N0; Fanout = 4; MEM Node = 'lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~porta_we_reg'
        Info: Total cell delay = 6.553 ns ( 72.74 % )
        Info: Total interconnect delay = 2.456 ns ( 27.26 % )
Info: Minimum slack time is 579 ps for clock "Clk" between source register "CoinCounter:inst2|CoinState.0001" and destination register "CoinCounter:inst2|CoinState.0001"
    Info: + Shortest register to register delay is 0.533 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X26_Y12_N15; Fanout = 4; REG Node = 'CoinCounter:inst2|CoinState.0001'
        Info: 2: + IC(0.000 ns) + CELL(0.429 ns) = 0.429 ns; Loc. = LCCOMB_X26_Y12_N14; Fanout = 1; COMB Node = 'CoinCounter:inst2|Selector3~0'
        Info: 3: + IC(0.000 ns) + CELL(0.104 ns) = 0.533 ns; Loc. = FF_X26_Y12_N15; Fanout = 4; REG Node = 'CoinCounter:inst2|CoinState.0001'
        Info: Total cell delay = 0.533 ns ( 100.00 % )
    Info: - Smallest register to register requirement is -0.046 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 5.000 ns
                Info: Clock period of Destination clock "Clk" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 5.000 ns
                Info: Clock period of Source clock "Clk" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "Clk" to destination register is 2.637 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_22; Fanout = 1; CLK Node = 'Clk'
                Info: 2: + IC(0.000 ns) + CELL(0.947 ns) = 0.947 ns; Loc. = IOIBUF_X0_Y11_N1; Fanout = 1; COMB Node = 'Clk~input'
                Info: 3: + IC(0.203 ns) + CELL(0.000 ns) = 1.150 ns; Loc. = CLKCTRL_G4; Fanout = 153; COMB Node = 'Clk~inputclkctrl'
                Info: 4: + IC(0.874 ns) + CELL(0.613 ns) = 2.637 ns; Loc. = FF_X26_Y12_N15; Fanout = 4; REG Node = 'CoinCounter:inst2|CoinState.0001'
                Info: Total cell delay = 1.560 ns ( 59.16 % )
                Info: Total interconnect delay = 1.077 ns ( 40.84 % )
            Info: - Shortest clock path from clock "Clk" to source register is 2.637 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_22; Fanout = 1; CLK Node = 'Clk'
                Info: 2: + IC(0.000 ns) + CELL(0.947 ns) = 0.947 ns; Loc. = IOIBUF_X0_Y11_N1; Fanout = 1; COMB Node = 'Clk~input'
                Info: 3: + IC(0.203 ns) + CELL(0.000 ns) = 1.150 ns; Loc. = CLKCTRL_G4; Fanout = 153; COMB Node = 'Clk~inputclkctrl'
                Info: 4: + IC(0.874 ns) + CELL(0.613 ns) = 2.637 ns; Loc. = FF_X26_Y12_N15; Fanout = 4; REG Node = 'CoinCounter:inst2|CoinState.0001'
                Info: Total cell delay = 1.560 ns ( 59.16 % )
                Info: Total interconnect delay = 1.077 ns ( 40.84 % )
        Info: - Micro clock to output delay of source is 0.232 ns
        Info: + Micro hold delay of destination is 0.186 ns
Info: tsu for register "CoincidenceAsyncInput:inst1|CDC_OFF" (data pin = "Apd[6]", clock pin = "Clk") is 4.066 ns
    Info: + Longest pin to register delay is 6.719 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_66; Fanout = 1; PIN Node = 'Apd[6]'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X28_Y0_N1; Fanout = 2; COMB Node = 'Apd[6]~input'
        Info: 3: + IC(4.348 ns) + CELL(0.417 ns) = 5.729 ns; Loc. = LCCOMB_X25_Y12_N18; Fanout = 1; COMB Node = 'CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~1'
        Info: 4: + IC(0.454 ns) + CELL(0.432 ns) = 6.615 ns; Loc. = LCCOMB_X24_Y12_N30; Fanout = 1; COMB Node = 'CoincidenceAsyncInput:inst1|lpm_or0:inst3|lpm_or:lpm_or_component|or_node[0][10]~3'
        Info: 5: + IC(0.000 ns) + CELL(0.104 ns) = 6.719 ns; Loc. = FF_X24_Y12_N31; Fanout = 1; REG Node = 'CoincidenceAsyncInput:inst1|CDC_OFF'
        Info: Total cell delay = 1.917 ns ( 28.53 % )
        Info: Total interconnect delay = 4.802 ns ( 71.47 % )
    Info: + Micro setup delay of destination is -0.018 ns
    Info: - Shortest clock path from clock "Clk" to destination register is 2.635 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_22; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.000 ns) + CELL(0.947 ns) = 0.947 ns; Loc. = IOIBUF_X0_Y11_N1; Fanout = 1; COMB Node = 'Clk~input'
        Info: 3: + IC(0.203 ns) + CELL(0.000 ns) = 1.150 ns; Loc. = CLKCTRL_G4; Fanout = 153; COMB Node = 'Clk~inputclkctrl'
        Info: 4: + IC(0.872 ns) + CELL(0.613 ns) = 2.635 ns; Loc. = FF_X24_Y12_N31; Fanout = 1; REG Node = 'CoincidenceAsyncInput:inst1|CDC_OFF'
        Info: Total cell delay = 1.560 ns ( 59.20 % )
        Info: Total interconnect delay = 1.075 ns ( 40.80 % )
Info: tco from clock "Clk" to destination pin "Rdat[6]" through memory "lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_we_reg" is 13.783 ns
    Info: + Longest clock path from clock "Clk" to source memory is 3.021 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_22; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.000 ns) + CELL(0.947 ns) = 0.947 ns; Loc. = IOIBUF_X0_Y11_N1; Fanout = 1; COMB Node = 'Clk~input'
        Info: 3: + IC(0.203 ns) + CELL(0.000 ns) = 1.150 ns; Loc. = CLKCTRL_G4; Fanout = 153; COMB Node = 'Clk~inputclkctrl'
        Info: 4: + IC(0.870 ns) + CELL(1.001 ns) = 3.021 ns; Loc. = M9K_X27_Y11_N0; Fanout = 4; MEM Node = 'lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_we_reg'
        Info: Total cell delay = 1.948 ns ( 64.48 % )
        Info: Total interconnect delay = 1.073 ns ( 35.52 % )
    Info: + Micro clock to output delay of source is 0.263 ns
    Info: + Longest memory to pin delay is 10.499 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X27_Y11_N0; Fanout = 4; MEM Node = 'lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|ram_block1a6~portb_we_reg'
        Info: 2: + IC(0.000 ns) + CELL(2.890 ns) = 2.890 ns; Loc. = M9K_X27_Y11_N0; Fanout = 1; MEM Node = 'lpm_ram_dp0:Counter_Block|altsyncram:altsyncram_component|altsyncram_16f2:auto_generated|q_b[6]'
        Info: 3: + IC(1.100 ns) + CELL(0.287 ns) = 4.277 ns; Loc. = LCCOMB_X26_Y13_N20; Fanout = 1; COMB Node = 'RabbitControl:inst|Rdat[6]~9'
        Info: 4: + IC(1.519 ns) + CELL(4.703 ns) = 10.499 ns; Loc. = IOOBUF_X23_Y24_N2; Fanout = 1; COMB Node = 'Rdat[6]~output'
        Info: 5: + IC(0.000 ns) + CELL(0.000 ns) = 10.499 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'Rdat[6]'
        Info: Total cell delay = 7.880 ns ( 75.05 % )
        Info: Total interconnect delay = 2.619 ns ( 24.95 % )
Info: th for register "CoincidenceAsyncInput:inst1|CDC_OFF9" (data pin = "ApdDel[7]", clock pin = "Clk") is -1.301 ns
    Info: + Longest clock path from clock "Clk" to destination register is 2.642 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_22; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.000 ns) + CELL(0.947 ns) = 0.947 ns; Loc. = IOIBUF_X0_Y11_N1; Fanout = 1; COMB Node = 'Clk~input'
        Info: 3: + IC(0.203 ns) + CELL(0.000 ns) = 1.150 ns; Loc. = CLKCTRL_G4; Fanout = 153; COMB Node = 'Clk~inputclkctrl'
        Info: 4: + IC(0.879 ns) + CELL(0.613 ns) = 2.642 ns; Loc. = FF_X33_Y12_N1; Fanout = 1; REG Node = 'CoincidenceAsyncInput:inst1|CDC_OFF9'
        Info: Total cell delay = 1.560 ns ( 59.05 % )
        Info: Total interconnect delay = 1.082 ns ( 40.95 % )
    Info: + Micro hold delay of destination is 0.186 ns
    Info: - Shortest pin to register delay is 4.129 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_67; Fanout = 1; CLK Node = 'ApdDel[7]'
        Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOIBUF_X30_Y0_N22; Fanout = 1; COMB Node = 'ApdDel[7]~input'
        Info: 3: + IC(0.855 ns) + CELL(0.155 ns) = 1.974 ns; Loc. = LCCOMB_X31_Y2_N0; Fanout = 1; COMB Node = 'CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]~0'
        Info: 4: + IC(0.232 ns) + CELL(0.155 ns) = 2.361 ns; Loc. = LCCOMB_X31_Y2_N20; Fanout = 2; COMB Node = 'CoincidenceAsyncInput:inst1|lpm_or0:inst4|lpm_or:lpm_or_component|or_node[0][10]'
        Info: 5: + IC(1.379 ns) + CELL(0.285 ns) = 4.025 ns; Loc. = LCCOMB_X33_Y12_N0; Fanout = 1; COMB Node = 'CoincidenceAsyncInput:inst1|CDC_OFF9~0'
        Info: 6: + IC(0.000 ns) + CELL(0.104 ns) = 4.129 ns; Loc. = FF_X33_Y12_N1; Fanout = 1; REG Node = 'CoincidenceAsyncInput:inst1|CDC_OFF9'
        Info: Total cell delay = 1.663 ns ( 40.28 % )
        Info: Total interconnect delay = 2.466 ns ( 59.72 % )
Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 25 warnings
    Info: Peak virtual memory: 156 megabytes
    Info: Processing ended: Wed Aug 18 13:13:25 2010
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


