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Alan Stummer
Research Lab Technologist |
BEC AC Line Sync
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Downloads
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I am curious who uses what. Are these webpages a waste of time, or are they any help to others? Are the circuits, software and utilities appearing in other labs? Please send your comments or suggestions or what you have used (or not) or schematics of your version or pictures or anything! Email me, or be creative and send a postcard! I want to hear from the vacuum! |
Links
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NOTICE: This webpage and associated files is provided for reference only. This is not a kit site! It is a collection of my work here at the University of Toronto in the Physics department. If you are considering using any schematics, designs, or anything else from here then be warned that you had better know something of what you are about to do. No design is guaranteed in any way, including workable schematic, board layout, HDL code, embedded software, user software, component selection, documentation, webpages, or anything. All that said, if it says here it works then for me it worked. To make the project work may have involved undocumented additions, changes, deletions, tweaks, tunings, alterations, modifications, adjustments, waving of a wand while wearing a pointy black hat, appeals to electron deities and just plain doing whatever it takes to make the project work. |
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Overview
Started October 2009 for Chris Ellenor in Æphraim's lab. This project syncronizes the BEC experiment to the 60Hz AC line, to correct for ambient magnetic fields. Other labs have found a correlation between the phase of the AC line and the results from the BEC experiment. However, tests have shown that the AC line can drift more than one cycle in 15-20 seconds and is only stable within one cycle in >10 4 cycles, about three minutes. The optimal syncing event timing will have to be determined emperically.
How It Works
The primary input and output are a 250KHz clock. When the /Sync input is high, the 250KHz clock is piped straight through to the output. When /Sync is dropped low, the output is stopped until both the rising zero-crossing of the 60Hz AC line and a rising edge of a 10KHz clock from the TOP coil. After those two events (which happen within 0-16.6mS), the 250KHz clock output resumes.
Two 1980's state of the art CD4000 CMOS devices are used: a dual D-latch and a dual And-Or-Invert. A newer (circa 1990) dual comparator discriminates both the weak 250KHz clock and the AC line. The 9VAC is used for both the AC line reference and to power the unit.
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