Analysis & Synthesis report for GP_DDS
Tue May 06 17:27:44 2014
Quartus II 64-Bit Version 12.0 Build 178 05/31/2012 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |GP_DDS|uberDDS:oneandonly|State
 11. Registers Removed During Synthesis
 12. General Register Statistics
 13. Inverted Register Statistics
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated
 16. Parameter Settings for User Entity Instance: altpll1:inst2|altpll:altpll_component
 17. Parameter Settings for User Entity Instance: ram_dq:inst|altsyncram:altsyncram_component
 18. altpll Parameter Settings by Entity Instance
 19. altsyncram Parameter Settings by Entity Instance
 20. Elapsed Time Per Partition
 21. Analysis & Synthesis Messages
 22. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue May 06 17:27:44 2014     ;
; Quartus II 64-Bit Version          ; 12.0 Build 178 05/31/2012 SJ Full Version ;
; Revision Name                      ; GP_DDS                                    ;
; Top-level Entity Name              ; GP_DDS                                    ;
; Family                             ; Cyclone III                               ;
; Total logic elements               ; 227                                       ;
;     Total combinational functions  ; 210                                       ;
;     Dedicated logic registers      ; 86                                        ;
; Total registers                    ; 86                                        ;
; Total pins                         ; 41                                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 262,144                                   ;
; Embedded Multiplier 9-bit elements ; 0                                         ;
; Total PLLs                         ; 1                                         ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP3C10E144C7       ;                    ;
; Top-level entity name                                                      ; GP_DDS             ; GP_DDS             ;
; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
; Use smart compilation                                                      ; On                 ; Off                ;
; Preserve fewer node names                                                  ; Off                ; On                 ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                          ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                ; Library ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+
; GP_DDS.bdf                       ; yes             ; User Block Diagram/Schematic File  ; C:/Projects/Archives/2011 General Purpose DDS/Altera/GP_DDS.bdf             ;         ;
; DoubleBuffer8.v                  ; yes             ; User Verilog HDL File              ; C:/Projects/Archives/2011 General Purpose DDS/Altera/DoubleBuffer8.v        ;         ;
; ram_dq.v                         ; yes             ; User Wizard-Generated File         ; C:/Projects/Archives/2011 General Purpose DDS/Altera/ram_dq.v               ;         ;
; altpll1.v                        ; yes             ; User Wizard-Generated File         ; C:/Projects/Archives/2011 General Purpose DDS/Altera/altpll1.v              ;         ;
; uberDDS.v                        ; yes             ; User Verilog HDL File              ; C:/Projects/Archives/2011 General Purpose DDS/Altera/uberDDS.v              ;         ;
; altpll.tdf                       ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altpll.tdf                   ;         ;
; aglobal120.inc                   ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/aglobal120.inc               ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/stratix_pll.inc              ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/stratixii_pll.inc            ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/cycloneii_pll.inc            ;         ;
; db/altpll1_altpll.v              ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2011 General Purpose DDS/Altera/db/altpll1_altpll.v    ;         ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altsyncram.tdf               ;         ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/stratix_ram_block.inc        ;         ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/lpm_mux.inc                  ;         ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/lpm_decode.inc               ;         ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/a_rdenreg.inc                ;         ;
; altrom.inc                       ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altrom.inc                   ;         ;
; altram.inc                       ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altram.inc                   ;         ;
; altdpram.inc                     ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altdpram.inc                 ;         ;
; db/altsyncram_q5f1.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2011 General Purpose DDS/Altera/db/altsyncram_q5f1.tdf ;         ;
; db/decode_dra.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2011 General Purpose DDS/Altera/db/decode_dra.tdf      ;         ;
; db/decode_67a.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2011 General Purpose DDS/Altera/db/decode_67a.tdf      ;         ;
; db/mux_tlb.tdf                   ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2011 General Purpose DDS/Altera/db/mux_tlb.tdf         ;         ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                        ;
+---------------------------------------------+--------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                ;
+---------------------------------------------+--------------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 227                                                                                  ;
;                                             ;                                                                                      ;
; Total combinational functions               ; 210                                                                                  ;
; Logic element usage by number of LUT inputs ;                                                                                      ;
;     -- 4 input functions                    ; 90                                                                                   ;
;     -- 3 input functions                    ; 41                                                                                   ;
;     -- <=2 input functions                  ; 79                                                                                   ;
;                                             ;                                                                                      ;
; Logic elements by mode                      ;                                                                                      ;
;     -- normal mode                          ; 160                                                                                  ;
;     -- arithmetic mode                      ; 50                                                                                   ;
;                                             ;                                                                                      ;
; Total registers                             ; 86                                                                                   ;
;     -- Dedicated logic registers            ; 86                                                                                   ;
;     -- I/O registers                        ; 0                                                                                    ;
;                                             ;                                                                                      ;
; I/O pins                                    ; 41                                                                                   ;
; Total memory bits                           ; 262144                                                                               ;
; Total PLLs                                  ; 1                                                                                    ;
;     -- PLLs                                 ; 1                                                                                    ;
;                                             ;                                                                                      ;
; Maximum fan-out node                        ; altpll1:inst2|altpll:altpll_component|altpll1_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out                             ; 119                                                                                  ;
; Total fan-out                               ; 1559                                                                                 ;
; Average fan-out                             ; 3.72                                                                                 ;
+---------------------------------------------+--------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                              ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                       ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------+--------------+
; |GP_DDS                                   ; 210 (1)           ; 86 (0)       ; 262144      ; 0            ; 0       ; 0         ; 41   ; 0            ; |GP_DDS                                                                                                   ;              ;
;    |DoubleBuffer8:inst3|                  ; 0 (0)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|DoubleBuffer8:inst3                                                                               ;              ;
;    |altpll1:inst2|                        ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|altpll1:inst2                                                                                     ;              ;
;       |altpll:altpll_component|           ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|altpll1:inst2|altpll:altpll_component                                                             ;              ;
;          |altpll1_altpll:auto_generated|  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|altpll1:inst2|altpll:altpll_component|altpll1_altpll:auto_generated                               ;              ;
;    |ram_dq:inst|                          ; 24 (0)            ; 2 (0)        ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|ram_dq:inst                                                                                       ;              ;
;       |altsyncram:altsyncram_component|   ; 24 (0)            ; 2 (0)        ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|ram_dq:inst|altsyncram:altsyncram_component                                                       ;              ;
;          |altsyncram_q5f1:auto_generated| ; 24 (0)            ; 2 (2)        ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated                        ;              ;
;             |decode_67a:rden_decode|      ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|decode_67a:rden_decode ;              ;
;             |decode_dra:decode3|          ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|decode_dra:decode3     ;              ;
;             |mux_tlb:mux2|                ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|mux_tlb:mux2           ;              ;
;    |uberDDS:oneandonly|                   ; 185 (185)         ; 78 (78)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |GP_DDS|uberDDS:oneandonly                                                                                ;              ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                       ;
+---------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------+------+
; Name                                                                                  ; Type ; Mode        ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF  ;
+---------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------+------+
; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 32768        ; 8            ; --           ; --           ; 262144 ; None ;
+---------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------+------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                  ;
+--------+--------------+---------+--------------+--------------+-----------------------+----------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance       ; IP Include File                                                ;
+--------+--------------+---------+--------------+--------------+-----------------------+----------------------------------------------------------------+
; Altera ; ALTPLL       ; N/A     ; N/A          ; N/A          ; |GP_DDS|altpll1:inst2 ; C:/Projects/Archives/2011 General Purpose DDS/Altera/altpll1.v ;
; Altera ; RAM: 1-PORT  ; N/A     ; N/A          ; N/A          ; |GP_DDS|ram_dq:inst   ; C:/Projects/Archives/2011 General Purpose DDS/Altera/ram_dq.v  ;
+--------+--------------+---------+--------------+--------------+-----------------------+----------------------------------------------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |GP_DDS|uberDDS:oneandonly|State                                                                                                                                                                                                                  ;
+------------------------+-----------------------+--------------------+-----------------+-----------------+------------------+----------------+----------------+------------------------+---------------------+-----------------+----------------+------------------+
; Name                   ; State.RESTART_CMD_SEQ ; State.FINISHED_CMD ; State.NEXT_BYTE ; State.CLOCK_LOW ; State.CLOCK_HIGH ; State.NEXT_BIT ; State.HDWR_PIN ; State.WAIT_FOR_TRIGGER ; State.WAIT_FOR_RAMP ; State.NOT_A_REG ; State.CMD_SIZE ; State.START_CMDS ;
+------------------------+-----------------------+--------------------+-----------------+-----------------+------------------+----------------+----------------+------------------------+---------------------+-----------------+----------------+------------------+
; State.START_CMDS       ; 0                     ; 0                  ; 0               ; 0               ; 0                ; 0              ; 0              ; 0                      ; 0                   ; 0               ; 0              ; 0                ;
; State.CMD_SIZE         ; 0                     ; 0                  ; 0               ; 0               ; 0                ; 0              ; 0              ; 0                      ; 0                   ; 0               ; 1              ; 1                ;
; State.NOT_A_REG        ; 0                     ; 0                  ; 0               ; 0               ; 0                ; 0              ; 0              ; 0                      ; 0                   ; 1               ; 0              ; 1                ;
; State.WAIT_FOR_RAMP    ; 0                     ; 0                  ; 0               ; 0               ; 0                ; 0              ; 0              ; 0                      ; 1                   ; 0               ; 0              ; 1                ;
; State.WAIT_FOR_TRIGGER ; 0                     ; 0                  ; 0               ; 0               ; 0                ; 0              ; 0              ; 1                      ; 0                   ; 0               ; 0              ; 1                ;
; State.HDWR_PIN         ; 0                     ; 0                  ; 0               ; 0               ; 0                ; 0              ; 1              ; 0                      ; 0                   ; 0               ; 0              ; 1                ;
; State.NEXT_BIT         ; 0                     ; 0                  ; 0               ; 0               ; 0                ; 1              ; 0              ; 0                      ; 0                   ; 0               ; 0              ; 1                ;
; State.CLOCK_HIGH       ; 0                     ; 0                  ; 0               ; 0               ; 1                ; 0              ; 0              ; 0                      ; 0                   ; 0               ; 0              ; 1                ;
; State.CLOCK_LOW        ; 0                     ; 0                  ; 0               ; 1               ; 0                ; 0              ; 0              ; 0                      ; 0                   ; 0               ; 0              ; 1                ;
; State.NEXT_BYTE        ; 0                     ; 0                  ; 1               ; 0               ; 0                ; 0              ; 0              ; 0                      ; 0                   ; 0               ; 0              ; 1                ;
; State.FINISHED_CMD     ; 0                     ; 1                  ; 0               ; 0               ; 0                ; 0              ; 0              ; 0                      ; 0                   ; 0               ; 0              ; 1                ;
; State.RESTART_CMD_SEQ  ; 1                     ; 0                  ; 0               ; 0               ; 0                ; 0              ; 0              ; 0                      ; 0                   ; 0               ; 0              ; 1                ;
+------------------------+-----------------------+--------------------+-----------------+-----------------+------------------+----------------+----------------+------------------------+---------------------+-----------------+----------------+------------------+


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; uberDDS:oneandonly|rData[7]~reg0       ; Stuck at GND due to stuck port data_in ;
; uberDDS:oneandonly|rData[6]~reg0       ; Stuck at GND due to stuck port data_in ;
; uberDDS:oneandonly|rData[5]~reg0       ; Stuck at GND due to stuck port data_in ;
; uberDDS:oneandonly|rData[4]~reg0       ; Stuck at GND due to stuck port data_in ;
; uberDDS:oneandonly|rData[3]~reg0       ; Stuck at GND due to stuck port data_in ;
; uberDDS:oneandonly|rData[2]~reg0       ; Stuck at VCC due to stuck port data_in ;
; uberDDS:oneandonly|rData[1]~reg0       ; Stuck at VCC due to stuck port data_in ;
; uberDDS:oneandonly|rData[0]~reg0       ; Stuck at VCC due to stuck port data_in ;
; uberDDS:oneandonly|State~14            ; Lost fanout                            ;
; uberDDS:oneandonly|State~15            ; Lost fanout                            ;
; uberDDS:oneandonly|State~16            ; Lost fanout                            ;
; uberDDS:oneandonly|State~17            ; Lost fanout                            ;
; Total Number of Removed Registers = 12 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 86    ;
; Number of registers using Synchronous Clear  ; 6     ;
; Number of registers using Synchronous Load   ; 22    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 57    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; uberDDS:oneandonly|LastrCS             ; 3       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                               ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------------------------------------+----------------------------+
; 17:1               ; 15 bits   ; 165 LEs       ; 15 LEs               ; 150 LEs                ; |GP_DDS|uberDDS:oneandonly|CmdSeqSize[7] ;                            ;
; 6:1                ; 7 bits    ; 28 LEs        ; 7 LEs                ; 21 LEs                 ; |GP_DDS|uberDDS:oneandonly|BitMask[6]    ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |GP_DDS|uberDDS:oneandonly|ByteCtr[6]    ;                            ;
; 24:1               ; 15 bits   ; 240 LEs       ; 30 LEs               ; 210 LEs                ; |GP_DDS|uberDDS:oneandonly|CmdSeqAdr[11] ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |GP_DDS|uberDDS:oneandonly|IOrst         ;                            ;
; 9:1                ; 4 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; |GP_DDS|uberDDS:oneandonly|State         ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------------------------------------+----------------------------+


+---------------------------------------------------------------------------------------------------+
; Source assignments for ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------+
; Assignment                      ; Value              ; From ; To                                  ;
+---------------------------------+--------------------+------+-------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                   ;
+---------------------------------+--------------------+------+-------------------------------------+


+------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altpll1:inst2|altpll:altpll_component ;
+-------------------------------+---------------------------+------------------------+
; Parameter Name                ; Value                     ; Type                   ;
+-------------------------------+---------------------------+------------------------+
; OPERATION_MODE                ; NORMAL                    ; Untyped                ;
; PLL_TYPE                      ; AUTO                      ; Untyped                ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=altpll1 ; Untyped                ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                ;
; INCLK0_INPUT_FREQUENCY        ; 10000                     ; Signed Integer         ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                ;
; LOCK_HIGH                     ; 1                         ; Untyped                ;
; LOCK_LOW                      ; 1                         ; Untyped                ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                ;
; SKIP_VCO                      ; OFF                       ; Untyped                ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                ;
; BANDWIDTH                     ; 0                         ; Untyped                ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                ;
; DOWN_SPREAD                   ; 0                         ; Untyped                ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK1_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK0_MULTIPLY_BY              ; 3                         ; Signed Integer         ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK1_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK0_DIVIDE_BY                ; 5                         ; Signed Integer         ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK1_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer         ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                ;
; DPA_DIVIDER                   ; 0                         ; Untyped                ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                ;
; VCO_MIN                       ; 0                         ; Untyped                ;
; VCO_MAX                       ; 0                         ; Untyped                ;
; VCO_CENTER                    ; 0                         ; Untyped                ;
; PFD_MIN                       ; 0                         ; Untyped                ;
; PFD_MAX                       ; 0                         ; Untyped                ;
; M_INITIAL                     ; 0                         ; Untyped                ;
; M                             ; 0                         ; Untyped                ;
; N                             ; 1                         ; Untyped                ;
; M2                            ; 1                         ; Untyped                ;
; N2                            ; 1                         ; Untyped                ;
; SS                            ; 1                         ; Untyped                ;
; C0_HIGH                       ; 0                         ; Untyped                ;
; C1_HIGH                       ; 0                         ; Untyped                ;
; C2_HIGH                       ; 0                         ; Untyped                ;
; C3_HIGH                       ; 0                         ; Untyped                ;
; C4_HIGH                       ; 0                         ; Untyped                ;
; C5_HIGH                       ; 0                         ; Untyped                ;
; C6_HIGH                       ; 0                         ; Untyped                ;
; C7_HIGH                       ; 0                         ; Untyped                ;
; C8_HIGH                       ; 0                         ; Untyped                ;
; C9_HIGH                       ; 0                         ; Untyped                ;
; C0_LOW                        ; 0                         ; Untyped                ;
; C1_LOW                        ; 0                         ; Untyped                ;
; C2_LOW                        ; 0                         ; Untyped                ;
; C3_LOW                        ; 0                         ; Untyped                ;
; C4_LOW                        ; 0                         ; Untyped                ;
; C5_LOW                        ; 0                         ; Untyped                ;
; C6_LOW                        ; 0                         ; Untyped                ;
; C7_LOW                        ; 0                         ; Untyped                ;
; C8_LOW                        ; 0                         ; Untyped                ;
; C9_LOW                        ; 0                         ; Untyped                ;
; C0_INITIAL                    ; 0                         ; Untyped                ;
; C1_INITIAL                    ; 0                         ; Untyped                ;
; C2_INITIAL                    ; 0                         ; Untyped                ;
; C3_INITIAL                    ; 0                         ; Untyped                ;
; C4_INITIAL                    ; 0                         ; Untyped                ;
; C5_INITIAL                    ; 0                         ; Untyped                ;
; C6_INITIAL                    ; 0                         ; Untyped                ;
; C7_INITIAL                    ; 0                         ; Untyped                ;
; C8_INITIAL                    ; 0                         ; Untyped                ;
; C9_INITIAL                    ; 0                         ; Untyped                ;
; C0_MODE                       ; BYPASS                    ; Untyped                ;
; C1_MODE                       ; BYPASS                    ; Untyped                ;
; C2_MODE                       ; BYPASS                    ; Untyped                ;
; C3_MODE                       ; BYPASS                    ; Untyped                ;
; C4_MODE                       ; BYPASS                    ; Untyped                ;
; C5_MODE                       ; BYPASS                    ; Untyped                ;
; C6_MODE                       ; BYPASS                    ; Untyped                ;
; C7_MODE                       ; BYPASS                    ; Untyped                ;
; C8_MODE                       ; BYPASS                    ; Untyped                ;
; C9_MODE                       ; BYPASS                    ; Untyped                ;
; C0_PH                         ; 0                         ; Untyped                ;
; C1_PH                         ; 0                         ; Untyped                ;
; C2_PH                         ; 0                         ; Untyped                ;
; C3_PH                         ; 0                         ; Untyped                ;
; C4_PH                         ; 0                         ; Untyped                ;
; C5_PH                         ; 0                         ; Untyped                ;
; C6_PH                         ; 0                         ; Untyped                ;
; C7_PH                         ; 0                         ; Untyped                ;
; C8_PH                         ; 0                         ; Untyped                ;
; C9_PH                         ; 0                         ; Untyped                ;
; L0_HIGH                       ; 1                         ; Untyped                ;
; L1_HIGH                       ; 1                         ; Untyped                ;
; G0_HIGH                       ; 1                         ; Untyped                ;
; G1_HIGH                       ; 1                         ; Untyped                ;
; G2_HIGH                       ; 1                         ; Untyped                ;
; G3_HIGH                       ; 1                         ; Untyped                ;
; E0_HIGH                       ; 1                         ; Untyped                ;
; E1_HIGH                       ; 1                         ; Untyped                ;
; E2_HIGH                       ; 1                         ; Untyped                ;
; E3_HIGH                       ; 1                         ; Untyped                ;
; L0_LOW                        ; 1                         ; Untyped                ;
; L1_LOW                        ; 1                         ; Untyped                ;
; G0_LOW                        ; 1                         ; Untyped                ;
; G1_LOW                        ; 1                         ; Untyped                ;
; G2_LOW                        ; 1                         ; Untyped                ;
; G3_LOW                        ; 1                         ; Untyped                ;
; E0_LOW                        ; 1                         ; Untyped                ;
; E1_LOW                        ; 1                         ; Untyped                ;
; E2_LOW                        ; 1                         ; Untyped                ;
; E3_LOW                        ; 1                         ; Untyped                ;
; L0_INITIAL                    ; 1                         ; Untyped                ;
; L1_INITIAL                    ; 1                         ; Untyped                ;
; G0_INITIAL                    ; 1                         ; Untyped                ;
; G1_INITIAL                    ; 1                         ; Untyped                ;
; G2_INITIAL                    ; 1                         ; Untyped                ;
; G3_INITIAL                    ; 1                         ; Untyped                ;
; E0_INITIAL                    ; 1                         ; Untyped                ;
; E1_INITIAL                    ; 1                         ; Untyped                ;
; E2_INITIAL                    ; 1                         ; Untyped                ;
; E3_INITIAL                    ; 1                         ; Untyped                ;
; L0_MODE                       ; BYPASS                    ; Untyped                ;
; L1_MODE                       ; BYPASS                    ; Untyped                ;
; G0_MODE                       ; BYPASS                    ; Untyped                ;
; G1_MODE                       ; BYPASS                    ; Untyped                ;
; G2_MODE                       ; BYPASS                    ; Untyped                ;
; G3_MODE                       ; BYPASS                    ; Untyped                ;
; E0_MODE                       ; BYPASS                    ; Untyped                ;
; E1_MODE                       ; BYPASS                    ; Untyped                ;
; E2_MODE                       ; BYPASS                    ; Untyped                ;
; E3_MODE                       ; BYPASS                    ; Untyped                ;
; L0_PH                         ; 0                         ; Untyped                ;
; L1_PH                         ; 0                         ; Untyped                ;
; G0_PH                         ; 0                         ; Untyped                ;
; G1_PH                         ; 0                         ; Untyped                ;
; G2_PH                         ; 0                         ; Untyped                ;
; G3_PH                         ; 0                         ; Untyped                ;
; E0_PH                         ; 0                         ; Untyped                ;
; E1_PH                         ; 0                         ; Untyped                ;
; E2_PH                         ; 0                         ; Untyped                ;
; E3_PH                         ; 0                         ; Untyped                ;
; M_PH                          ; 0                         ; Untyped                ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                ;
; CLK0_COUNTER                  ; G0                        ; Untyped                ;
; CLK1_COUNTER                  ; G0                        ; Untyped                ;
; CLK2_COUNTER                  ; G0                        ; Untyped                ;
; CLK3_COUNTER                  ; G0                        ; Untyped                ;
; CLK4_COUNTER                  ; G0                        ; Untyped                ;
; CLK5_COUNTER                  ; G0                        ; Untyped                ;
; CLK6_COUNTER                  ; E0                        ; Untyped                ;
; CLK7_COUNTER                  ; E1                        ; Untyped                ;
; CLK8_COUNTER                  ; E2                        ; Untyped                ;
; CLK9_COUNTER                  ; E3                        ; Untyped                ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                ;
; M_TIME_DELAY                  ; 0                         ; Untyped                ;
; N_TIME_DELAY                  ; 0                         ; Untyped                ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                ;
; VCO_POST_SCALE                ; 0                         ; Untyped                ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; INTENDED_DEVICE_FAMILY        ; Cyclone III               ; Untyped                ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                ;
; PORT_CLK1                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                ;
; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                ;
; CBXI_PARAMETER                ; altpll1_altpll            ; Untyped                ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                ;
; WIDTH_CLOCK                   ; 5                         ; Signed Integer         ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                ;
; DEVICE_FAMILY                 ; Cyclone III               ; Untyped                ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE         ;
+-------------------------------+---------------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram_dq:inst|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------+
; Parameter Name                     ; Value                ; Type                         ;
+------------------------------------+----------------------+------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                      ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                   ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                 ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE               ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                      ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                      ;
; WIDTH_A                            ; 8                    ; Signed Integer               ;
; WIDTHAD_A                          ; 15                   ; Signed Integer               ;
; NUMWORDS_A                         ; 32768                ; Signed Integer               ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                      ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                      ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                      ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                      ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                      ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                      ;
; WIDTH_B                            ; 1                    ; Untyped                      ;
; WIDTHAD_B                          ; 1                    ; Untyped                      ;
; NUMWORDS_B                         ; 1                    ; Untyped                      ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                      ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                      ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                      ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                      ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                      ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                      ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                      ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                      ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                      ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                      ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                      ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer               ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                      ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                      ;
; BYTE_SIZE                          ; 8                    ; Untyped                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                      ;
; READ_DURING_WRITE_MODE_PORT_A      ; DONT_CARE            ; Untyped                      ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                      ;
; INIT_FILE                          ; UNUSED               ; Untyped                      ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                      ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                      ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                      ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                      ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                      ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                      ;
; ENABLE_ECC                         ; FALSE                ; Untyped                      ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                      ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                      ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                      ;
; CBXI_PARAMETER                     ; altsyncram_q5f1      ; Untyped                      ;
+------------------------------------+----------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                          ;
+-------------------------------+---------------------------------------+
; Name                          ; Value                                 ;
+-------------------------------+---------------------------------------+
; Number of entity instances    ; 1                                     ;
; Entity Instance               ; altpll1:inst2|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                ;
;     -- PLL_TYPE               ; AUTO                                  ;
;     -- PRIMARY_CLOCK          ; INCLK0                                ;
;     -- INCLK0_INPUT_FREQUENCY ; 10000                                 ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                     ;
;     -- VCO_MULTIPLY_BY        ; 0                                     ;
;     -- VCO_DIVIDE_BY          ; 0                                     ;
+-------------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                        ;
+-------------------------------------------+---------------------------------------------+
; Name                                      ; Value                                       ;
+-------------------------------------------+---------------------------------------------+
; Number of entity instances                ; 1                                           ;
; Entity Instance                           ; ram_dq:inst|altsyncram:altsyncram_component ;
;     -- OPERATION_MODE                     ; SINGLE_PORT                                 ;
;     -- WIDTH_A                            ; 8                                           ;
;     -- NUMWORDS_A                         ; 32768                                       ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                ;
;     -- WIDTH_B                            ; 1                                           ;
;     -- NUMWORDS_B                         ; 1                                           ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                      ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                        ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                   ;
+-------------------------------------------+---------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:02     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 12.0 Build 178 05/31/2012 SJ Full Version
    Info: Processing started: Tue May 06 17:27:28 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GP_DDS -c GP_DDS
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file gp_dds.bdf
    Info (12023): Found entity 1: GP_DDS
Info (12021): Found 1 design units, including 1 entities, in source file doublebuffer8.v
    Info (12023): Found entity 1: DoubleBuffer8
Info (12021): Found 1 design units, including 1 entities, in source file ram_dq.v
    Info (12023): Found entity 1: ram_dq
Info (12021): Found 1 design units, including 1 entities, in source file altpll1.v
    Info (12023): Found entity 1: altpll1
Info (12021): Found 1 design units, including 1 entities, in source file uberdds.v
    Info (12023): Found entity 1: uberDDS
Info (12127): Elaborating entity "GP_DDS" for the top level hierarchy
Info (12128): Elaborating entity "uberDDS" for hierarchy "uberDDS:oneandonly"
Info (12128): Elaborating entity "DoubleBuffer8" for hierarchy "DoubleBuffer8:inst3"
Info (12128): Elaborating entity "altpll1" for hierarchy "altpll1:inst2"
Info (12128): Elaborating entity "altpll" for hierarchy "altpll1:inst2|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "altpll1:inst2|altpll:altpll_component"
Info (12133): Instantiated megafunction "altpll1:inst2|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "5"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "3"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "10000"
    Info (12134): Parameter "intended_device_family" = "Cyclone III"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll1"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/altpll1_altpll.v
    Info (12023): Found entity 1: altpll1_altpll
Info (12128): Elaborating entity "altpll1_altpll" for hierarchy "altpll1:inst2|altpll:altpll_component|altpll1_altpll:auto_generated"
Info (12128): Elaborating entity "ram_dq" for hierarchy "ram_dq:inst"
Info (12128): Elaborating entity "altsyncram" for hierarchy "ram_dq:inst|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "ram_dq:inst|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "ram_dq:inst|altsyncram:altsyncram_component" with the following parameter:
    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
    Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
    Info (12134): Parameter "intended_device_family" = "Cyclone III"
    Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "32768"
    Info (12134): Parameter "operation_mode" = "SINGLE_PORT"
    Info (12134): Parameter "outdata_aclr_a" = "NONE"
    Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "read_during_write_mode_port_a" = "DONT_CARE"
    Info (12134): Parameter "widthad_a" = "15"
    Info (12134): Parameter "width_a" = "8"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_q5f1.tdf
    Info (12023): Found entity 1: altsyncram_q5f1
Info (12128): Elaborating entity "altsyncram_q5f1" for hierarchy "ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_dra.tdf
    Info (12023): Found entity 1: decode_dra
Info (12128): Elaborating entity "decode_dra" for hierarchy "ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|decode_dra:decode3"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_67a.tdf
    Info (12023): Found entity 1: decode_67a
Info (12128): Elaborating entity "decode_67a" for hierarchy "ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|decode_67a:rden_decode"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_tlb.tdf
    Info (12023): Found entity 1: mux_tlb
Info (12128): Elaborating entity "mux_tlb" for hierarchy "ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|mux_tlb:mux2"
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "TXen" is stuck at VCC
    Warning (13410): Pin "TP1" is stuck at GND
    Warning (13410): Pin "TP2" is stuck at GND
    Warning (13410): Pin "P[0]" is stuck at GND
    Warning (13410): Pin "P[1]" is stuck at GND
    Warning (13410): Pin "P[2]" is stuck at GND
Info (286030): Timing-Driven Synthesis is running
Info (17049): 4 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file C:/Projects/Archives/2011 General Purpose DDS/Altera/GP_DDS.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 8 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "Spare_in1"
    Warning (15610): No output dependent on input pin "Spare_in2"
    Warning (15610): No output dependent on input pin "Sdo"
    Warning (15610): No output dependent on input pin "PLLlock"
    Warning (15610): No output dependent on input pin "RAMswpOvr"
    Warning (15610): No output dependent on input pin "rSpare[2]"
    Warning (15610): No output dependent on input pin "rSpare[1]"
    Warning (15610): No output dependent on input pin "rSpare[0]"
Info (21057): Implemented 303 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 16 input pins
    Info (21059): Implemented 17 output pins
    Info (21060): Implemented 8 bidirectional pins
    Info (21061): Implemented 229 logic cells
    Info (21064): Implemented 32 RAM segments
    Info (21065): Implemented 1 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Peak virtual memory: 433 megabytes
    Info: Processing ended: Tue May 06 17:27:44 2014
    Info: Elapsed time: 00:00:16
    Info: Total CPU time (on all processors): 00:00:04


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Projects/Archives/2011 General Purpose DDS/Altera/GP_DDS.map.smsg.


