TimeQuest Timing Analyzer report for GP_DDS
Tue May 06 17:28:26 2014
Quartus II 64-Bit Version 12.0 Build 178 05/31/2012 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 13. Slow 1200mV 85C Model Hold: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 14. Slow 1200mV 85C Model Minimum Pulse Width: 'Clock'
 15. Slow 1200mV 85C Model Minimum Pulse Width: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 16. Setup Times
 17. Hold Times
 18. Clock to Output Times
 19. Minimum Clock to Output Times
 20. Propagation Delay
 21. Minimum Propagation Delay
 22. Output Enable Times
 23. Minimum Output Enable Times
 24. Output Disable Times
 25. Minimum Output Disable Times
 26. Slow 1200mV 85C Model Metastability Report
 27. Slow 1200mV 0C Model Fmax Summary
 28. Slow 1200mV 0C Model Setup Summary
 29. Slow 1200mV 0C Model Hold Summary
 30. Slow 1200mV 0C Model Recovery Summary
 31. Slow 1200mV 0C Model Removal Summary
 32. Slow 1200mV 0C Model Minimum Pulse Width Summary
 33. Slow 1200mV 0C Model Setup: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 0C Model Hold: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 35. Slow 1200mV 0C Model Minimum Pulse Width: 'Clock'
 36. Slow 1200mV 0C Model Minimum Pulse Width: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 37. Setup Times
 38. Hold Times
 39. Clock to Output Times
 40. Minimum Clock to Output Times
 41. Propagation Delay
 42. Minimum Propagation Delay
 43. Output Enable Times
 44. Minimum Output Enable Times
 45. Output Disable Times
 46. Minimum Output Disable Times
 47. Slow 1200mV 0C Model Metastability Report
 48. Fast 1200mV 0C Model Setup Summary
 49. Fast 1200mV 0C Model Hold Summary
 50. Fast 1200mV 0C Model Recovery Summary
 51. Fast 1200mV 0C Model Removal Summary
 52. Fast 1200mV 0C Model Minimum Pulse Width Summary
 53. Fast 1200mV 0C Model Setup: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 54. Fast 1200mV 0C Model Hold: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 55. Fast 1200mV 0C Model Minimum Pulse Width: 'Clock'
 56. Fast 1200mV 0C Model Minimum Pulse Width: 'inst2|altpll_component|auto_generated|pll1|clk[0]'
 57. Setup Times
 58. Hold Times
 59. Clock to Output Times
 60. Minimum Clock to Output Times
 61. Propagation Delay
 62. Minimum Propagation Delay
 63. Output Enable Times
 64. Minimum Output Enable Times
 65. Output Disable Times
 66. Minimum Output Disable Times
 67. Fast 1200mV 0C Model Metastability Report
 68. Multicorner Timing Analysis Summary
 69. Setup Times
 70. Hold Times
 71. Clock to Output Times
 72. Minimum Clock to Output Times
 73. Progagation Delay
 74. Minimum Progagation Delay
 75. Board Trace Model Assignments
 76. Input Transition Times
 77. Slow Corner Signal Integrity Metrics
 78. Fast Corner Signal Integrity Metrics
 79. Setup Transfers
 80. Hold Transfers
 81. Report TCCS
 82. Report RSKM
 83. Unconstrained Paths
 84. TimeQuest Timing Analyzer Messages
 85. TimeQuest Timing Analyzer Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                      ;
+--------------------+---------------------------------------------------+
; Quartus II Version ; Version 12.0 Build 178 05/31/2012 SJ Full Version ;
; Revision Name      ; GP_DDS                                            ;
; Device Family      ; Cyclone III                                       ;
; Device Name        ; EP3C10E144C7                                      ;
; Timing Models      ; Final                                             ;
; Delay Model        ; Combined                                          ;
; Rise/Fall Delays   ; Enabled                                           ;
+--------------------+---------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ; < 0.1%      ;
+----------------------------+-------------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; GP_DDS.sdc    ; OK     ; Tue May 06 17:28:24 2014 ;
+---------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                ;
+---------------------------------------------------+-----------+--------+-----------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+
; Clock Name                                        ; Type      ; Period ; Frequency ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source                                              ; Targets                                               ;
+---------------------------------------------------+-----------+--------+-----------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+
; Clock                                             ; Base      ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                     ; { Clk }                                               ;
; inst2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 16.666 ; 60.0 MHz  ; 0.000 ; 8.333 ; 50.00      ; 5         ; 3           ;       ;        ;           ;            ; false    ; Clock  ; inst2|altpll_component|auto_generated|pll1|inclk[0] ; { inst2|altpll_component|auto_generated|pll1|clk[0] } ;
+---------------------------------------------------+-----------+--------+-----------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                     ;
+-----------+-----------------+---------------------------------------------------+------+
; Fmax      ; Restricted Fmax ; Clock Name                                        ; Note ;
+-----------+-----------------+---------------------------------------------------+------+
; 59.51 MHz ; 59.51 MHz       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+-----------+-----------------+---------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+----------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                        ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; inst2|altpll_component|auto_generated|pll1|clk[0] ; -0.069 ; -0.636        ;
+---------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                        ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; Slack ; End Point TNS ;
+---------------------------------------------------+-------+---------------+
; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.397 ; 0.000         ;
+---------------------------------------------------+-------+---------------+


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+---------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                         ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; Slack ; End Point TNS ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; 4.793 ; 0.000         ;
; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.046 ; 0.000         ;
+---------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                ;
+--------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                             ; To Node                       ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; -0.069 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.958      ;
; -0.069 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.958      ;
; -0.069 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.958      ;
; -0.069 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.958      ;
; -0.069 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.958      ;
; -0.069 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.958      ;
; -0.069 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.958      ;
; -0.051 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.443     ; 7.939      ;
; -0.051 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.443     ; 7.939      ;
; -0.051 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.443     ; 7.939      ;
; -0.041 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.444     ; 7.928      ;
; -0.041 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.444     ; 7.928      ;
; -0.041 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.444     ; 7.928      ;
; -0.041 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.444     ; 7.928      ;
; -0.041 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.444     ; 7.928      ;
; -0.041 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.444     ; 7.928      ;
; -0.041 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.444     ; 7.928      ;
; -0.008 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.910      ;
; -0.008 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.910      ;
; -0.008 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.910      ;
; 0.004  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.440     ; 7.887      ;
; 0.004  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.440     ; 7.887      ;
; 0.004  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.440     ; 7.887      ;
; 0.004  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.440     ; 7.887      ;
; 0.004  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.440     ; 7.887      ;
; 0.004  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.440     ; 7.887      ;
; 0.004  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.440     ; 7.887      ;
; 0.009  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.894      ;
; 0.009  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.894      ;
; 0.009  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.894      ;
; 0.009  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.894      ;
; 0.009  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.894      ;
; 0.009  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.894      ;
; 0.009  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.894      ;
; 0.018  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.425     ; 7.888      ;
; 0.018  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.425     ; 7.888      ;
; 0.018  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.425     ; 7.888      ;
; 0.029  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.449     ; 7.853      ;
; 0.029  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.449     ; 7.853      ;
; 0.029  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.449     ; 7.853      ;
; 0.029  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.449     ; 7.853      ;
; 0.029  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.449     ; 7.853      ;
; 0.029  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.449     ; 7.853      ;
; 0.029  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.449     ; 7.853      ;
; 0.039  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.850      ;
; 0.039  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.850      ;
; 0.039  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.850      ;
; 0.039  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.850      ;
; 0.039  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.850      ;
; 0.039  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.850      ;
; 0.039  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.442     ; 7.850      ;
; 0.045  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.430     ; 7.856      ;
; 0.045  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.430     ; 7.856      ;
; 0.045  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.430     ; 7.856      ;
; 0.094  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.808      ;
; 0.094  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.808      ;
; 0.094  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.808      ;
; 0.108  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.431     ; 7.792      ;
; 0.108  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.431     ; 7.792      ;
; 0.108  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.431     ; 7.792      ;
; 0.109  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.441     ; 7.781      ;
; 0.109  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.441     ; 7.781      ;
; 0.109  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.441     ; 7.781      ;
; 0.109  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.441     ; 7.781      ;
; 0.109  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.441     ; 7.781      ;
; 0.109  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.441     ; 7.781      ;
; 0.109  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.441     ; 7.781      ;
; 0.111  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.443     ; 7.777      ;
; 0.111  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.443     ; 7.777      ;
; 0.111  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.443     ; 7.777      ;
; 0.119  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.783      ;
; 0.119  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.783      ;
; 0.119  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.783      ;
; 0.120  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.785      ;
; 0.120  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.785      ;
; 0.120  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.785      ;
; 0.155  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.750      ;
; 0.155  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.750      ;
; 0.155  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.750      ;
; 0.155  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.750      ;
; 0.155  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.750      ;
; 0.155  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.750      ;
; 0.155  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.426     ; 7.750      ;
; 0.157  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.746      ;
; 0.157  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.746      ;
; 0.157  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.428     ; 7.746      ;
; 0.163  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.445     ; 7.723      ;
; 0.163  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.445     ; 7.723      ;
; 0.163  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.445     ; 7.723      ;
; 0.166  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.446     ; 7.719      ;
; 0.166  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.446     ; 7.719      ;
; 0.166  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.446     ; 7.719      ;
; 0.167  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.448     ; 7.716      ;
; 0.167  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.448     ; 7.716      ;
; 0.167  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.448     ; 7.716      ;
; 0.167  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.448     ; 7.716      ;
; 0.167  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.448     ; 7.716      ;
; 0.167  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.448     ; 7.716      ;
; 0.167  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.448     ; 7.716      ;
; 0.167  ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.429     ; 7.735      ;
+--------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                        ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                               ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; 0.397 ; uberDDS:oneandonly|IOupdateRun        ; uberDDS:oneandonly|IOupdateRun        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 0.669      ;
; 0.412 ; uberDDS:oneandonly|CmdSeqFull         ; uberDDS:oneandonly|CmdSeqFull         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|RunSequence        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; uberDDS:oneandonly|CmdSeqWrite        ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.439 ; DoubleBuffer8:inst3|D55               ; DoubleBuffer8:inst3|Q5                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.696      ;
; 0.440 ; DoubleBuffer8:inst3|D22               ; DoubleBuffer8:inst3|Q2                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.697      ;
; 0.453 ; uberDDS:oneandonly|LastrCS            ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.710      ;
; 0.457 ; uberDDS:oneandonly|BitMask[6]         ; uberDDS:oneandonly|BitMask[5]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.714      ;
; 0.461 ; uberDDS:oneandonly|BitMask[1]         ; uberDDS:oneandonly|BitMask[0]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.718      ;
; 0.468 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|BitMask[4]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.725      ;
; 0.468 ; uberDDS:oneandonly|BitMask[3]         ; uberDDS:oneandonly|BitMask[2]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.725      ;
; 0.592 ; uberDDS:oneandonly|BitMask[2]         ; uberDDS:oneandonly|BitMask[1]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.849      ;
; 0.623 ; uberDDS:oneandonly|BitMask[4]         ; uberDDS:oneandonly|BitMask[3]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.880      ;
; 0.665 ; uberDDS:oneandonly|State.CLOCK_HIGH   ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.922      ;
; 0.666 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.923      ;
; 0.666 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.923      ;
; 0.667 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.924      ;
; 0.667 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.924      ;
; 0.667 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.924      ;
; 0.667 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.924      ;
; 0.668 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.925      ;
; 0.668 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.925      ;
; 0.668 ; uberDDS:oneandonly|State.CLOCK_HIGH   ; uberDDS:oneandonly|State.CLOCK_LOW    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.925      ;
; 0.671 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.928      ;
; 0.671 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.928      ;
; 0.689 ; uberDDS:oneandonly|CmdSeqAdr[13]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.946      ;
; 0.691 ; uberDDS:oneandonly|CmdSeqAdr[14]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.948      ;
; 0.691 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[0]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.948      ;
; 0.728 ; uberDDS:oneandonly|CmdSeqFull         ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.985      ;
; 0.813 ; uberDDS:oneandonly|BitMask[0]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.496      ; 1.495      ;
; 0.823 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.496      ; 1.505      ;
; 0.824 ; uberDDS:oneandonly|CmdSeqAdr[1]       ; uberDDS:oneandonly|CmdSeqAdr[1]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.081      ;
; 0.827 ; uberDDS:oneandonly|CmdSeqAdr[3]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.084      ;
; 0.839 ; uberDDS:oneandonly|State.CLOCK_LOW    ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.500      ; 1.525      ;
; 0.845 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[1]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.445      ; 1.476      ;
; 0.845 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[6]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.445      ; 1.476      ;
; 0.959 ; uberDDS:oneandonly|BitMask[3]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.496      ; 1.641      ;
; 0.984 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.241      ;
; 0.984 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.241      ;
; 0.985 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.242      ;
; 0.985 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.242      ;
; 0.989 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.CLOCK_HIGH   ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.241      ;
; 0.990 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.242      ;
; 0.993 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.CLOCK_LOW    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.245      ;
; 0.993 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.250      ;
; 0.994 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.251      ;
; 0.994 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.251      ;
; 0.994 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.251      ;
; 0.995 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[1]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.252      ;
; 0.998 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.255      ;
; 0.998 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.255      ;
; 0.998 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.255      ;
; 0.999 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.256      ;
; 0.999 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.256      ;
; 0.999 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.256      ;
; 1.000 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.257      ;
; 1.003 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.260      ;
; 1.003 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.260      ;
; 1.006 ; uberDDS:oneandonly|CmdSeqAdr[13]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.263      ;
; 1.023 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.502      ; 1.711      ;
; 1.066 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.495      ; 1.747      ;
; 1.067 ; uberDDS:oneandonly|Rst                ; uberDDS:oneandonly|Rst                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.325      ;
; 1.076 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.START_CMDS   ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.332      ;
; 1.080 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[5]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.445      ; 1.711      ;
; 1.080 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[7]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.445      ; 1.711      ;
; 1.081 ; uberDDS:oneandonly|BitMask[2]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.496      ; 1.763      ;
; 1.096 ; uberDDS:oneandonly|BitMask[6]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.496      ; 1.778      ;
; 1.104 ; uberDDS:oneandonly|State.FINISHED_CMD ; uberDDS:oneandonly|State.FINISHED_CMD ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.361      ;
; 1.105 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.362      ;
; 1.105 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.362      ;
; 1.106 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.363      ;
; 1.106 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.363      ;
; 1.107 ; uberDDS:oneandonly|State.START_CMDS   ; uberDDS:oneandonly|Rst                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.365      ;
; 1.107 ; uberDDS:oneandonly|State.CLOCK_LOW    ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.506      ; 1.799      ;
; 1.110 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.367      ;
; 1.110 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.367      ;
; 1.111 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.368      ;
; 1.111 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.368      ;
; 1.112 ; uberDDS:oneandonly|State.START_CMDS   ; uberDDS:oneandonly|TrigDirect         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.370      ;
; 1.119 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.376      ;
; 1.120 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.377      ;
; 1.120 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.377      ;
; 1.121 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.378      ;
; 1.124 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.381      ;
; 1.124 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.381      ;
; 1.124 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.381      ;
; 1.125 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.382      ;
; 1.125 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.382      ;
; 1.126 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.383      ;
; 1.129 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.386      ;
; 1.129 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.386      ;
; 1.136 ; uberDDS:oneandonly|BitMask[1]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.496      ; 1.818      ;
; 1.142 ; uberDDS:oneandonly|CmdSeqAdr[1]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.399      ;
; 1.143 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|State.NOT_A_REG    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.502      ; 1.831      ;
; 1.145 ; uberDDS:oneandonly|CmdSeqAdr[3]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.402      ;
; 1.165 ; uberDDS:oneandonly|DRhold             ; uberDDS:oneandonly|DRhold             ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.423      ;
; 1.168 ; uberDDS:oneandonly|State.START_CMDS   ; uberDDS:oneandonly|State.CMD_SIZE     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.426      ;
; 1.171 ; uberDDS:oneandonly|BitMask[0]         ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.502      ; 1.859      ;
; 1.183 ; uberDDS:oneandonly|Sclk               ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.440      ;
; 1.187 ; uberDDS:oneandonly|SDio               ; uberDDS:oneandonly|SDio               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.444      ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'Clock'                                                                                          ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                      ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+
; 4.793 ; 4.793        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0]           ;
; 4.793 ; 4.793        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|observablevcoout ;
; 4.811 ; 4.811        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; Clk~input|o                                                 ;
; 4.828 ; 4.828        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.000 ; 5.000        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; Clk~input|i                                                 ;
; 5.000 ; 5.000        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; Clk~input|i                                                 ;
; 5.171 ; 5.171        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.189 ; 5.189        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; Clk~input|o                                                 ;
; 5.205 ; 5.205        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0]           ;
; 5.205 ; 5.205        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|observablevcoout ;
; 6.000 ; 10.000       ; 4.000          ; Port Rate        ; Clock ; Rise       ; Clk                                                         ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+-------+--------------+----------------+-----------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                             ; Clock Edge ; Target                                                                                                      ;
+-------+--------------+----------------+-----------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; 8.046 ; 8.281        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_address_reg0 ;
; 8.046 ; 8.281        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_re_reg       ;
; 8.046 ; 8.281        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_we_reg       ;
; 8.046 ; 8.281        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_address_reg0 ;
; 8.046 ; 8.281        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg       ;
; 8.046 ; 8.281        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_we_reg       ;
; 8.047 ; 8.282        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.047 ; 8.282        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg        ;
; 8.047 ; 8.282        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.047 ; 8.282        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_address_reg0 ;
; 8.047 ; 8.282        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg       ;
; 8.047 ; 8.282        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_we_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg        ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_datain_reg0  ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_address_reg0 ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_we_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_address_reg0 ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_we_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_address_reg0 ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_we_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_datain_reg0  ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_address_reg0 ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_we_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_address_reg0 ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_re_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_we_reg       ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_re_reg        ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_address_reg0  ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg        ;
; 8.048 ; 8.283        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_we_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_datain_reg0  ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_address_reg0 ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_re_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_we_reg       ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_we_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_address_reg0  ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_re_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_we_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_address_reg0  ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_we_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_address_reg0  ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg        ;
; 8.049 ; 8.284        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_we_reg        ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_datain_reg0  ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_datain_reg0  ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_datain_reg0  ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_datain_reg0  ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_datain_reg0  ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_address_reg0  ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_re_reg        ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_we_reg        ;
; 8.050 ; 8.285        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_datain_reg0   ;
; 8.051 ; 8.286        ; 0.235          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_datain_reg0  ;
+-------+--------------+----------------+-----------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                             ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; DRover    ; Clock      ; 5.253 ; 5.782 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Trigger   ; Clock      ; 5.073 ; 5.613 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCS       ; Clock      ; 4.412 ; 4.779 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; 5.472 ; 5.949 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 4.336 ; 4.861 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.928 ; 5.441 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 5.061 ; 5.614 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; 4.375 ; 4.762 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4] ; Clock      ; 4.836 ; 5.322 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; 5.472 ; 5.949 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; 5.167 ; 5.654 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7] ; Clock      ; 4.265 ; 4.716 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCmd[*]   ; Clock      ; 7.847 ; 8.279 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[0]  ; Clock      ; 7.332 ; 7.824 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[1]  ; Clock      ; 6.959 ; 7.452 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[2]  ; Clock      ; 7.149 ; 7.637 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[3]  ; Clock      ; 7.847 ; 8.279 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; 6.237 ; 6.745 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 6.237 ; 6.745 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 5.960 ; 6.470 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 5.767 ; 6.317 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; 6.236 ; 6.683 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; 5.421 ; 5.905 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; 5.981 ; 6.500 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+
; DRover    ; Clock      ; -4.493 ; -5.003 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Trigger   ; Clock      ; -4.320 ; -4.840 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCS       ; Clock      ; -3.692 ; -4.038 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; -3.145 ; -3.554 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; -3.145 ; -3.554 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; -3.452 ; -3.928 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; -3.877 ; -4.397 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; -3.230 ; -3.618 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4] ; Clock      ; -3.539 ; -4.039 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; -3.487 ; -3.964 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; -3.758 ; -4.232 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7] ; Clock      ; -3.209 ; -3.675 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCmd[*]   ; Clock      ; -3.769 ; -4.161 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[0]  ; Clock      ; -4.616 ; -4.976 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[1]  ; Clock      ; -4.298 ; -4.680 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[2]  ; Clock      ; -3.769 ; -4.161 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[3]  ; Clock      ; -4.376 ; -4.794 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; -4.151 ; -4.606 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; -4.983 ; -5.457 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; -5.172 ; -5.661 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; -4.954 ; -5.498 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; -4.666 ; -5.056 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; -4.151 ; -4.606 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; -4.625 ; -5.107 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                    ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Q2         ; Clock      ; 4.477 ; 4.498 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; CmdSeqFull ; Clock      ; 4.721 ; 4.709 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRctl      ; Clock      ; 5.291 ; 5.274 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRhold     ; Clock      ; 5.608 ; 5.592 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOrst      ; Clock      ; 4.532 ; 4.616 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOupdate   ; Clock      ; 6.572 ; 6.570 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q1         ; Clock      ; 5.534 ; 5.516 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q3         ; Clock      ; 8.758 ; 9.002 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Rst        ; Clock      ; 4.179 ; 4.209 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; SDio       ; Clock      ; 4.445 ; 4.495 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Sclk       ; Clock      ; 4.905 ; 5.019 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]   ; Clock      ; 6.332 ; 6.063 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3]  ; Clock      ; 3.675 ; 3.715 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4]  ; Clock      ; 3.441 ; 3.447 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5]  ; Clock      ; 3.408 ; 3.415 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6]  ; Clock      ; 6.332 ; 6.063 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7]  ; Clock      ; 3.961 ; 3.992 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+------------+------------+-------+-------+------------+---------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                            ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Q2         ; Clock      ; 4.023 ; 4.044 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; CmdSeqFull ; Clock      ; 4.257 ; 4.246 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRctl      ; Clock      ; 4.799 ; 4.782 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRhold     ; Clock      ; 5.104 ; 5.087 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOrst      ; Clock      ; 4.070 ; 4.150 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOupdate   ; Clock      ; 5.352 ; 5.361 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q1         ; Clock      ; 5.032 ; 5.014 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q3         ; Clock      ; 7.554 ; 7.810 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Rst        ; Clock      ; 3.731 ; 3.759 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; SDio       ; Clock      ; 3.988 ; 4.035 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Sclk       ; Clock      ; 4.429 ; 4.537 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]   ; Clock      ; 2.990 ; 2.998 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3]  ; Clock      ; 3.246 ; 3.285 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4]  ; Clock      ; 3.022 ; 3.029 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5]  ; Clock      ; 2.990 ; 2.998 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6]  ; Clock      ; 5.913 ; 5.645 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7]  ; Clock      ; 3.521 ; 3.552 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+------------+------------+-------+-------+------------+---------------------------------------------------+


+------------------------------------------------------+
; Propagation Delay                                    ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Trigger    ; IOupdate    ; 9.054  ;    ;    ; 9.579  ;
; Trigger    ; Q3          ; 11.240 ;    ;    ; 12.011 ;
+------------+-------------+--------+----+----+--------+


+------------------------------------------------------+
; Minimum Propagation Delay                            ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Trigger    ; IOupdate    ; 8.799  ;    ;    ; 9.312  ;
; Trigger    ; Q3          ; 11.001 ;    ;    ; 11.761 ;
+------------+-------------+--------+----+----+--------+


+---------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                     ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 4.551 ; 4.168 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 4.793 ; 4.410 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.551 ; 4.168 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 4.780 ; 4.397 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                             ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 4.005 ; 3.637 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 4.237 ; 3.869 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.005 ; 3.637 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 4.224 ; 3.856 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                            ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 4.218     ; 4.601     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 4.428     ; 4.811     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.218     ; 4.601     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 4.372     ; 4.755     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                    ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 3.685     ; 4.053     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 3.886     ; 4.254     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 3.685     ; 4.053     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 3.832     ; 4.200     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                      ;
+-----------+-----------------+---------------------------------------------------+------+
; Fmax      ; Restricted Fmax ; Clock Name                                        ; Note ;
+-----------+-----------------+---------------------------------------------------+------+
; 64.79 MHz ; 64.79 MHz       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+-----------+-----------------+---------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                        ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; Slack ; End Point TNS ;
+---------------------------------------------------+-------+---------------+
; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.616 ; 0.000         ;
+---------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                         ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; Slack ; End Point TNS ;
+---------------------------------------------------+-------+---------------+
; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.349 ; 0.000         ;
+---------------------------------------------------+-------+---------------+


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+---------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                          ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; Slack ; End Point TNS ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; 4.763 ; 0.000         ;
; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.053 ; 0.000         ;
+---------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                ;
+-------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                             ; To Node                       ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; 0.616 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.306      ;
; 0.616 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.306      ;
; 0.616 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.306      ;
; 0.616 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.306      ;
; 0.616 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.306      ;
; 0.616 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.306      ;
; 0.616 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.306      ;
; 0.640 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.281      ;
; 0.640 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.281      ;
; 0.640 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.281      ;
; 0.640 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.281      ;
; 0.640 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.281      ;
; 0.640 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.281      ;
; 0.640 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.281      ;
; 0.658 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.409     ; 7.265      ;
; 0.658 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.409     ; 7.265      ;
; 0.658 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.409     ; 7.265      ;
; 0.670 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.255      ;
; 0.670 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.255      ;
; 0.670 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.255      ;
; 0.670 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.255      ;
; 0.670 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.255      ;
; 0.670 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.255      ;
; 0.670 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.255      ;
; 0.675 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.261      ;
; 0.675 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.261      ;
; 0.675 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.261      ;
; 0.692 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.416     ; 7.224      ;
; 0.692 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.416     ; 7.224      ;
; 0.692 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.416     ; 7.224      ;
; 0.692 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.416     ; 7.224      ;
; 0.692 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.416     ; 7.224      ;
; 0.692 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.416     ; 7.224      ;
; 0.692 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.416     ; 7.224      ;
; 0.701 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.392     ; 7.239      ;
; 0.701 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.392     ; 7.239      ;
; 0.701 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.392     ; 7.239      ;
; 0.714 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.208      ;
; 0.714 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.208      ;
; 0.714 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.208      ;
; 0.714 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.208      ;
; 0.714 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.208      ;
; 0.714 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.208      ;
; 0.714 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.208      ;
; 0.717 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.219      ;
; 0.717 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.219      ;
; 0.717 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.219      ;
; 0.717 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.219      ;
; 0.717 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.219      ;
; 0.717 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.219      ;
; 0.717 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.219      ;
; 0.754 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.397     ; 7.181      ;
; 0.754 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.397     ; 7.181      ;
; 0.754 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.397     ; 7.181      ;
; 0.768 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.401     ; 7.163      ;
; 0.768 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.401     ; 7.163      ;
; 0.768 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.401     ; 7.163      ;
; 0.776 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.160      ;
; 0.776 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.160      ;
; 0.776 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.160      ;
; 0.786 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.136      ;
; 0.786 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.136      ;
; 0.786 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.410     ; 7.136      ;
; 0.803 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.133      ;
; 0.803 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.133      ;
; 0.803 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.133      ;
; 0.804 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.393     ; 7.135      ;
; 0.804 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.393     ; 7.135      ;
; 0.804 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.393     ; 7.135      ;
; 0.829 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.107      ;
; 0.829 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.107      ;
; 0.829 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.107      ;
; 0.832 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.104      ;
; 0.832 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.104      ;
; 0.832 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.396     ; 7.104      ;
; 0.840 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.085      ;
; 0.840 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.085      ;
; 0.840 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.085      ;
; 0.840 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.085      ;
; 0.840 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.085      ;
; 0.840 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.085      ;
; 0.840 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.407     ; 7.085      ;
; 0.841 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.395     ; 7.096      ;
; 0.841 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.395     ; 7.096      ;
; 0.841 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.395     ; 7.096      ;
; 0.841 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.395     ; 7.096      ;
; 0.841 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.395     ; 7.096      ;
; 0.841 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.395     ; 7.096      ;
; 0.841 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.395     ; 7.096      ;
; 0.843 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.078      ;
; 0.843 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.078      ;
; 0.843 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.411     ; 7.078      ;
; 0.846 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.401     ; 7.085      ;
; 0.846 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.401     ; 7.085      ;
; 0.846 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.401     ; 7.085      ;
; 0.855 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.409     ; 7.068      ;
; 0.855 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.409     ; 7.068      ;
; 0.855 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.409     ; 7.068      ;
; 0.855 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.409     ; 7.068      ;
; 0.855 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.409     ; 7.068      ;
+-------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                         ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                               ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; 0.349 ; uberDDS:oneandonly|IOupdateRun        ; uberDDS:oneandonly|IOupdateRun        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.597      ;
; 0.362 ; uberDDS:oneandonly|CmdSeqFull         ; uberDDS:oneandonly|CmdSeqFull         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|RunSequence        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; uberDDS:oneandonly|CmdSeqWrite        ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.404 ; DoubleBuffer8:inst3|D55               ; DoubleBuffer8:inst3|Q5                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.639      ;
; 0.406 ; DoubleBuffer8:inst3|D22               ; DoubleBuffer8:inst3|Q2                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.641      ;
; 0.418 ; uberDDS:oneandonly|LastrCS            ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.653      ;
; 0.421 ; uberDDS:oneandonly|BitMask[6]         ; uberDDS:oneandonly|BitMask[5]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.656      ;
; 0.425 ; uberDDS:oneandonly|BitMask[1]         ; uberDDS:oneandonly|BitMask[0]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.660      ;
; 0.431 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|BitMask[4]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.666      ;
; 0.431 ; uberDDS:oneandonly|BitMask[3]         ; uberDDS:oneandonly|BitMask[2]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.666      ;
; 0.545 ; uberDDS:oneandonly|BitMask[2]         ; uberDDS:oneandonly|BitMask[1]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.780      ;
; 0.570 ; uberDDS:oneandonly|BitMask[4]         ; uberDDS:oneandonly|BitMask[3]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.805      ;
; 0.606 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.841      ;
; 0.607 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.842      ;
; 0.607 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.842      ;
; 0.608 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.843      ;
; 0.608 ; uberDDS:oneandonly|State.CLOCK_HIGH   ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.843      ;
; 0.609 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.844      ;
; 0.611 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.846      ;
; 0.611 ; uberDDS:oneandonly|State.CLOCK_HIGH   ; uberDDS:oneandonly|State.CLOCK_LOW    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.846      ;
; 0.612 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.847      ;
; 0.612 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.847      ;
; 0.612 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.847      ;
; 0.614 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.849      ;
; 0.629 ; uberDDS:oneandonly|CmdSeqAdr[14]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.864      ;
; 0.630 ; uberDDS:oneandonly|CmdSeqAdr[13]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.865      ;
; 0.632 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[0]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.867      ;
; 0.658 ; uberDDS:oneandonly|CmdSeqFull         ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.893      ;
; 0.752 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[1]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.394      ; 1.317      ;
; 0.753 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[6]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.394      ; 1.318      ;
; 0.760 ; uberDDS:oneandonly|BitMask[0]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.439      ; 1.370      ;
; 0.762 ; uberDDS:oneandonly|State.CLOCK_LOW    ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.443      ; 1.376      ;
; 0.763 ; uberDDS:oneandonly|CmdSeqAdr[1]       ; uberDDS:oneandonly|CmdSeqAdr[1]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.998      ;
; 0.766 ; uberDDS:oneandonly|CmdSeqAdr[3]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.001      ;
; 0.770 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.439      ; 1.380      ;
; 0.892 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.127      ;
; 0.895 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.130      ;
; 0.895 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.130      ;
; 0.896 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.131      ;
; 0.897 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.132      ;
; 0.898 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.133      ;
; 0.899 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.134      ;
; 0.899 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.134      ;
; 0.899 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[1]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.134      ;
; 0.900 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.135      ;
; 0.902 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.137      ;
; 0.906 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.141      ;
; 0.906 ; uberDDS:oneandonly|BitMask[3]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.439      ; 1.516      ;
; 0.906 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.141      ;
; 0.907 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.142      ;
; 0.908 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.143      ;
; 0.910 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.145      ;
; 0.911 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.146      ;
; 0.912 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.443      ; 1.526      ;
; 0.913 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.148      ;
; 0.917 ; uberDDS:oneandonly|CmdSeqAdr[13]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.152      ;
; 0.927 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.CLOCK_HIGH   ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 1.157      ;
; 0.928 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 1.158      ;
; 0.931 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.CLOCK_LOW    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 1.161      ;
; 0.960 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[5]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.394      ; 1.525      ;
; 0.964 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[7]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.394      ; 1.529      ;
; 0.979 ; uberDDS:oneandonly|Rst                ; uberDDS:oneandonly|Rst                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.214      ;
; 0.979 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.438      ; 1.588      ;
; 0.987 ; uberDDS:oneandonly|State.CLOCK_LOW    ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.447      ; 1.605      ;
; 0.991 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.226      ;
; 0.997 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.232      ;
; 0.998 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.233      ;
; 0.998 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.233      ;
; 1.002 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.237      ;
; 1.003 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.START_CMDS   ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.236      ;
; 1.005 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.240      ;
; 1.005 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.240      ;
; 1.007 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.242      ;
; 1.008 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.243      ;
; 1.009 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.244      ;
; 1.009 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.244      ;
; 1.009 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.244      ;
; 1.010 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.245      ;
; 1.012 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.247      ;
; 1.015 ; uberDDS:oneandonly|BitMask[2]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.439      ; 1.625      ;
; 1.016 ; uberDDS:oneandonly|State.START_CMDS   ; uberDDS:oneandonly|Rst                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.251      ;
; 1.016 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.251      ;
; 1.016 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.251      ;
; 1.018 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.253      ;
; 1.019 ; uberDDS:oneandonly|State.START_CMDS   ; uberDDS:oneandonly|TrigDirect         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.254      ;
; 1.020 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.255      ;
; 1.021 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.256      ;
; 1.022 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|State.NOT_A_REG    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.444      ; 1.637      ;
; 1.023 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.258      ;
; 1.027 ; uberDDS:oneandonly|State.FINISHED_CMD ; uberDDS:oneandonly|State.FINISHED_CMD ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.262      ;
; 1.033 ; uberDDS:oneandonly|BitMask[6]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.439      ; 1.643      ;
; 1.038 ; uberDDS:oneandonly|BitMask[0]         ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.443      ; 1.652      ;
; 1.049 ; uberDDS:oneandonly|CmdSeqAdr[1]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.284      ;
; 1.052 ; uberDDS:oneandonly|CmdSeqAdr[3]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.287      ;
; 1.067 ; uberDDS:oneandonly|BitMask[1]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.439      ; 1.677      ;
; 1.073 ; uberDDS:oneandonly|DRhold             ; uberDDS:oneandonly|DRhold             ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.307      ;
; 1.084 ; uberDDS:oneandonly|Sclk               ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.319      ;
; 1.086 ; uberDDS:oneandonly|SDio               ; uberDDS:oneandonly|SDio               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.321      ;
; 1.089 ; uberDDS:oneandonly|State.START_CMDS   ; uberDDS:oneandonly|State.CMD_SIZE     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.324      ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'Clock'                                                                                           ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                      ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+
; 4.763 ; 4.763        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0]           ;
; 4.763 ; 4.763        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|observablevcoout ;
; 4.811 ; 4.811        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; Clk~input|o                                                 ;
; 4.828 ; 4.828        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.000 ; 5.000        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; Clk~input|i                                                 ;
; 5.000 ; 5.000        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; Clk~input|i                                                 ;
; 5.172 ; 5.172        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.189 ; 5.189        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; Clk~input|o                                                 ;
; 5.235 ; 5.235        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0]           ;
; 5.235 ; 5.235        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|observablevcoout ;
; 6.000 ; 10.000       ; 4.000          ; Port Rate        ; Clock ; Rise       ; Clk                                                         ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                          ;
+-------+--------------+----------------+-----------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                             ; Clock Edge ; Target                                                                                                      ;
+-------+--------------+----------------+-----------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_address_reg0 ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_re_reg       ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_we_reg       ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_address_reg0 ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg       ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_we_reg       ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_address_reg0 ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg       ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_we_reg       ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg        ;
; 8.053 ; 8.286        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_datain_reg0  ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_datain_reg0  ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_datain_reg0  ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_address_reg0 ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg       ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_we_reg       ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_address_reg0 ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_re_reg       ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_we_reg       ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_re_reg        ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_address_reg0  ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg        ;
; 8.054 ; 8.287        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_we_reg        ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg        ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_datain_reg0  ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_address_reg0 ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_re_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_we_reg       ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg        ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_datain_reg0  ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_address_reg0  ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg        ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_we_reg        ;
; 8.055 ; 8.288        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_datain_reg0   ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_address_reg0 ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_we_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_address_reg0 ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_we_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_address_reg0 ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_we_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_address_reg0 ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_re_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_we_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_datain_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_address_reg0 ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_re_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_we_reg       ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.056 ; 8.289        ; 0.233          ; Low Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg        ;
+-------+--------------+----------------+-----------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                             ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; DRover    ; Clock      ; 4.612 ; 5.031 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Trigger   ; Clock      ; 4.438 ; 4.849 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCS       ; Clock      ; 3.828 ; 4.102 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; 4.856 ; 5.212 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 3.787 ; 4.215 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.336 ; 4.756 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 4.467 ; 4.879 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; 3.823 ; 4.116 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4] ; Clock      ; 4.264 ; 4.634 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; 4.856 ; 5.212 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; 4.564 ; 4.906 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7] ; Clock      ; 3.719 ; 4.087 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCmd[*]   ; Clock      ; 6.942 ; 7.317 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[0]  ; Clock      ; 6.495 ; 6.892 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[1]  ; Clock      ; 6.154 ; 6.554 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[2]  ; Clock      ; 6.316 ; 6.724 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[3]  ; Clock      ; 6.942 ; 7.317 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; 5.528 ; 5.882 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 5.528 ; 5.882 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 5.282 ; 5.649 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 5.096 ; 5.522 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; 5.522 ; 5.836 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; 4.759 ; 5.119 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; 5.290 ; 5.650 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+
; DRover    ; Clock      ; -3.936 ; -4.339 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Trigger   ; Clock      ; -3.769 ; -4.165 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCS       ; Clock      ; -3.190 ; -3.447 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; -2.699 ; -3.030 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; -2.699 ; -3.030 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; -2.991 ; -3.365 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; -3.384 ; -3.799 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; -2.783 ; -3.083 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4] ; Clock      ; -3.077 ; -3.478 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; -3.023 ; -3.409 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; -3.280 ; -3.636 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7] ; Clock      ; -2.760 ; -3.146 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCmd[*]   ; Clock      ; -3.272 ; -3.577 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[0]  ; Clock      ; -4.043 ; -4.295 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[1]  ; Clock      ; -3.743 ; -4.050 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[2]  ; Clock      ; -3.272 ; -3.577 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[3]  ; Clock      ; -3.810 ; -4.163 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; -3.619 ; -3.971 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; -4.398 ; -4.751 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; -4.580 ; -4.932 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; -4.375 ; -4.786 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; -4.106 ; -4.373 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; -3.619 ; -3.971 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; -4.070 ; -4.412 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                    ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Q2         ; Clock      ; 4.463 ; 4.398 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; CmdSeqFull ; Clock      ; 4.676 ; 4.597 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRctl      ; Clock      ; 5.194 ; 5.098 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRhold     ; Clock      ; 5.495 ; 5.393 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOrst      ; Clock      ; 4.483 ; 4.487 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOupdate   ; Clock      ; 6.329 ; 6.292 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q1         ; Clock      ; 5.419 ; 5.352 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q3         ; Clock      ; 8.542 ; 8.768 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Rst        ; Clock      ; 4.152 ; 4.140 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; SDio       ; Clock      ; 4.423 ; 4.372 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Sclk       ; Clock      ; 4.840 ; 4.870 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]   ; Clock      ; 6.329 ; 6.081 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3]  ; Clock      ; 3.644 ; 3.720 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4]  ; Clock      ; 3.428 ; 3.467 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5]  ; Clock      ; 3.401 ; 3.434 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6]  ; Clock      ; 6.329 ; 6.081 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7]  ; Clock      ; 3.896 ; 3.980 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+------------+------------+-------+-------+------------+---------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                            ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Q2         ; Clock      ; 4.058 ; 3.995 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; CmdSeqFull ; Clock      ; 4.262 ; 4.186 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRctl      ; Clock      ; 4.755 ; 4.662 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRhold     ; Clock      ; 5.044 ; 4.946 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOrst      ; Clock      ; 4.073 ; 4.076 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOupdate   ; Clock      ; 5.270 ; 5.152 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q1         ; Clock      ; 4.969 ; 4.904 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q3         ; Clock      ; 7.498 ; 7.643 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Rst        ; Clock      ; 3.754 ; 3.741 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; SDio       ; Clock      ; 4.014 ; 3.965 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Sclk       ; Clock      ; 4.414 ; 4.442 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]   ; Clock      ; 3.032 ; 3.064 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3]  ; Clock      ; 3.265 ; 3.339 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4]  ; Clock      ; 3.058 ; 3.097 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5]  ; Clock      ; 3.032 ; 3.064 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6]  ; Clock      ; 5.958 ; 5.711 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7]  ; Clock      ; 3.507 ; 3.589 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+------------+------------+-------+-------+------------+---------------------------------------------------+


+------------------------------------------------------+
; Propagation Delay                                    ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Trigger    ; IOupdate    ; 8.454  ;    ;    ; 8.760  ;
; Trigger    ; Q3          ; 10.667 ;    ;    ; 11.236 ;
+------------+-------------+--------+----+----+--------+


+------------------------------------------------------+
; Minimum Propagation Delay                            ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Trigger    ; IOupdate    ; 8.225  ;    ;    ; 8.527  ;
; Trigger    ; Q3          ; 10.453 ;    ;    ; 11.018 ;
+------------+-------------+--------+----+----+--------+


+---------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                     ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 4.513 ; 4.134 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 4.735 ; 4.356 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.513 ; 4.134 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 4.733 ; 4.354 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                             ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 4.017 ; 3.653 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 4.230 ; 3.866 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.017 ; 3.653 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 4.228 ; 3.864 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                            ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 4.123     ; 4.502     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 4.306     ; 4.685     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.123     ; 4.502     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 4.262     ; 4.641     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                    ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 3.642     ; 4.006     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 3.818     ; 4.182     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 3.642     ; 4.006     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 3.776     ; 4.140     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                        ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; Slack ; End Point TNS ;
+---------------------------------------------------+-------+---------------+
; inst2|altpll_component|auto_generated|pll1|clk[0] ; 4.433 ; 0.000         ;
+---------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                         ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; Slack ; End Point TNS ;
+---------------------------------------------------+-------+---------------+
; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.177 ; 0.000         ;
+---------------------------------------------------+-------+---------------+


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+---------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                          ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; Slack ; End Point TNS ;
+---------------------------------------------------+-------+---------------+
; Clock                                             ; 4.422 ; 0.000         ;
; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.065 ; 0.000         ;
+---------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                ;
+-------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                             ; To Node                       ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; 4.433 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.689      ;
; 4.433 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.689      ;
; 4.433 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.689      ;
; 4.455 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.668      ;
; 4.455 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.668      ;
; 4.455 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.668      ;
; 4.455 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.668      ;
; 4.455 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.668      ;
; 4.455 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.668      ;
; 4.455 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.668      ;
; 4.460 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.663      ;
; 4.460 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.663      ;
; 4.460 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.663      ;
; 4.460 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.663      ;
; 4.460 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.663      ;
; 4.460 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.663      ;
; 4.460 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.663      ;
; 4.474 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.645      ;
; 4.474 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.645      ;
; 4.474 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.645      ;
; 4.474 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.645      ;
; 4.474 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.645      ;
; 4.474 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.645      ;
; 4.474 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.645      ;
; 4.488 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.637      ;
; 4.488 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.637      ;
; 4.488 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.637      ;
; 4.488 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.637      ;
; 4.488 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.637      ;
; 4.488 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.637      ;
; 4.488 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.637      ;
; 4.493 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.199     ; 3.628      ;
; 4.493 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.199     ; 3.628      ;
; 4.493 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.199     ; 3.628      ;
; 4.500 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.629      ;
; 4.500 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.629      ;
; 4.500 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.629      ;
; 4.505 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.618      ;
; 4.505 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.618      ;
; 4.505 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.618      ;
; 4.505 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.618      ;
; 4.505 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.618      ;
; 4.505 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.618      ;
; 4.505 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.618      ;
; 4.507 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.612      ;
; 4.507 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.612      ;
; 4.507 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.201     ; 3.612      ;
; 4.516 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.609      ;
; 4.516 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.609      ;
; 4.516 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.195     ; 3.609      ;
; 4.533 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.585      ;
; 4.533 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.585      ;
; 4.533 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.585      ;
; 4.533 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.585      ;
; 4.533 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.585      ;
; 4.533 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.585      ;
; 4.533 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.585      ;
; 4.535 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.194     ; 3.591      ;
; 4.535 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.194     ; 3.591      ;
; 4.535 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.194     ; 3.591      ;
; 4.535 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.194     ; 3.591      ;
; 4.535 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.194     ; 3.591      ;
; 4.535 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.194     ; 3.591      ;
; 4.535 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.194     ; 3.591      ;
; 4.540 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.578      ;
; 4.540 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.578      ;
; 4.540 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.578      ;
; 4.540 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.578      ;
; 4.540 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.578      ;
; 4.540 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.578      ;
; 4.540 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.578      ;
; 4.544 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.189     ; 3.587      ;
; 4.544 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.189     ; 3.587      ;
; 4.544 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.189     ; 3.587      ;
; 4.544 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.189     ; 3.587      ;
; 4.544 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.189     ; 3.587      ;
; 4.544 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.189     ; 3.587      ;
; 4.544 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a7~porta_re_reg  ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.189     ; 3.587      ;
; 4.553 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.569      ;
; 4.553 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.569      ;
; 4.553 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.569      ;
; 4.555 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.574      ;
; 4.555 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.574      ;
; 4.555 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.574      ;
; 4.558 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.564      ;
; 4.558 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.564      ;
; 4.558 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg  ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.198     ; 3.564      ;
; 4.564 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg ; uberDDS:oneandonly|BitMask[6] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.559      ;
; 4.564 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg ; uberDDS:oneandonly|BitMask[5] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.559      ;
; 4.564 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg ; uberDDS:oneandonly|BitMask[4] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.559      ;
; 4.564 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg ; uberDDS:oneandonly|BitMask[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.559      ;
; 4.564 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg ; uberDDS:oneandonly|BitMask[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.559      ;
; 4.564 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg ; uberDDS:oneandonly|BitMask[1] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.559      ;
; 4.564 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg ; uberDDS:oneandonly|BitMask[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.197     ; 3.559      ;
; 4.565 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.564      ;
; 4.565 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.564      ;
; 4.565 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.191     ; 3.564      ;
; 4.572 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|ByteCtr[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.546      ;
; 4.572 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|ByteCtr[2] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.546      ;
; 4.572 ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg ; uberDDS:oneandonly|ByteCtr[3] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 8.333        ; -0.202     ; 3.546      ;
+-------+-------------------------------------------------------------------------------------------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                         ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                               ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; 0.177 ; uberDDS:oneandonly|IOupdateRun        ; uberDDS:oneandonly|IOupdateRun        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 0.307      ;
; 0.184 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|RunSequence        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.185 ; uberDDS:oneandonly|CmdSeqFull         ; uberDDS:oneandonly|CmdSeqFull         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; uberDDS:oneandonly|CmdSeqWrite        ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.194 ; DoubleBuffer8:inst3|D55               ; DoubleBuffer8:inst3|Q5                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.196 ; DoubleBuffer8:inst3|D22               ; DoubleBuffer8:inst3|Q2                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
; 0.201 ; uberDDS:oneandonly|LastrCS            ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.323      ;
; 0.204 ; uberDDS:oneandonly|BitMask[1]         ; uberDDS:oneandonly|BitMask[0]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.326      ;
; 0.205 ; uberDDS:oneandonly|BitMask[6]         ; uberDDS:oneandonly|BitMask[5]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.327      ;
; 0.208 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|BitMask[4]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.330      ;
; 0.208 ; uberDDS:oneandonly|BitMask[3]         ; uberDDS:oneandonly|BitMask[2]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.330      ;
; 0.268 ; uberDDS:oneandonly|BitMask[4]         ; uberDDS:oneandonly|BitMask[3]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.390      ;
; 0.269 ; uberDDS:oneandonly|BitMask[2]         ; uberDDS:oneandonly|BitMask[1]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.391      ;
; 0.302 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.425      ;
; 0.302 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.425      ;
; 0.302 ; uberDDS:oneandonly|State.CLOCK_HIGH   ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.425      ;
; 0.303 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.426      ;
; 0.303 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.426      ;
; 0.303 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.426      ;
; 0.303 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.426      ;
; 0.303 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.426      ;
; 0.304 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.427      ;
; 0.304 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.427      ;
; 0.304 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.427      ;
; 0.305 ; uberDDS:oneandonly|State.CLOCK_HIGH   ; uberDDS:oneandonly|State.CLOCK_LOW    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.428      ;
; 0.314 ; uberDDS:oneandonly|CmdSeqAdr[13]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.437      ;
; 0.314 ; uberDDS:oneandonly|CmdSeqAdr[14]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.437      ;
; 0.314 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[0]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.437      ;
; 0.327 ; uberDDS:oneandonly|BitMask[0]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.261      ; 0.672      ;
; 0.332 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.261      ; 0.677      ;
; 0.335 ; uberDDS:oneandonly|CmdSeqFull         ; uberDDS:oneandonly|CmdSeqWrite        ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.457      ;
; 0.355 ; uberDDS:oneandonly|State.CLOCK_LOW    ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.263      ; 0.702      ;
; 0.357 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[1]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.234      ; 0.675      ;
; 0.357 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[6]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.234      ; 0.675      ;
; 0.367 ; uberDDS:oneandonly|CmdSeqAdr[1]       ; uberDDS:oneandonly|CmdSeqAdr[1]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.490      ;
; 0.369 ; uberDDS:oneandonly|CmdSeqAdr[3]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.492      ;
; 0.396 ; uberDDS:oneandonly|BitMask[3]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.261      ; 0.741      ;
; 0.423 ; uberDDS:oneandonly|BitMask[5]         ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.264      ; 0.771      ;
; 0.451 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.574      ;
; 0.452 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.575      ;
; 0.452 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.575      ;
; 0.453 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.576      ;
; 0.460 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.583      ;
; 0.460 ; uberDDS:oneandonly|BitMask[2]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.261      ; 0.805      ;
; 0.461 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.584      ;
; 0.461 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.584      ;
; 0.461 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[1]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.584      ;
; 0.461 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.584      ;
; 0.462 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.585      ;
; 0.462 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.585      ;
; 0.463 ; uberDDS:oneandonly|CmdSeqAdr[13]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.586      ;
; 0.463 ; uberDDS:oneandonly|CmdSeqAdr[12]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.586      ;
; 0.464 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.587      ;
; 0.464 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.587      ;
; 0.464 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.587      ;
; 0.464 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.587      ;
; 0.465 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.588      ;
; 0.465 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.588      ;
; 0.467 ; uberDDS:oneandonly|BitMask[6]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.261      ; 0.812      ;
; 0.469 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.CLOCK_HIGH   ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.588      ;
; 0.470 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[5]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.234      ; 0.788      ;
; 0.472 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.591      ;
; 0.473 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|ByteCtr[7]         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.234      ; 0.791      ;
; 0.473 ; uberDDS:oneandonly|State.CLOCK_LOW    ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.266      ; 0.823      ;
; 0.475 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.CLOCK_LOW    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.594      ;
; 0.482 ; uberDDS:oneandonly|BitMask[1]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.261      ; 0.827      ;
; 0.483 ; uberDDS:oneandonly|Rst                ; uberDDS:oneandonly|Rst                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.606      ;
; 0.487 ; uberDDS:oneandonly|BitMask[0]         ; uberDDS:oneandonly|State.NEXT_BIT     ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.264      ; 0.835      ;
; 0.488 ; uberDDS:oneandonly|State.FINISHED_CMD ; uberDDS:oneandonly|State.FINISHED_CMD ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.611      ;
; 0.492 ; uberDDS:oneandonly|State.START_CMDS   ; uberDDS:oneandonly|Rst                ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.615      ;
; 0.494 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.259      ; 0.837      ;
; 0.495 ; uberDDS:oneandonly|RunSequence        ; uberDDS:oneandonly|State.START_CMDS   ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.615      ;
; 0.496 ; uberDDS:oneandonly|State.START_CMDS   ; uberDDS:oneandonly|TrigDirect         ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.619      ;
; 0.499 ; uberDDS:oneandonly|State.CMD_SIZE     ; uberDDS:oneandonly|State.NOT_A_REG    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.265      ; 0.848      ;
; 0.514 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.637      ;
; 0.515 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.638      ;
; 0.515 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.638      ;
; 0.516 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.639      ;
; 0.516 ; uberDDS:oneandonly|CmdSeqAdr[1]       ; uberDDS:oneandonly|CmdSeqAdr[2]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.639      ;
; 0.517 ; uberDDS:oneandonly|CmdSeqAdr[5]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.640      ;
; 0.518 ; uberDDS:oneandonly|CmdSeqAdr[11]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.641      ;
; 0.518 ; uberDDS:oneandonly|CmdSeqAdr[3]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.641      ;
; 0.518 ; uberDDS:oneandonly|CmdSeqAdr[7]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.641      ;
; 0.519 ; uberDDS:oneandonly|CmdSeqAdr[9]       ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.642      ;
; 0.527 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[5]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.650      ;
; 0.527 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[3]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.650      ;
; 0.527 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[7]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.650      ;
; 0.527 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[13]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.650      ;
; 0.528 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[9]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.651      ;
; 0.528 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[11]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.651      ;
; 0.530 ; uberDDS:oneandonly|CmdSeqAdr[0]       ; uberDDS:oneandonly|CmdSeqAdr[4]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.653      ;
; 0.530 ; uberDDS:oneandonly|CmdSeqAdr[2]       ; uberDDS:oneandonly|CmdSeqAdr[6]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.653      ;
; 0.530 ; uberDDS:oneandonly|CmdSeqAdr[4]       ; uberDDS:oneandonly|CmdSeqAdr[8]       ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.653      ;
; 0.530 ; uberDDS:oneandonly|CmdSeqAdr[10]      ; uberDDS:oneandonly|CmdSeqAdr[14]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.653      ;
; 0.531 ; uberDDS:oneandonly|DRhold             ; uberDDS:oneandonly|DRhold             ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.654      ;
; 0.531 ; uberDDS:oneandonly|BitMask[4]         ; uberDDS:oneandonly|State.NEXT_BYTE    ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.261      ; 0.876      ;
; 0.531 ; uberDDS:oneandonly|CmdSeqAdr[6]       ; uberDDS:oneandonly|CmdSeqAdr[10]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.654      ;
; 0.531 ; uberDDS:oneandonly|CmdSeqAdr[8]       ; uberDDS:oneandonly|CmdSeqAdr[12]      ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.654      ;
; 0.537 ; uberDDS:oneandonly|Sclk               ; uberDDS:oneandonly|Sclk               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.660      ;
; 0.542 ; uberDDS:oneandonly|SDio               ; uberDDS:oneandonly|SDio               ; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.664      ;
+-------+---------------------------------------+---------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'Clock'                                                                                           ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                      ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+
; 4.422 ; 4.422        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0]           ;
; 4.422 ; 4.422        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|observablevcoout ;
; 4.447 ; 4.447        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; Clk~input|o                                                 ;
; 4.449 ; 4.449        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.000 ; 5.000        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; Clk~input|i                                                 ;
; 5.000 ; 5.000        ; 0.000          ; Low Pulse Width  ; Clock ; Rise       ; Clk~input|i                                                 ;
; 5.550 ; 5.550        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.553 ; 5.553        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; Clk~input|o                                                 ;
; 5.577 ; 5.577        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0]           ;
; 5.577 ; 5.577        ; 0.000          ; High Pulse Width ; Clock ; Rise       ; inst2|altpll_component|auto_generated|pll1|observablevcoout ;
; 6.000 ; 10.000       ; 4.000          ; Port Rate        ; Clock ; Rise       ; Clk                                                         ;
+-------+--------------+----------------+------------------+-------+------------+-------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'inst2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                           ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                             ; Clock Edge ; Target                                                                                                      ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; 8.065 ; 8.295        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_address_reg0 ;
; 8.065 ; 8.295        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_re_reg       ;
; 8.065 ; 8.295        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_we_reg       ;
; 8.065 ; 8.295        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a27~porta_address_reg0 ;
; 8.065 ; 8.295        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a27~porta_re_reg       ;
; 8.065 ; 8.295        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a27~porta_we_reg       ;
; 8.065 ; 8.281        ; 0.216          ; High Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; uberDDS:oneandonly|State.HDWR_PIN                                                                           ;
; 8.065 ; 8.281        ; 0.216          ; High Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; uberDDS:oneandonly|State.NEXT_BIT                                                                           ;
; 8.065 ; 8.281        ; 0.216          ; High Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; uberDDS:oneandonly|State.NOT_A_REG                                                                          ;
; 8.065 ; 8.281        ; 0.216          ; High Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; uberDDS:oneandonly|State.RESTART_CMD_SEQ                                                                    ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_re_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_address_reg0 ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_re_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a11~porta_we_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_address_reg0 ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_re_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a12~porta_we_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_address_reg0 ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_re_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a13~porta_we_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_address_reg0 ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_re_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a17~porta_we_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_address_reg0 ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_re_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a21~porta_we_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_address_reg0 ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_re_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a22~porta_we_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_address_reg0 ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_re_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a24~porta_we_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_address_reg0 ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_re_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a26~porta_we_reg       ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_re_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_address_reg0  ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_re_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a5~porta_we_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_address_reg0  ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_re_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a6~porta_we_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_address_reg0  ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_re_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a8~porta_we_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_address_reg0  ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_re_reg        ;
; 8.066 ; 8.296        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a9~porta_we_reg        ;
; 8.066 ; 8.282        ; 0.216          ; High Pulse Width ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; uberDDS:oneandonly|State.NEXT_BYTE                                                                          ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a10~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a14~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a15~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a16~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a18~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a19~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_re_reg        ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a20~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a23~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a25~porta_datain_reg0  ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a27~porta_datain_reg0  ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a28~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a29~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_re_reg        ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a30~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_address_reg0 ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_re_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a31~porta_we_reg       ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_re_reg        ;
; 8.067 ; 8.297        ; 0.230          ; Low Pulse Width  ; inst2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_dq:inst|altsyncram:altsyncram_component|altsyncram_q5f1:auto_generated|ram_block1a4~porta_we_reg        ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                             ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; DRover    ; Clock      ; 2.806 ; 3.646 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Trigger   ; Clock      ; 2.692 ; 3.551 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCS       ; Clock      ; 2.309 ; 3.057 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; 2.916 ; 3.818 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 2.355 ; 3.200 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 2.669 ; 3.518 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 2.712 ; 3.632 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; 2.329 ; 3.129 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4] ; Clock      ; 2.603 ; 3.458 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; 2.916 ; 3.818 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; 2.749 ; 3.628 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7] ; Clock      ; 2.316 ; 3.134 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCmd[*]   ; Clock      ; 4.012 ; 4.689 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[0]  ; Clock      ; 3.771 ; 4.494 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[1]  ; Clock      ; 3.589 ; 4.305 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[2]  ; Clock      ; 3.682 ; 4.407 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[3]  ; Clock      ; 4.012 ; 4.689 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; 3.184 ; 4.091 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 3.184 ; 4.091 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 3.074 ; 3.951 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 2.980 ; 3.869 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; 3.147 ; 3.991 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; 2.775 ; 3.614 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; 3.035 ; 3.926 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+
; DRover    ; Clock      ; -2.425 ; -3.246 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Trigger   ; Clock      ; -2.316 ; -3.155 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCS       ; Clock      ; -1.945 ; -2.679 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; -1.720 ; -2.469 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; -1.720 ; -2.469 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; -1.866 ; -2.678 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; -2.120 ; -2.960 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; -1.739 ; -2.495 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4] ; Clock      ; -1.934 ; -2.761 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; -1.907 ; -2.717 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; -2.008 ; -2.838 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7] ; Clock      ; -1.759 ; -2.560 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCmd[*]   ; Clock      ; -1.974 ; -2.725 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[0]  ; Clock      ; -2.346 ; -3.119 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[1]  ; Clock      ; -2.226 ; -2.946 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[2]  ; Clock      ; -1.974 ; -2.725 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[3]  ; Clock      ; -2.277 ; -3.000 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; -2.162 ; -2.959 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; -2.569 ; -3.419 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; -2.675 ; -3.533 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; -2.577 ; -3.456 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; -2.396 ; -3.196 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; -2.162 ; -2.959 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; -2.379 ; -3.223 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                    ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Q2         ; Clock      ; 2.277 ; 2.454 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; CmdSeqFull ; Clock      ; 2.447 ; 2.651 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRctl      ; Clock      ; 2.749 ; 2.917 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRhold     ; Clock      ; 2.927 ; 3.109 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOrst      ; Clock      ; 2.390 ; 2.532 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOupdate   ; Clock      ; 3.439 ; 3.532 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q1         ; Clock      ; 2.904 ; 3.091 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q3         ; Clock      ; 4.992 ; 5.336 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Rst        ; Clock      ; 2.198 ; 2.324 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; SDio       ; Clock      ; 2.320 ; 2.453 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Sclk       ; Clock      ; 2.590 ; 2.764 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]   ; Clock      ; 3.950 ; 3.606 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3]  ; Clock      ; 2.014 ; 1.940 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4]  ; Clock      ; 1.889 ; 1.824 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5]  ; Clock      ; 1.870 ; 1.808 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6]  ; Clock      ; 3.950 ; 3.606 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7]  ; Clock      ; 2.160 ; 2.084 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+------------+------------+-------+-------+------------+---------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                            ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Q2         ; Clock      ; 2.042 ; 2.215 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; CmdSeqFull ; Clock      ; 2.203 ; 2.402 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRctl      ; Clock      ; 2.490 ; 2.651 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRhold     ; Clock      ; 2.661 ; 2.836 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOrst      ; Clock      ; 2.145 ; 2.281 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOupdate   ; Clock      ; 2.710 ; 2.893 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q1         ; Clock      ; 2.638 ; 2.818 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q3         ; Clock      ; 4.271 ; 4.708 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Rst        ; Clock      ; 1.961 ; 2.082 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; SDio       ; Clock      ; 2.079 ; 2.207 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Sclk       ; Clock      ; 2.337 ; 2.504 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]   ; Clock      ; 1.646 ; 1.587 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3]  ; Clock      ; 1.784 ; 1.713 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4]  ; Clock      ; 1.665 ; 1.601 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5]  ; Clock      ; 1.646 ; 1.587 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6]  ; Clock      ; 3.725 ; 3.384 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7]  ; Clock      ; 1.925 ; 1.852 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+------------+------------+-------+-------+------------+---------------------------------------------------+


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+-------+----+----+-------+
; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
+------------+-------------+-------+----+----+-------+
; Trigger    ; IOupdate    ; 4.742 ;    ;    ; 5.713 ;
; Trigger    ; Q3          ; 6.295 ;    ;    ; 7.517 ;
+------------+-------------+-------+----+----+-------+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+-------+----+----+-------+
; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
+------------+-------------+-------+----+----+-------+
; Trigger    ; IOupdate    ; 4.616 ;    ;    ; 5.570 ;
; Trigger    ; Q3          ; 6.177 ;    ;    ; 7.385 ;
+------------+-------------+-------+----+----+-------+


+---------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                     ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 3.412 ; 3.036 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 3.502 ; 3.126 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 3.412 ; 3.036 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 3.517 ; 3.141 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                             ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 3.077 ; 2.716 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 3.163 ; 2.802 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 3.077 ; 2.716 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 3.177 ; 2.816 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                            ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 3.139     ; 3.515     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 3.244     ; 3.620     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 3.139     ; 3.515     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 3.252     ; 3.628     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                    ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+
; rData[*]  ; Clock      ; 2.815     ; 3.176     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 2.915     ; 3.276     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 2.815     ; 3.176     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 2.923     ; 3.284     ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-----------+-----------+------------+---------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                            ;
+----------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                              ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+----------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                   ; -0.069 ; 0.177 ; N/A      ; N/A     ; 4.422               ;
;  Clock                                             ; N/A    ; N/A   ; N/A      ; N/A     ; 4.422               ;
;  inst2|altpll_component|auto_generated|pll1|clk[0] ; -0.069 ; 0.177 ; N/A      ; N/A     ; 8.046               ;
; Design-wide TNS                                    ; -0.636 ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  Clock                                             ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  inst2|altpll_component|auto_generated|pll1|clk[0] ; -0.636 ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+----------------------------------------------------+--------+-------+----------+---------+---------------------+


+---------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                             ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+
; DRover    ; Clock      ; 5.253 ; 5.782 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Trigger   ; Clock      ; 5.073 ; 5.613 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCS       ; Clock      ; 4.412 ; 4.779 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; 5.472 ; 5.949 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 4.336 ; 4.861 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 4.928 ; 5.441 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 5.061 ; 5.614 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; 4.375 ; 4.762 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4] ; Clock      ; 4.836 ; 5.322 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; 5.472 ; 5.949 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; 5.167 ; 5.654 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7] ; Clock      ; 4.265 ; 4.716 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCmd[*]   ; Clock      ; 7.847 ; 8.279 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[0]  ; Clock      ; 7.332 ; 7.824 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[1]  ; Clock      ; 6.959 ; 7.452 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[2]  ; Clock      ; 7.149 ; 7.637 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[3]  ; Clock      ; 7.847 ; 8.279 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; 6.237 ; 6.745 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; 6.237 ; 6.745 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; 5.960 ; 6.470 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; 5.767 ; 6.317 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; 6.236 ; 6.683 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; 5.421 ; 5.905 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; 5.981 ; 6.500 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+-------+-------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+
; DRover    ; Clock      ; -2.425 ; -3.246 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Trigger   ; Clock      ; -2.316 ; -3.155 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCS       ; Clock      ; -1.945 ; -2.679 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; -1.720 ; -2.469 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; -1.720 ; -2.469 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; -1.866 ; -2.678 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; -2.120 ; -2.960 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; -1.739 ; -2.495 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4] ; Clock      ; -1.934 ; -2.761 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; -1.907 ; -2.717 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; -2.008 ; -2.838 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7] ; Clock      ; -1.759 ; -2.560 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rCmd[*]   ; Clock      ; -1.974 ; -2.725 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[0]  ; Clock      ; -2.346 ; -3.119 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[1]  ; Clock      ; -2.226 ; -2.946 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[2]  ; Clock      ; -1.974 ; -2.725 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rCmd[3]  ; Clock      ; -2.277 ; -3.000 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]  ; Clock      ; -2.162 ; -2.959 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[0] ; Clock      ; -2.569 ; -3.419 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[1] ; Clock      ; -2.675 ; -3.533 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[2] ; Clock      ; -2.577 ; -3.456 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3] ; Clock      ; -2.396 ; -3.196 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5] ; Clock      ; -2.162 ; -2.959 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6] ; Clock      ; -2.379 ; -3.223 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+-----------+------------+--------+--------+------------+---------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                    ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Q2         ; Clock      ; 4.477 ; 4.498 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; CmdSeqFull ; Clock      ; 4.721 ; 4.709 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRctl      ; Clock      ; 5.291 ; 5.274 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRhold     ; Clock      ; 5.608 ; 5.592 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOrst      ; Clock      ; 4.532 ; 4.616 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOupdate   ; Clock      ; 6.572 ; 6.570 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q1         ; Clock      ; 5.534 ; 5.516 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q3         ; Clock      ; 8.758 ; 9.002 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Rst        ; Clock      ; 4.179 ; 4.209 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; SDio       ; Clock      ; 4.445 ; 4.495 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Sclk       ; Clock      ; 4.905 ; 5.019 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]   ; Clock      ; 6.332 ; 6.081 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3]  ; Clock      ; 3.675 ; 3.720 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4]  ; Clock      ; 3.441 ; 3.467 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5]  ; Clock      ; 3.408 ; 3.434 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6]  ; Clock      ; 6.332 ; 6.081 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7]  ; Clock      ; 3.961 ; 3.992 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+------------+------------+-------+-------+------------+---------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                            ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+------------+------------+-------+-------+------------+---------------------------------------------------+
; Q2         ; Clock      ; 2.042 ; 2.215 ; Rise       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; CmdSeqFull ; Clock      ; 2.203 ; 2.402 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRctl      ; Clock      ; 2.490 ; 2.651 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; DRhold     ; Clock      ; 2.661 ; 2.836 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOrst      ; Clock      ; 2.145 ; 2.281 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; IOupdate   ; Clock      ; 2.710 ; 2.893 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q1         ; Clock      ; 2.638 ; 2.818 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Q3         ; Clock      ; 4.271 ; 4.708 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Rst        ; Clock      ; 1.961 ; 2.082 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; SDio       ; Clock      ; 2.079 ; 2.207 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; Sclk       ; Clock      ; 2.337 ; 2.504 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
; rData[*]   ; Clock      ; 1.646 ; 1.587 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[3]  ; Clock      ; 1.784 ; 1.713 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[4]  ; Clock      ; 1.665 ; 1.601 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[5]  ; Clock      ; 1.646 ; 1.587 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[6]  ; Clock      ; 3.725 ; 3.384 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
;  rData[7]  ; Clock      ; 1.925 ; 1.852 ; Fall       ; inst2|altpll_component|auto_generated|pll1|clk[0] ;
+------------+------------+-------+-------+------------+---------------------------------------------------+


+------------------------------------------------------+
; Progagation Delay                                    ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Trigger    ; IOupdate    ; 9.054  ;    ;    ; 9.579  ;
; Trigger    ; Q3          ; 11.240 ;    ;    ; 12.011 ;
+------------+-------------+--------+----+----+--------+


+----------------------------------------------------+
; Minimum Progagation Delay                          ;
+------------+-------------+-------+----+----+-------+
; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
+------------+-------------+-------+----+----+-------+
; Trigger    ; IOupdate    ; 4.616 ;    ;    ; 5.570 ;
; Trigger    ; Q3          ; 6.177 ;    ;    ; 7.385 ;
+------------+-------------+-------+----+----+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Q1            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Q2            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRhold        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDio          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Sclk          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; IOrst         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; IOupdate      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; TXen          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Rst           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRctl         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Q3            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; TP1           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; TP2           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CmdSeqFull    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; P[0]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; P[1]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; P[2]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rData[7]      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rData[6]      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rData[5]      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rData[4]      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rData[3]      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rData[2]      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rData[1]      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; rData[0]      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_nCEO~ ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; Spare_in1               ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; Spare_in2               ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; Sdo                     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PLLlock                 ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; RAMswpOvr               ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rSpare[2]               ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rSpare[1]               ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rSpare[0]               ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rData[7]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rData[6]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rData[5]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rData[4]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rData[3]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rData[2]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rData[1]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rData[0]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; Trigger                 ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rCmd[0]                 ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rCmd[1]                 ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rCmd[2]                 ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rCmd[3]                 ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; Clk                     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; rCS                     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; DRover                  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Q1            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.58e-06 V                   ; 3.1 V               ; -0.0177 V           ; 0.11 V                               ; 0.102 V                              ; 8.58e-10 s                  ; 8.47e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.58e-06 V                  ; 3.1 V              ; -0.0177 V          ; 0.11 V                              ; 0.102 V                             ; 8.58e-10 s                 ; 8.47e-10 s                 ; Yes                       ; Yes                       ;
; Q2            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.58e-06 V                   ; 3.09 V              ; -0.0157 V           ; 0.125 V                              ; 0.21 V                               ; 1.28e-09 s                  ; 1.27e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.58e-06 V                  ; 3.09 V             ; -0.0157 V          ; 0.125 V                             ; 0.21 V                              ; 1.28e-09 s                 ; 1.27e-09 s                 ; Yes                       ; Yes                       ;
; DRhold        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; SDio          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; Sclk          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; IOrst         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; IOupdate      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; TXen          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; Rst           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; DRctl         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; Q3            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.58e-06 V                   ; 3.09 V              ; -0.00214 V          ; 0.106 V                              ; 0.189 V                              ; 6.91e-09 s                  ; 6.83e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.58e-06 V                  ; 3.09 V             ; -0.00214 V         ; 0.106 V                             ; 0.189 V                             ; 6.91e-09 s                 ; 6.83e-09 s                 ; Yes                       ; Yes                       ;
; TP1           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; TP2           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; CmdSeqFull    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.58e-06 V                   ; 3.09 V              ; -0.0157 V           ; 0.125 V                              ; 0.21 V                               ; 1.28e-09 s                  ; 1.27e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.58e-06 V                  ; 3.09 V             ; -0.0157 V          ; 0.125 V                             ; 0.21 V                              ; 1.28e-09 s                 ; 1.27e-09 s                 ; Yes                       ; Yes                       ;
; P[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; P[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; P[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; rData[7]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; rData[6]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0021 V           ; 0.065 V                              ; 0.193 V                              ; 6.95e-09 s                  ; 6.89e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0021 V          ; 0.065 V                             ; 0.193 V                             ; 6.95e-09 s                 ; 6.89e-09 s                 ; Yes                       ; Yes                       ;
; rData[5]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; rData[4]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; rData[3]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; rData[2]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; rData[1]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; rData[0]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.36e-06 V                   ; 3.09 V              ; -0.0165 V           ; 0.063 V                              ; 0.117 V                              ; 8.83e-10 s                  ; 8.63e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.36e-06 V                  ; 3.09 V             ; -0.0165 V          ; 0.063 V                             ; 0.117 V                             ; 8.83e-10 s                 ; 8.63e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.08e-07 V                   ; 3.13 V              ; -0.108 V            ; 0.146 V                              ; 0.136 V                              ; 3.07e-10 s                  ; 3.89e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.08e-07 V                  ; 3.13 V             ; -0.108 V           ; 0.146 V                             ; 0.136 V                             ; 3.07e-10 s                 ; 3.89e-10 s                 ; Yes                       ; No                        ;
; ~ALTERA_nCEO~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.58e-06 V                   ; 3.09 V              ; -0.0157 V           ; 0.125 V                              ; 0.21 V                               ; 1.28e-09 s                  ; 1.27e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.58e-06 V                  ; 3.09 V             ; -0.0157 V          ; 0.125 V                             ; 0.21 V                              ; 1.28e-09 s                 ; 1.27e-09 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Q1            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-07 V                   ; 3.54 V              ; -0.0659 V           ; 0.392 V                              ; 0.179 V                              ; 5.03e-10 s                  ; 6.23e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.98e-07 V                  ; 3.54 V             ; -0.0659 V          ; 0.392 V                             ; 0.179 V                             ; 5.03e-10 s                 ; 6.23e-10 s                 ; No                        ; No                        ;
; Q2            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-07 V                   ; 3.52 V              ; -0.0536 V           ; 0.251 V                              ; 0.255 V                              ; 8.74e-10 s                  ; 8.74e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.98e-07 V                  ; 3.52 V             ; -0.0536 V          ; 0.251 V                             ; 0.255 V                             ; 8.74e-10 s                 ; 8.74e-10 s                 ; No                        ; No                        ;
; DRhold        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; SDio          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; Sclk          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; IOrst         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; IOupdate      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; TXen          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; Rst           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; DRctl         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; Q3            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-07 V                   ; 3.47 V              ; -0.0089 V           ; 0.316 V                              ; 0.302 V                              ; 4.78e-09 s                  ; 4.88e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.98e-07 V                  ; 3.47 V             ; -0.0089 V          ; 0.316 V                             ; 0.302 V                             ; 4.78e-09 s                 ; 4.88e-09 s                 ; No                        ; No                        ;
; TP1           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; TP2           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; CmdSeqFull    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-07 V                   ; 3.52 V              ; -0.0536 V           ; 0.251 V                              ; 0.255 V                              ; 8.74e-10 s                  ; 8.74e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.98e-07 V                  ; 3.52 V             ; -0.0536 V          ; 0.251 V                             ; 0.255 V                             ; 8.74e-10 s                 ; 8.74e-10 s                 ; No                        ; No                        ;
; P[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; P[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; P[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; rData[7]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; rData[6]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.47 V              ; -0.00833 V          ; 0.321 V                              ; 0.308 V                              ; 4.78e-09 s                  ; 4.89e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.47 V             ; -0.00833 V         ; 0.321 V                             ; 0.308 V                             ; 4.78e-09 s                 ; 4.89e-09 s                 ; No                        ; No                        ;
; rData[5]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; rData[4]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; rData[3]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; rData[2]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; rData[1]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; rData[0]      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.92e-07 V                   ; 3.53 V              ; -0.0594 V           ; 0.209 V                              ; 0.186 V                              ; 6.36e-10 s                  ; 6.3e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 2.92e-07 V                  ; 3.53 V             ; -0.0594 V          ; 0.209 V                             ; 0.186 V                             ; 6.36e-10 s                 ; 6.3e-10 s                  ; No                        ; No                        ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.53e-08 V                   ; 3.65 V              ; -0.246 V            ; 0.406 V                              ; 0.305 V                              ; 1.57e-10 s                  ; 2.13e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 6.53e-08 V                  ; 3.65 V             ; -0.246 V           ; 0.406 V                             ; 0.305 V                             ; 1.57e-10 s                 ; 2.13e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.98e-07 V                   ; 3.52 V              ; -0.0536 V           ; 0.251 V                              ; 0.255 V                              ; 8.74e-10 s                  ; 8.74e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.98e-07 V                  ; 3.52 V             ; -0.0536 V          ; 0.251 V                             ; 0.255 V                             ; 8.74e-10 s                 ; 8.74e-10 s                 ; No                        ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                   ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
; From Clock                                        ; To Clock                                          ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 3        ; 802      ; 1734     ; 1612     ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                    ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
; From Clock                                        ; To Clock                                          ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
; inst2|altpll_component|auto_generated|pll1|clk[0] ; inst2|altpll_component|auto_generated|pll1|clk[0] ; 3        ; 802      ; 1734     ; 1612     ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 15    ; 15   ;
; Unconstrained Input Port Paths  ; 235   ; 235  ;
; Unconstrained Output Ports      ; 19    ; 19   ;
; Unconstrained Output Port Paths ; 25    ; 25   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 12.0 Build 178 05/31/2012 SJ Full Version
    Info: Processing started: Tue May 06 17:28:09 2014
Info: Command: quartus_sta GP_DDS -c GP_DDS
Info (P0): qsta_default_script.tcl version: #4
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'GP_DDS.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {inst2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 3 -duty_cycle 50.00 -name {inst2|altpll_component|auto_generated|pll1|clk[0]} {inst2|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (P0): Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (P0): Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -0.069
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.069        -0.636 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.397
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.397         0.000 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 4.793
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.793         0.000 Clock 
    Info (332119):     8.046         0.000 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (P0): Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.616
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.616         0.000 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.349
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.349         0.000 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 4.763
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.763         0.000 Clock 
    Info (332119):     8.053         0.000 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (P0): Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 4.433
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.433         0.000 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.177
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.177         0.000 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 4.422
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.422         0.000 Clock 
    Info (332119):     8.065         0.000 inst2|altpll_component|auto_generated|pll1|clk[0] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info (144001): Generated suppressed messages file C:/Projects/Archives/2011 General Purpose DDS/Altera/GP_DDS.sta.smsg
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 437 megabytes
    Info: Processing ended: Tue May 06 17:28:25 2014
    Info: Elapsed time: 00:00:16
    Info: Total CPU time (on all processors): 00:00:03


+-----------------------------------------------+
; TimeQuest Timing Analyzer Suppressed Messages ;
+-----------------------------------------------+
The suppressed messages can be found in C:/Projects/Archives/2011 General Purpose DDS/Altera/GP_DDS.sta.smsg.


