<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">Flow report for Test
Fri Apr 25 13:53:04 2014
Quartus II 64-Bit Version 12.0 Build 178 05/31/2012 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Flow Summary                                                                   ;
+------------------------------------+-------------------------------------------+
; Flow Status                        ; Successful - Fri Apr 25 13:53:04 2014     ;
; Quartus II 64-Bit Version          ; 12.0 Build 178 05/31/2012 SJ Full Version ;
; Revision Name                      ; Test                                      ;
; Top-level Entity Name              ; Test                                      ;
; Family                             ; Cyclone IV E                              ;
; Total logic elements               ; 1 / 6,272 ( &lt; 1 % )                       ;
;     Total combinational functions  ; 1 / 6,272 ( &lt; 1 % )                       ;
;     Dedicated logic registers      ; 0 / 6,272 ( 0 % )                         ;
; Total registers                    ; 0                                         ;
; Total pins                         ; 3 / 92 ( 3 % )                            ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 0 / 276,480 ( 0 % )                       ;
; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % )                            ;
; Total PLLs                         ; 0 / 2 ( 0 % )                             ;
; Device                             ; EP4CE6E22C6                               ;
; Timing Models                      ; Final                                     ;
+------------------------------------+-------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date &amp; time ; 04/25/2014 13:51:57 ;
; Main task         ; Compilation         ;
; Revision Name     ; Test                ;
+-------------------+---------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                     ;
+-------------------------------------+---------------------------------+---------------+-------------+----------------+
; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
+-------------------------------------+---------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID               ; 159410501154123.139844831406376 ; --            ; --          ; --             ;
; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                     ; --            ; --          ; eda_simulation ;
; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)       ; &lt;None&gt;        ; --          ; --             ;
; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+-------------------------------------+---------------------------------+---------------+-------------+----------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                             ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis &amp; Synthesis      ; 00:00:17     ; 1.0                     ; 412 MB              ; 00:00:02                           ;
; Fitter                    ; 00:00:25     ; 1.6                     ; 630 MB              ; 00:00:07                           ;
; Assembler                 ; 00:00:16     ; 1.0                     ; 380 MB              ; 00:00:01                           ;
; TimeQuest Timing Analyzer ; 00:00:17     ; 1.0                     ; 451 MB              ; 00:00:02                           ;
; EDA Netlist Writer        ; 00:00:17     ; 1.0                     ; 338 MB              ; 00:00:01                           ;
; Total                     ; 00:01:32     ; --                      ; --                  ; 00:00:13                           ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+


+----------------------------------------------------------------------------------------+
; Flow OS Summary                                                                        ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis &amp; Synthesis      ; Erbium           ; Windows 7 ; 6.1        ; x86_64         ;
; Fitter                    ; Erbium           ; Windows 7 ; 6.1        ; x86_64         ;
; Assembler                 ; Erbium           ; Windows 7 ; 6.1        ; x86_64         ;
; TimeQuest Timing Analyzer ; Erbium           ; Windows 7 ; 6.1        ; x86_64         ;
; EDA Netlist Writer        ; Erbium           ; Windows 7 ; 6.1        ; x86_64         ;
+---------------------------+------------------+-----------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off Test -c Test
quartus_fit --read_settings_files=off --write_settings_files=off Test -c Test
quartus_asm --read_settings_files=off --write_settings_files=off Test -c Test
quartus_sta Test -c Test
quartus_eda --read_settings_files=off --write_settings_files=off Test -c Test



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