| setting_showUnpublishedSettings | false | 
       
        | setting_showInternalSettings | false | 
       
        | setting_preciseSlaveAccessErrorException | false | 
       
        | setting_preciseIllegalMemAccessException | false | 
       
        | setting_preciseDivisionErrorException | false | 
       
        | setting_performanceCounter | false | 
       
        | setting_illegalMemAccessDetection | false | 
       
        | setting_illegalInstructionsTrap | false | 
       
        | setting_fullWaveformSignals | false | 
       
        | setting_extraExceptionInfo | false | 
       
        | setting_exportPCB | false | 
       
        | setting_debugSimGen | false | 
       
        | setting_clearXBitsLDNonBypass | true | 
       
        | setting_bit31BypassDCache | true | 
       
        | setting_bigEndian | false | 
       
        | setting_bhtIndexPcOnly | false | 
       
        | setting_avalonDebugPortPresent | false | 
       
        | setting_alwaysEncrypt | true | 
       
        | setting_allowFullAddressRange | false | 
       
        | setting_activateTrace | true | 
       
        | setting_activateTestEndChecker | false | 
       
        | setting_activateMonitors | true | 
       
        | setting_activateModelChecker | false | 
       
        | setting_HDLSimCachesCleared | true | 
       
        | setting_HBreakTest | false | 
       
        | muldiv_divider | false | 
       
        | mpu_useLimit | false | 
       
        | mpu_enabled | false | 
       
        | mmu_enabled | false | 
       
        | mmu_autoAssignTlbPtrSz | true | 
       
        | manuallyAssignCpuID | true | 
       
        | debug_triggerArming | true | 
       
        | debug_embeddedPLL | true | 
       
        | debug_debugReqSignals | false | 
       
        | debug_assignJtagInstanceID | false | 
       
        | dcache_omitDataMaster | false | 
       
        | cpuReset | false | 
       
        | is_hardcopy_compatible | false | 
       
        | setting_shadowRegisterSets | 0 | 
       
        | mpu_numOfInstRegion | 8 | 
       
        | mpu_numOfDataRegion | 8 | 
       
        | mmu_TLBMissExcOffset | 0 | 
       
        | debug_jtagInstanceID | 0 | 
       
        | resetOffset | 0 | 
       
        | exceptionOffset | 32 | 
       
        | cpuID | 0 | 
       
        | cpuID_stored | 0 | 
       
        | breakOffset | 32 | 
       
        | userDefinedSettings |  | 
       
        | resetSlave | oc_ram_32K.s1 | 
       
        | mmu_TLBMissExcSlave |  | 
       
        | exceptionSlave | oc_ram_32K.s1 | 
       
        | breakSlave | Nios_II.jtag_debug_module | 
       
        | setting_perfCounterWidth | 32 | 
       
        | setting_interruptControllerType | Internal | 
       
        | setting_branchPredictionType | Automatic | 
       
        | setting_bhtPtrSz | 8 | 
       
        | muldiv_multiplierType | DSPBlock | 
       
        | mpu_minInstRegionSize | 12 | 
       
        | mpu_minDataRegionSize | 12 | 
       
        | mmu_uitlbNumEntries | 4 | 
       
        | mmu_udtlbNumEntries | 6 | 
       
        | mmu_tlbPtrSz | 7 | 
       
        | mmu_tlbNumWays | 16 | 
       
        | mmu_processIDNumBits | 8 | 
       
        | impl | Tiny | 
       
        | icache_size | 4096 | 
       
        | icache_ramBlockType | Automatic | 
       
        | icache_numTCIM | 0 | 
       
        | icache_burstType | None | 
       
        | dcache_bursts | false | 
       
        | debug_level | Level1 | 
       
        | debug_OCIOnchipTrace | _128 | 
       
        | dcache_size | 2048 | 
       
        | dcache_ramBlockType | Automatic | 
       
        | dcache_numTCDM | 0 | 
       
        | dcache_lineSize | 32 | 
       
        | resetAbsoluteAddr | 16875520 | 
       
        | exceptionAbsoluteAddr | 16875552 | 
       
        | breakAbsoluteAddr | 16910368 | 
       
        | mmu_TLBMissExcAbsAddr | 0 | 
       
        | instAddrWidth | 25 | 
       
        | dataAddrWidth | 25 | 
       
        | tightlyCoupledDataMaster0AddrWidth | 1 | 
       
        | tightlyCoupledDataMaster1AddrWidth | 1 | 
       
        | tightlyCoupledDataMaster2AddrWidth | 1 | 
       
        | tightlyCoupledDataMaster3AddrWidth | 1 | 
       
        | tightlyCoupledInstructionMaster0AddrWidth | 1 | 
       
        | tightlyCoupledInstructionMaster1AddrWidth | 1 | 
       
        | tightlyCoupledInstructionMaster2AddrWidth | 1 | 
       
        | tightlyCoupledInstructionMaster3AddrWidth | 1 | 
       
        | instSlaveMapParam | <address-map><slave name='oc_rom_32K.s1' start='0x1010000' end='0x1018000' /><slave name='oc_ram_32K.s1' start='0x1018000' end='0x1020000' /><slave name='Nios_II.jtag_debug_module' start='0x1020800' end='0x1021000' /></address-map> | 
       
        | dataSlaveMapParam | <address-map><slave name='AvalonExport1_0.avalon_slave' start='0x0' end='0x20' /><slave name='oc_rom_32K.s1' start='0x1010000' end='0x1018000' /><slave name='oc_ram_32K.s1' start='0x1018000' end='0x1020000' /><slave name='Nios_II.jtag_debug_module' start='0x1020800' end='0x1021000' /><slave name='triple_speed_ethernet_0.control_port' start='0x1021000' end='0x1021400' /><slave name='timer_system.s1' start='0x1021400' end='0x1021440' /><slave name='Acam_PLL_40MHz.pll_slave' start='0x1021440' end='0x1021450' /><slave name='lcd_0.control_slave' start='0x1021450' end='0x1021460' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1021460' end='0x1021468' /></address-map> | 
       
        | clockFrequency | 50000000 | 
       
        | deviceFamilyName | ARRIAII | 
       
        | internalIrqMaskSystemInfo | 3 | 
       
        | customInstSlavesSystemInfo | <info/> | 
       
        | deviceFeaturesSystemInfo | NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 | 
       
        | tightlyCoupledDataMaster0MapParam |  | 
       
        | tightlyCoupledDataMaster1MapParam |  | 
       
        | tightlyCoupledDataMaster2MapParam |  | 
       
        | tightlyCoupledDataMaster3MapParam |  | 
       
        | tightlyCoupledInstructionMaster0MapParam |  | 
       
        | tightlyCoupledInstructionMaster1MapParam |  | 
       
        | tightlyCoupledInstructionMaster2MapParam |  | 
       
        | tightlyCoupledInstructionMaster3MapParam |  | 
       
        | deviceFamily | UNKNOWN | 
       
        | generateLegacySim | false |