Analysis & Synthesis report for PhotonFinish2
Tue Feb 04 12:15:38 2014
Quartus II 64-Bit Version 12.0 Build 178 05/31/2012 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis DSP Block Usage Summary
 10. Analysis & Synthesis IP Cores Summary
 11. State Machine - |PhotonFinish2|Uber:Big_Enchilada|RunState
 12. Registers Removed During Synthesis
 13. General Register Statistics
 14. Inverted Register Statistics
 15. Multiplexer Restructuring Statistics (Restructuring Performed)
 16. Source assignments for DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated
 17. Parameter Settings for User Entity Instance: altpll0:ClkGen|altpll:altpll_component
 18. Parameter Settings for User Entity Instance: DP_RAM:FIFO|altsyncram:altsyncram_component
 19. Parameter Settings for Inferred Entity Instance: Uber:Big_Enchilada|lpm_mult:Mult0
 20. altpll Parameter Settings by Entity Instance
 21. altsyncram Parameter Settings by Entity Instance
 22. lpm_mult Parameter Settings by Entity Instance
 23. Elapsed Time Per Partition
 24. Analysis & Synthesis Messages
 25. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Feb 04 12:15:38 2014     ;
; Quartus II 64-Bit Version          ; 12.0 Build 178 05/31/2012 SJ Full Version ;
; Revision Name                      ; PhotonFinish2                             ;
; Top-level Entity Name              ; PhotonFinish2                             ;
; Family                             ; Cyclone IV E                              ;
; Total logic elements               ; 256                                       ;
;     Total combinational functions  ; 215                                       ;
;     Dedicated logic registers      ; 186                                       ;
; Total registers                    ; 186                                       ;
; Total pins                         ; 68                                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 393,216                                   ;
; Embedded Multiplier 9-bit elements ; 2                                         ;
; Total PLLs                         ; 1                                         ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE22E22C6       ;                    ;
; Top-level entity name                                                      ; PhotonFinish2      ; PhotonFinish2      ;
; Family name                                                                ; Cyclone IV E       ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                   ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                         ; Library ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+---------+
; PhotonFinish2.bdf                ; yes             ; User Block Diagram/Schematic File  ; C:/Projects/2011_PhotonFinish2/Altera/PhotonFinish2.bdf              ;         ;
; DP_RAM.v                         ; yes             ; User Wizard-Generated File         ; C:/Projects/2011_PhotonFinish2/Altera/DP_RAM.v                       ;         ;
; uberPhotonFinish2.v              ; yes             ; User Verilog HDL File              ; C:/Projects/2011_PhotonFinish2/Altera/uberPhotonFinish2.v            ;         ;
; altpll0.v                        ; yes             ; User Wizard-Generated File         ; C:/Projects/2011_PhotonFinish2/Altera/altpll0.v                      ;         ;
; altpll.tdf                       ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altpll.tdf            ;         ;
; aglobal120.inc                   ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/aglobal120.inc        ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/stratix_pll.inc       ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/stratixii_pll.inc     ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/cycloneii_pll.inc     ;         ;
; db/altpll0_altpll.v              ; yes             ; Auto-Generated Megafunction        ; C:/Projects/2011_PhotonFinish2/Altera/db/altpll0_altpll.v            ;         ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altsyncram.tdf        ;         ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/stratix_ram_block.inc ;         ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/lpm_mux.inc           ;         ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/lpm_decode.inc        ;         ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/a_rdenreg.inc         ;         ;
; altrom.inc                       ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altrom.inc            ;         ;
; altram.inc                       ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altram.inc            ;         ;
; altdpram.inc                     ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altdpram.inc          ;         ;
; db/altsyncram_4sn1.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Projects/2011_PhotonFinish2/Altera/db/altsyncram_4sn1.tdf         ;         ;
; db/decode_jsa.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/Projects/2011_PhotonFinish2/Altera/db/decode_jsa.tdf              ;         ;
; db/decode_c8a.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/Projects/2011_PhotonFinish2/Altera/db/decode_c8a.tdf              ;         ;
; db/mux_gob.tdf                   ; yes             ; Auto-Generated Megafunction        ; C:/Projects/2011_PhotonFinish2/Altera/db/mux_gob.tdf                 ;         ;
; lpm_mult.tdf                     ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/lpm_mult.tdf          ;         ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/lpm_add_sub.inc       ;         ;
; multcore.inc                     ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/multcore.inc          ;         ;
; bypassff.inc                     ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/bypassff.inc          ;         ;
; altshift.inc                     ; yes             ; Megafunction                       ; c:/altera/12.0/quartus/libraries/megafunctions/altshift.inc          ;         ;
; db/mult_qbt.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Projects/2011_PhotonFinish2/Altera/db/mult_qbt.tdf                ;         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                         ;
+---------------------------------------------+---------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                 ;
+---------------------------------------------+---------------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 256                                                                                   ;
;                                             ;                                                                                       ;
; Total combinational functions               ; 215                                                                                   ;
; Logic element usage by number of LUT inputs ;                                                                                       ;
;     -- 4 input functions                    ; 71                                                                                    ;
;     -- 3 input functions                    ; 35                                                                                    ;
;     -- <=2 input functions                  ; 109                                                                                   ;
;                                             ;                                                                                       ;
; Logic elements by mode                      ;                                                                                       ;
;     -- normal mode                          ; 150                                                                                   ;
;     -- arithmetic mode                      ; 65                                                                                    ;
;                                             ;                                                                                       ;
; Total registers                             ; 186                                                                                   ;
;     -- Dedicated logic registers            ; 186                                                                                   ;
;     -- I/O registers                        ; 0                                                                                     ;
;                                             ;                                                                                       ;
; I/O pins                                    ; 68                                                                                    ;
; Total memory bits                           ; 393216                                                                                ;
; Embedded Multiplier 9-bit elements          ; 2                                                                                     ;
; Total PLLs                                  ; 1                                                                                     ;
;     -- PLLs                                 ; 1                                                                                     ;
;                                             ;                                                                                       ;
; Maximum fan-out node                        ; altpll0:ClkGen|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out                             ; 235                                                                                   ;
; Total fan-out                               ; 2869                                                                                  ;
; Average fan-out                             ; 4.57                                                                                  ;
+---------------------------------------------+---------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                 ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                          ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+--------------+
; |PhotonFinish2                            ; 215 (1)           ; 186 (0)      ; 393216      ; 2            ; 0       ; 1         ; 68   ; 0            ; |PhotonFinish2                                                                                               ;              ;
;    |DP_RAM:FIFO|                          ; 2 (0)             ; 2 (0)        ; 393216      ; 0            ; 0       ; 0         ; 0    ; 0            ; |PhotonFinish2|DP_RAM:FIFO                                                                                   ;              ;
;       |altsyncram:altsyncram_component|   ; 2 (0)             ; 2 (0)        ; 393216      ; 0            ; 0       ; 0         ; 0    ; 0            ; |PhotonFinish2|DP_RAM:FIFO|altsyncram:altsyncram_component                                                   ;              ;
;          |altsyncram_4sn1:auto_generated| ; 2 (0)             ; 2 (2)        ; 393216      ; 0            ; 0       ; 0         ; 0    ; 0            ; |PhotonFinish2|DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated                    ;              ;
;             |decode_jsa:decode2|          ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PhotonFinish2|DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|decode_jsa:decode2 ;              ;
;    |Uber:Big_Enchilada|                   ; 212 (212)         ; 184 (184)    ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |PhotonFinish2|Uber:Big_Enchilada                                                                            ;              ;
;       |lpm_mult:Mult0|                    ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |PhotonFinish2|Uber:Big_Enchilada|lpm_mult:Mult0                                                             ;              ;
;          |mult_qbt:auto_generated|        ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |PhotonFinish2|Uber:Big_Enchilada|lpm_mult:Mult0|mult_qbt:auto_generated                                     ;              ;
;    |altpll0:ClkGen|                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PhotonFinish2|altpll0:ClkGen                                                                                ;              ;
;       |altpll:altpll_component|           ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PhotonFinish2|altpll0:ClkGen|altpll:altpll_component                                                        ;              ;
;          |altpll0_altpll:auto_generated|  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PhotonFinish2|altpll0:ClkGen|altpll:altpll_component|altpll0_altpll:auto_generated                          ;              ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                            ;
+---------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; Name                                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF  ;
+---------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16384        ; 32           ; 16384        ; 32           ; 524288 ; None ;
+---------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 1           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 2           ;
; Signed Embedded Multipliers           ; 0           ;
; Unsigned Embedded Multipliers         ; 1           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                           ;
+--------+--------------+---------+--------------+--------------+-------------------------------+-------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance               ; IP Include File                                 ;
+--------+--------------+---------+--------------+--------------+-------------------------------+-------------------------------------------------+
; Altera ; RAM: 2-PORT  ; N/A     ; N/A          ; N/A          ; |PhotonFinish2|DP_RAM:FIFO    ; C:/Projects/2011_PhotonFinish2/Altera/DP_RAM.v  ;
; Altera ; ALTPLL       ; 12.0    ; N/A          ; N/A          ; |PhotonFinish2|altpll0:ClkGen ; C:/Projects/2011_PhotonFinish2/Altera/altpll0.v ;
+--------+--------------+---------+--------------+--------------+-------------------------------+-------------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------+
; State Machine - |PhotonFinish2|Uber:Big_Enchilada|RunState                                             ;
+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
; Name         ; RunState.101 ; RunState.100 ; RunState.011 ; RunState.010 ; RunState.001 ; RunState.000 ;
+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
; RunState.000 ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
; RunState.001 ; 0            ; 0            ; 0            ; 0            ; 1            ; 1            ;
; RunState.010 ; 0            ; 0            ; 0            ; 1            ; 0            ; 1            ;
; RunState.011 ; 0            ; 0            ; 1            ; 0            ; 0            ; 1            ;
; RunState.100 ; 0            ; 1            ; 0            ; 0            ; 0            ; 1            ;
; RunState.101 ; 1            ; 0            ; 0            ; 0            ; 0            ; 1            ;
+--------------+--------------+--------------+--------------+--------------+--------------+--------------+


+------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                 ;
+----------------------------------------+-------------------------------------------+
; Register name                          ; Reason for Removal                        ;
+----------------------------------------+-------------------------------------------+
; Uber:Big_Enchilada|DataRab[11]~en      ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[10]~en      ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[9]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[8]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[7]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[6]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[5]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[4]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[3]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[2]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[1]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[0]~en       ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|RamWrData[24..31]   ; Lost fanout                               ;
; Uber:Big_Enchilada|FifoNum             ; Lost fanout                               ;
; Uber:Big_Enchilada|AddrRun[2]          ; Merged with Uber:Big_Enchilada|AddrRun[1] ;
; Uber:Big_Enchilada|AddrRun[1]          ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[0]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[11]~reg0    ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[10]~reg0    ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[9]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[8]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[7]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[6]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[5]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[4]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[3]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[2]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|DataRab[1]~reg0     ; Stuck at GND due to stuck port data_in    ;
; Uber:Big_Enchilada|AddrRun[3]          ; Stuck at VCC due to stuck port data_in    ;
; Uber:Big_Enchilada|RunState~8          ; Lost fanout                               ;
; Uber:Big_Enchilada|RunState~9          ; Lost fanout                               ;
; Uber:Big_Enchilada|RunState~10         ; Lost fanout                               ;
; Total Number of Removed Registers = 39 ;                                           ;
+----------------------------------------+-------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 186   ;
; Number of registers using Synchronous Clear  ; 35    ;
; Number of registers using Synchronous Load   ; 32    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 173   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; Uber:Big_Enchilada|BinsPerStart[5]     ; 1       ;
; Uber:Big_Enchilada|BinsPerStart[8]     ; 1       ;
; Uber:Big_Enchilada|BinsPerStart[12]    ; 1       ;
; Uber:Big_Enchilada|BinsPerStart[13]    ; 1       ;
; Uber:Big_Enchilada|BinsPerStart[14]    ; 1       ;
; Uber:Big_Enchilada|BinsPerStart[15]    ; 1       ;
; Total number of inverted registers = 6 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                                       ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |PhotonFinish2|Uber:Big_Enchilada|Fiducial       ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |PhotonFinish2|Uber:Big_Enchilada|AddrRun[3]     ;                            ;
; 4:1                ; 14 bits   ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; |PhotonFinish2|Uber:Big_Enchilada|RamWrAddr[2]   ;                            ;
; 4:1                ; 14 bits   ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; |PhotonFinish2|Uber:Big_Enchilada|RamRdAddr[5]   ;                            ;
; 17:1               ; 4 bits    ; 44 LEs        ; 4 LEs                ; 40 LEs                 ; |PhotonFinish2|Uber:Big_Enchilada|DataAbuf[24]   ;                            ;
; 18:1               ; 8 bits    ; 96 LEs        ; 8 LEs                ; 88 LEs                 ; |PhotonFinish2|Uber:Big_Enchilada|DataAbuf[23]   ;                            ;
; 11:1               ; 8 bits    ; 56 LEs        ; 8 LEs                ; 48 LEs                 ; |PhotonFinish2|Uber:Big_Enchilada|DataAbuf[4]    ;                            ;
; 18:1               ; 4 bits    ; 48 LEs        ; 4 LEs                ; 44 LEs                 ; |PhotonFinish2|Uber:Big_Enchilada|DataAbuf[13]   ;                            ;
; 8:1                ; 4 bits    ; 20 LEs        ; 4 LEs                ; 16 LEs                 ; |PhotonFinish2|Uber:Big_Enchilada|DataAbuf[1]    ;                            ;
; 7:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; |PhotonFinish2|Uber:Big_Enchilada|DataAc[6]~reg0 ;                            ;
; 6:1                ; 4 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |PhotonFinish2|Uber:Big_Enchilada|DataAc[3]~reg0 ;                            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; |PhotonFinish2|Uber:Big_Enchilada|RunState       ;                            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |PhotonFinish2|Uber:Big_Enchilada|RunState       ;                            ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; |PhotonFinish2|Uber:Big_Enchilada|RunState       ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------+----------------------------+


+---------------------------------------------------------------------------------------------------+
; Source assignments for DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------+
; Assignment                      ; Value              ; From ; To                                  ;
+---------------------------------+--------------------+------+-------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                   ;
+---------------------------------+--------------------+------+-------------------------------------+


+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altpll0:ClkGen|altpll:altpll_component ;
+-------------------------------+---------------------------+-------------------------+
; Parameter Name                ; Value                     ; Type                    ;
+-------------------------------+---------------------------+-------------------------+
; OPERATION_MODE                ; NORMAL                    ; Untyped                 ;
; PLL_TYPE                      ; AUTO                      ; Untyped                 ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=altpll0 ; Untyped                 ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                 ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                 ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                 ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                 ;
; INCLK0_INPUT_FREQUENCY        ; 25000                     ; Signed Integer          ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                 ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                 ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                 ;
; LOCK_HIGH                     ; 1                         ; Untyped                 ;
; LOCK_LOW                      ; 1                         ; Untyped                 ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                 ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                 ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                 ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                 ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                 ;
; SKIP_VCO                      ; OFF                       ; Untyped                 ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                 ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                 ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                 ;
; BANDWIDTH                     ; 0                         ; Untyped                 ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                 ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                 ;
; DOWN_SPREAD                   ; 0                         ; Untyped                 ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                 ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                 ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                 ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                 ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                 ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                 ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                 ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                 ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                 ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                 ;
; CLK1_MULTIPLY_BY              ; 1                         ; Untyped                 ;
; CLK0_MULTIPLY_BY              ; 5                         ; Signed Integer          ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                 ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                 ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                 ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                 ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                 ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                 ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                 ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                 ;
; CLK1_DIVIDE_BY                ; 1                         ; Untyped                 ;
; CLK0_DIVIDE_BY                ; 2                         ; Signed Integer          ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                 ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                 ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                 ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                 ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                 ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                 ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                 ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK1_DUTY_CYCLE               ; 50                        ; Untyped                 ;
; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer          ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                 ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                 ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                 ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                 ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                 ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                 ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                 ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                 ;
; DPA_DIVIDER                   ; 0                         ; Untyped                 ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                 ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                 ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                 ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                 ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                 ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                 ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                 ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                 ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                 ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                 ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                 ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                 ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                 ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                 ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                 ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                 ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                 ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                 ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                 ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                 ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                 ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                 ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                 ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                 ;
; VCO_MIN                       ; 0                         ; Untyped                 ;
; VCO_MAX                       ; 0                         ; Untyped                 ;
; VCO_CENTER                    ; 0                         ; Untyped                 ;
; PFD_MIN                       ; 0                         ; Untyped                 ;
; PFD_MAX                       ; 0                         ; Untyped                 ;
; M_INITIAL                     ; 0                         ; Untyped                 ;
; M                             ; 0                         ; Untyped                 ;
; N                             ; 1                         ; Untyped                 ;
; M2                            ; 1                         ; Untyped                 ;
; N2                            ; 1                         ; Untyped                 ;
; SS                            ; 1                         ; Untyped                 ;
; C0_HIGH                       ; 0                         ; Untyped                 ;
; C1_HIGH                       ; 0                         ; Untyped                 ;
; C2_HIGH                       ; 0                         ; Untyped                 ;
; C3_HIGH                       ; 0                         ; Untyped                 ;
; C4_HIGH                       ; 0                         ; Untyped                 ;
; C5_HIGH                       ; 0                         ; Untyped                 ;
; C6_HIGH                       ; 0                         ; Untyped                 ;
; C7_HIGH                       ; 0                         ; Untyped                 ;
; C8_HIGH                       ; 0                         ; Untyped                 ;
; C9_HIGH                       ; 0                         ; Untyped                 ;
; C0_LOW                        ; 0                         ; Untyped                 ;
; C1_LOW                        ; 0                         ; Untyped                 ;
; C2_LOW                        ; 0                         ; Untyped                 ;
; C3_LOW                        ; 0                         ; Untyped                 ;
; C4_LOW                        ; 0                         ; Untyped                 ;
; C5_LOW                        ; 0                         ; Untyped                 ;
; C6_LOW                        ; 0                         ; Untyped                 ;
; C7_LOW                        ; 0                         ; Untyped                 ;
; C8_LOW                        ; 0                         ; Untyped                 ;
; C9_LOW                        ; 0                         ; Untyped                 ;
; C0_INITIAL                    ; 0                         ; Untyped                 ;
; C1_INITIAL                    ; 0                         ; Untyped                 ;
; C2_INITIAL                    ; 0                         ; Untyped                 ;
; C3_INITIAL                    ; 0                         ; Untyped                 ;
; C4_INITIAL                    ; 0                         ; Untyped                 ;
; C5_INITIAL                    ; 0                         ; Untyped                 ;
; C6_INITIAL                    ; 0                         ; Untyped                 ;
; C7_INITIAL                    ; 0                         ; Untyped                 ;
; C8_INITIAL                    ; 0                         ; Untyped                 ;
; C9_INITIAL                    ; 0                         ; Untyped                 ;
; C0_MODE                       ; BYPASS                    ; Untyped                 ;
; C1_MODE                       ; BYPASS                    ; Untyped                 ;
; C2_MODE                       ; BYPASS                    ; Untyped                 ;
; C3_MODE                       ; BYPASS                    ; Untyped                 ;
; C4_MODE                       ; BYPASS                    ; Untyped                 ;
; C5_MODE                       ; BYPASS                    ; Untyped                 ;
; C6_MODE                       ; BYPASS                    ; Untyped                 ;
; C7_MODE                       ; BYPASS                    ; Untyped                 ;
; C8_MODE                       ; BYPASS                    ; Untyped                 ;
; C9_MODE                       ; BYPASS                    ; Untyped                 ;
; C0_PH                         ; 0                         ; Untyped                 ;
; C1_PH                         ; 0                         ; Untyped                 ;
; C2_PH                         ; 0                         ; Untyped                 ;
; C3_PH                         ; 0                         ; Untyped                 ;
; C4_PH                         ; 0                         ; Untyped                 ;
; C5_PH                         ; 0                         ; Untyped                 ;
; C6_PH                         ; 0                         ; Untyped                 ;
; C7_PH                         ; 0                         ; Untyped                 ;
; C8_PH                         ; 0                         ; Untyped                 ;
; C9_PH                         ; 0                         ; Untyped                 ;
; L0_HIGH                       ; 1                         ; Untyped                 ;
; L1_HIGH                       ; 1                         ; Untyped                 ;
; G0_HIGH                       ; 1                         ; Untyped                 ;
; G1_HIGH                       ; 1                         ; Untyped                 ;
; G2_HIGH                       ; 1                         ; Untyped                 ;
; G3_HIGH                       ; 1                         ; Untyped                 ;
; E0_HIGH                       ; 1                         ; Untyped                 ;
; E1_HIGH                       ; 1                         ; Untyped                 ;
; E2_HIGH                       ; 1                         ; Untyped                 ;
; E3_HIGH                       ; 1                         ; Untyped                 ;
; L0_LOW                        ; 1                         ; Untyped                 ;
; L1_LOW                        ; 1                         ; Untyped                 ;
; G0_LOW                        ; 1                         ; Untyped                 ;
; G1_LOW                        ; 1                         ; Untyped                 ;
; G2_LOW                        ; 1                         ; Untyped                 ;
; G3_LOW                        ; 1                         ; Untyped                 ;
; E0_LOW                        ; 1                         ; Untyped                 ;
; E1_LOW                        ; 1                         ; Untyped                 ;
; E2_LOW                        ; 1                         ; Untyped                 ;
; E3_LOW                        ; 1                         ; Untyped                 ;
; L0_INITIAL                    ; 1                         ; Untyped                 ;
; L1_INITIAL                    ; 1                         ; Untyped                 ;
; G0_INITIAL                    ; 1                         ; Untyped                 ;
; G1_INITIAL                    ; 1                         ; Untyped                 ;
; G2_INITIAL                    ; 1                         ; Untyped                 ;
; G3_INITIAL                    ; 1                         ; Untyped                 ;
; E0_INITIAL                    ; 1                         ; Untyped                 ;
; E1_INITIAL                    ; 1                         ; Untyped                 ;
; E2_INITIAL                    ; 1                         ; Untyped                 ;
; E3_INITIAL                    ; 1                         ; Untyped                 ;
; L0_MODE                       ; BYPASS                    ; Untyped                 ;
; L1_MODE                       ; BYPASS                    ; Untyped                 ;
; G0_MODE                       ; BYPASS                    ; Untyped                 ;
; G1_MODE                       ; BYPASS                    ; Untyped                 ;
; G2_MODE                       ; BYPASS                    ; Untyped                 ;
; G3_MODE                       ; BYPASS                    ; Untyped                 ;
; E0_MODE                       ; BYPASS                    ; Untyped                 ;
; E1_MODE                       ; BYPASS                    ; Untyped                 ;
; E2_MODE                       ; BYPASS                    ; Untyped                 ;
; E3_MODE                       ; BYPASS                    ; Untyped                 ;
; L0_PH                         ; 0                         ; Untyped                 ;
; L1_PH                         ; 0                         ; Untyped                 ;
; G0_PH                         ; 0                         ; Untyped                 ;
; G1_PH                         ; 0                         ; Untyped                 ;
; G2_PH                         ; 0                         ; Untyped                 ;
; G3_PH                         ; 0                         ; Untyped                 ;
; E0_PH                         ; 0                         ; Untyped                 ;
; E1_PH                         ; 0                         ; Untyped                 ;
; E2_PH                         ; 0                         ; Untyped                 ;
; E3_PH                         ; 0                         ; Untyped                 ;
; M_PH                          ; 0                         ; Untyped                 ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                 ;
; CLK0_COUNTER                  ; G0                        ; Untyped                 ;
; CLK1_COUNTER                  ; G0                        ; Untyped                 ;
; CLK2_COUNTER                  ; G0                        ; Untyped                 ;
; CLK3_COUNTER                  ; G0                        ; Untyped                 ;
; CLK4_COUNTER                  ; G0                        ; Untyped                 ;
; CLK5_COUNTER                  ; G0                        ; Untyped                 ;
; CLK6_COUNTER                  ; E0                        ; Untyped                 ;
; CLK7_COUNTER                  ; E1                        ; Untyped                 ;
; CLK8_COUNTER                  ; E2                        ; Untyped                 ;
; CLK9_COUNTER                  ; E3                        ; Untyped                 ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                 ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                 ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                 ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                 ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                 ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                 ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                 ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                 ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                 ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                 ;
; M_TIME_DELAY                  ; 0                         ; Untyped                 ;
; N_TIME_DELAY                  ; 0                         ; Untyped                 ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                 ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                 ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                 ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                 ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                 ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                 ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                 ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                 ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                 ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                 ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                 ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                 ;
; VCO_POST_SCALE                ; 0                         ; Untyped                 ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                 ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                 ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                 ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E              ; Untyped                 ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                 ;
; PORT_CLK1                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                 ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                 ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                 ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                 ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                 ;
; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                 ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                 ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                 ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                 ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                 ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                 ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                 ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                 ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                 ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                 ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                 ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                 ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                 ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                 ;
; CBXI_PARAMETER                ; altpll0_altpll            ; Untyped                 ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                 ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                 ;
; WIDTH_CLOCK                   ; 5                         ; Signed Integer          ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                 ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                 ;
; DEVICE_FAMILY                 ; Cyclone IV E              ; Untyped                 ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                 ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                 ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY              ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY            ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE            ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE          ;
+-------------------------------+---------------------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DP_RAM:FIFO|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------+
; Parameter Name                     ; Value                ; Type                         ;
+------------------------------------+----------------------+------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                      ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                   ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                 ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE               ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                      ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                      ;
; WIDTH_A                            ; 32                   ; Signed Integer               ;
; WIDTHAD_A                          ; 14                   ; Signed Integer               ;
; NUMWORDS_A                         ; 16384                ; Signed Integer               ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                      ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                      ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                      ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                      ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                      ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                      ;
; WIDTH_B                            ; 32                   ; Signed Integer               ;
; WIDTHAD_B                          ; 14                   ; Signed Integer               ;
; NUMWORDS_B                         ; 16384                ; Signed Integer               ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                      ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                      ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                      ;
; OUTDATA_REG_B                      ; CLOCK0               ; Untyped                      ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                      ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                      ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                      ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                      ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                      ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                      ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                      ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer               ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                      ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                      ;
; BYTE_SIZE                          ; 8                    ; Untyped                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                      ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                      ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                      ;
; INIT_FILE                          ; UNUSED               ; Untyped                      ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                      ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                      ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                      ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                      ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                      ;
; ENABLE_ECC                         ; FALSE                ; Untyped                      ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                      ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                      ;
; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                      ;
; CBXI_PARAMETER                     ; altsyncram_4sn1      ; Untyped                      ;
+------------------------------------+----------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Uber:Big_Enchilada|lpm_mult:Mult0  ;
+------------------------------------------------+--------------+---------------------+
; Parameter Name                                 ; Value        ; Type                ;
+------------------------------------------------+--------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON           ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF          ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON           ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF          ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 8            ; Untyped             ;
; LPM_WIDTHB                                     ; 17           ; Untyped             ;
; LPM_WIDTHP                                     ; 25           ; Untyped             ;
; LPM_WIDTHR                                     ; 25           ; Untyped             ;
; LPM_WIDTHS                                     ; 1            ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED     ; Untyped             ;
; LPM_PIPELINE                                   ; 0            ; Untyped             ;
; LATENCY                                        ; 0            ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO           ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO           ; Untyped             ;
; USE_EAB                                        ; OFF          ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5            ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone IV E ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL       ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT          ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO         ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0            ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0            ; Untyped             ;
; CBXI_PARAMETER                                 ; mult_qbt     ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx           ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx           ; Untyped             ;
; USE_AHDL_IMPLEMENTATION                        ; OFF          ; Untyped             ;
+------------------------------------------------+--------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                           ;
+-------------------------------+----------------------------------------+
; Name                          ; Value                                  ;
+-------------------------------+----------------------------------------+
; Number of entity instances    ; 1                                      ;
; Entity Instance               ; altpll0:ClkGen|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                 ;
;     -- PLL_TYPE               ; AUTO                                   ;
;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
;     -- INCLK0_INPUT_FREQUENCY ; 25000                                  ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
;     -- VCO_MULTIPLY_BY        ; 0                                      ;
;     -- VCO_DIVIDE_BY          ; 0                                      ;
+-------------------------------+----------------------------------------+


+-----------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                        ;
+-------------------------------------------+---------------------------------------------+
; Name                                      ; Value                                       ;
+-------------------------------------------+---------------------------------------------+
; Number of entity instances                ; 1                                           ;
; Entity Instance                           ; DP_RAM:FIFO|altsyncram:altsyncram_component ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                   ;
;     -- WIDTH_A                            ; 32                                          ;
;     -- NUMWORDS_A                         ; 16384                                       ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                ;
;     -- WIDTH_B                            ; 32                                          ;
;     -- NUMWORDS_B                         ; 16384                                       ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                      ;
;     -- OUTDATA_REG_B                      ; CLOCK0                                      ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                        ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                   ;
+-------------------------------------------+---------------------------------------------+


+---------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                            ;
+---------------------------------------+-----------------------------------+
; Name                                  ; Value                             ;
+---------------------------------------+-----------------------------------+
; Number of entity instances            ; 1                                 ;
; Entity Instance                       ; Uber:Big_Enchilada|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 8                                 ;
;     -- LPM_WIDTHB                     ; 17                                ;
;     -- LPM_WIDTHP                     ; 25                                ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                          ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                ;
;     -- USE_EAB                        ; OFF                               ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                              ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                ;
+---------------------------------------+-----------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:03     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 12.0 Build 178 05/31/2012 SJ Full Version
    Info: Processing started: Tue Feb 04 12:15:19 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PhotonFinish2 -c PhotonFinish2
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file photonfinish2.bdf
    Info (12023): Found entity 1: PhotonFinish2
Info (12021): Found 1 design units, including 1 entities, in source file dp_ram.v
    Info (12023): Found entity 1: DP_RAM
Info (12021): Found 1 design units, including 1 entities, in source file uberphotonfinish2.v
    Info (12023): Found entity 1: Uber
Info (12021): Found 1 design units, including 1 entities, in source file altpll0.v
    Info (12023): Found entity 1: altpll0
Info (12127): Elaborating entity "PhotonFinish2" for the top level hierarchy
Info (12128): Elaborating entity "Uber" for hierarchy "Uber:Big_Enchilada"
Warning (10858): Verilog HDL warning at uberPhotonFinish2.v(85): object EventCtr used but never assigned
Warning (10030): Net "EventCtr" at uberPhotonFinish2.v(85) has no driver or initial value, using a default initial value '0'
Warning (10034): Output port "ALUtrigger" at uberPhotonFinish2.v(58) has no driver
Info (12128): Elaborating entity "altpll0" for hierarchy "altpll0:ClkGen"
Info (12128): Elaborating entity "altpll" for hierarchy "altpll0:ClkGen|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "altpll0:ClkGen|altpll:altpll_component"
Info (12133): Instantiated megafunction "altpll0:ClkGen|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "2"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "5"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "25000"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll0"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/altpll0_altpll.v
    Info (12023): Found entity 1: altpll0_altpll
Info (12128): Elaborating entity "altpll0_altpll" for hierarchy "altpll0:ClkGen|altpll:altpll_component|altpll0_altpll:auto_generated"
Info (12128): Elaborating entity "DP_RAM" for hierarchy "DP_RAM:FIFO"
Info (12128): Elaborating entity "altsyncram" for hierarchy "DP_RAM:FIFO|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "DP_RAM:FIFO|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "DP_RAM:FIFO|altsyncram:altsyncram_component" with the following parameter:
    Info (12134): Parameter "address_aclr_b" = "NONE"
    Info (12134): Parameter "address_reg_b" = "CLOCK0"
    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
    Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
    Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "16384"
    Info (12134): Parameter "numwords_b" = "16384"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "widthad_a" = "14"
    Info (12134): Parameter "widthad_b" = "14"
    Info (12134): Parameter "width_a" = "32"
    Info (12134): Parameter "width_b" = "32"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4sn1.tdf
    Info (12023): Found entity 1: altsyncram_4sn1
Info (12128): Elaborating entity "altsyncram_4sn1" for hierarchy "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
    Info (12023): Found entity 1: decode_jsa
Info (12128): Elaborating entity "decode_jsa" for hierarchy "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|decode_jsa:decode2"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf
    Info (12023): Found entity 1: decode_c8a
Info (12128): Elaborating entity "decode_c8a" for hierarchy "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|decode_c8a:rden_decode_b"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_gob.tdf
    Info (12023): Found entity 1: mux_gob
Info (12128): Elaborating entity "mux_gob" for hierarchy "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|mux_gob:mux3"
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a24"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a25"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a26"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a27"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a28"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a29"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a30"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a31"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a56"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a57"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a58"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a59"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a60"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a61"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a62"
        Warning (14320): Synthesized away node "DP_RAM:FIFO|altsyncram:altsyncram_component|altsyncram_4sn1:auto_generated|ram_block1a63"
Info (278001): Inferred 1 megafunctions from design logic
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Uber:Big_Enchilada|Mult0"
Info (12130): Elaborated megafunction instantiation "Uber:Big_Enchilada|lpm_mult:Mult0"
Info (12133): Instantiated megafunction "Uber:Big_Enchilada|lpm_mult:Mult0" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHA" = "8"
    Info (12134): Parameter "LPM_WIDTHB" = "17"
    Info (12134): Parameter "LPM_WIDTHP" = "25"
    Info (12134): Parameter "LPM_WIDTHR" = "25"
    Info (12134): Parameter "LPM_WIDTHS" = "1"
    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_qbt.tdf
    Info (12023): Found entity 1: mult_qbt
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "ALUtrigger" is stuck at GND
    Warning (13410): Pin "nOE" is stuck at VCC
    Warning (13410): Pin "TP2" is stuck at GND
Info (286030): Timing-Driven Synthesis is running
Info (17049): 12 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file C:/Projects/2011_PhotonFinish2/Altera/PhotonFinish2.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 375 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 14 input pins
    Info (21059): Implemented 14 output pins
    Info (21060): Implemented 40 bidirectional pins
    Info (21061): Implemented 256 logic cells
    Info (21064): Implemented 48 RAM segments
    Info (21065): Implemented 1 PLLs
    Info (21062): Implemented 2 DSP elements
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Peak virtual memory: 441 megabytes
    Info: Processing ended: Tue Feb 04 12:15:38 2014
    Info: Elapsed time: 00:00:19
    Info: Total CPU time (on all processors): 00:00:04


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Projects/2011_PhotonFinish2/Altera/PhotonFinish2.map.smsg.


