Fitter report for ACync
Thu Mar 12 16:10:26 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. I/O Assignment Warnings
  6. Ignored Assignments
  7. Incremental Compilation Preservation Summary
  8. Incremental Compilation Partition Settings
  9. Incremental Compilation Placement Preservation
 10. Pin-Out File
 11. Fitter Resource Usage Summary
 12. Fitter Partition Statistics
 13. Input Pins
 14. Output Pins
 15. Dual Purpose and Dedicated Pins
 16. I/O Bank Usage
 17. All Package Pins
 18. Migration Devices
 19. PLL Summary
 20. PLL Usage
 21. Fitter Resource Utilization by Entity
 22. Delay Chain Summary
 23. Pad To Core Delay Chain Fanout
 24. Control Signals
 25. Global & Other Fast Signals
 26. Non-Global High Fan-Out Signals
 27. Fitter RAM Summary
 28. Routing Usage Summary
 29. LAB Logic Elements
 30. LAB-wide Signals
 31. LAB Signals Sourced
 32. LAB Signals Sourced Out
 33. LAB Distinct Inputs
 34. I/O Rules Summary
 35. I/O Rules Details
 36. I/O Rules Matrix
 37. Fitter Device Options
 38. Operating Settings and Conditions
 39. Estimated Delay Added for Hold Timing Summary
 40. Estimated Delay Added for Hold Timing Details
 41. Fitter Messages
 42. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Fitter Summary                                                                   ;
+------------------------------------+---------------------------------------------+
; Fitter Status                      ; Successful - Thu Mar 12 16:10:26 2015       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; ACync                                       ;
; Top-level Entity Name              ; ACync_block                                 ;
; Family                             ; Cyclone IV E                                ;
; Device                             ; EP4CE15E22C6                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 1,152 / 15,408 ( 7 % )                      ;
;     Total combinational functions  ; 939 / 15,408 ( 6 % )                        ;
;     Dedicated logic registers      ; 581 / 15,408 ( 4 % )                        ;
; Total registers                    ; 581                                         ;
; Total pins                         ; 51 / 82 ( 62 % )                            ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 458,752 / 516,096 ( 89 % )                  ;
; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
+------------------------------------+---------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                                                       ;
+----------------------------------------------------------------------------+------------------------------------------------------------------+---------------------------------------+
; Option                                                                     ; Setting                                                          ; Default Value                         ;
+----------------------------------------------------------------------------+------------------------------------------------------------------+---------------------------------------+
; Device                                                                     ; EP4CE15E22C6                                                     ;                                       ;
; Minimum Core Junction Temperature                                          ; 0                                                                ;                                       ;
; Maximum Core Junction Temperature                                          ; 85                                                               ;                                       ;
; Fit Attempts to Skip                                                       ; 0                                                                ; 0.0                                   ;
; Device Migration List                                                      ; EP4CE15E22C6,EP4CE15E22C7,EP4CE15E22C8,EP4CE15E22I7,EP4CE15E22C8 ;                                       ;
; Device I/O Standard                                                        ; 3.3-V LVCMOS                                                     ;                                       ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; On                                                               ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; On                                                               ; Off                                   ;
; Perform Register Retiming for Performance                                  ; On                                                               ; Off                                   ;
; Fitter Effort                                                              ; Fast Fit                                                         ; Auto Fit                              ;
; Synchronizer Identification                                                ; Auto                                                             ; Off                                   ;
; Use smart compilation                                                      ; Off                                                              ; Off                                   ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                                               ; On                                    ;
; Enable compact report table                                                ; Off                                                              ; Off                                   ;
; Auto Merge PLLs                                                            ; On                                                               ; On                                    ;
; Router Timing Optimization Level                                           ; Normal                                                           ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                          ; Off                                                              ; Off                                   ;
; Placement Effort Multiplier                                                ; 1.0                                                              ; 1.0                                   ;
; Router Effort Multiplier                                                   ; 1.0                                                              ; 1.0                                   ;
; Optimize Hold Timing                                                       ; All Paths                                                        ; All Paths                             ;
; Optimize Multi-Corner Timing                                               ; On                                                               ; On                                    ;
; PowerPlay Power Optimization                                               ; Normal compilation                                               ; Normal compilation                    ;
; SSN Optimization                                                           ; Off                                                              ; Off                                   ;
; Optimize Timing                                                            ; Normal compilation                                               ; Normal compilation                    ;
; Optimize Timing for ECOs                                                   ; Off                                                              ; Off                                   ;
; Regenerate full fit report during ECO compiles                             ; Off                                                              ; Off                                   ;
; Optimize IOC Register Placement for Timing                                 ; Normal                                                           ; Normal                                ;
; Limit to One Fitting Attempt                                               ; Off                                                              ; Off                                   ;
; Final Placement Optimizations                                              ; Automatically                                                    ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                                                    ; Automatically                         ;
; Fitter Initial Placement Seed                                              ; 1                                                                ; 1                                     ;
; PCI I/O                                                                    ; Off                                                              ; Off                                   ;
; Weak Pull-Up Resistor                                                      ; Off                                                              ; Off                                   ;
; Enable Bus-Hold Circuitry                                                  ; Off                                                              ; Off                                   ;
; Auto Packed Registers                                                      ; Auto                                                             ; Auto                                  ;
; Auto Delay Chains                                                          ; On                                                               ; On                                    ;
; Auto Delay Chains for High Fanout Input Pins                               ; Off                                                              ; Off                                   ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                                              ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                                                              ; Off                                   ;
; Perform Register Duplication for Performance                               ; Off                                                              ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                                                              ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                     ; Off                                                              ; Off                                   ;
; Physical Synthesis Effort Level                                            ; Normal                                                           ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                                                             ; Auto                                  ;
; Auto Register Duplication                                                  ; Auto                                                             ; Auto                                  ;
; Auto Global Clock                                                          ; On                                                               ; On                                    ;
; Auto Global Register Control Signals                                       ; On                                                               ; On                                    ;
; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up                            ; As input tri-stated with weak pull-up ;
; Enable Beneficial Skew Optimization                                        ; On                                                               ; On                                    ;
; Optimize Design for Metastability                                          ; On                                                               ; On                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                                              ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode           ; Off                                                              ; Off                                   ;
+----------------------------------------------------------------------------+------------------------------------------------------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.23        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  22.7%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------+
; I/O Assignment Warnings               ;
+--------------+------------------------+
; Pin Name     ; Reason                 ;
+--------------+------------------------+
; Prbs         ; Missing drive strength ;
; AdcClk       ; Missing drive strength ;
; AdcCs        ; Missing drive strength ;
; AdcStart     ; Missing drive strength ;
; DacLoad      ; Missing drive strength ;
; DacCs        ; Missing drive strength ;
; PotClk       ; Missing drive strength ;
; PotStart     ; Missing drive strength ;
; Led          ; Missing drive strength ;
; DacAddr[1]   ; Missing drive strength ;
; DacAddr[0]   ; Missing drive strength ;
; DacDat[11]   ; Missing drive strength ;
; DacDat[10]   ; Missing drive strength ;
; DacDat[9]    ; Missing drive strength ;
; DacDat[8]    ; Missing drive strength ;
; DacDat[7]    ; Missing drive strength ;
; DacDat[6]    ; Missing drive strength ;
; DacDat[5]    ; Missing drive strength ;
; DacDat[4]    ; Missing drive strength ;
; DacDat[3]    ; Missing drive strength ;
; DacDat[2]    ; Missing drive strength ;
; DacDat[1]    ; Missing drive strength ;
; DacDat[0]    ; Missing drive strength ;
; DigOut[7]    ; Missing drive strength ;
; DigOut[6]    ; Missing drive strength ;
; DigOut[5]    ; Missing drive strength ;
; DigOut[4]    ; Missing drive strength ;
; DigOut[3]    ; Missing drive strength ;
; DigOut[2]    ; Missing drive strength ;
; DigOut[1]    ; Missing drive strength ;
; DigOut[0]    ; Missing drive strength ;
; ExtendOut[1] ; Missing drive strength ;
; ExtendOut[0] ; Missing drive strength ;
+--------------+------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Ignored Assignments                                                                                                             ;
+-----------------------------+----------------+--------------+-------------+------------------------+----------------------------+
; Name                        ; Ignored Entity ; Ignored From ; Ignored To  ; Ignored Value          ; Ignored Source             ;
+-----------------------------+----------------+--------------+-------------+------------------------+----------------------------+
; Synchronizer Identification ; dcfifo_h0l1    ;              ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
; Synchronizer Identification ; dcfifo_s1l1    ;              ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+-----------------------------+----------------+--------------+-------------+------------------------+----------------------------+


+---------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary                                                      ;
+---------------------+---------------------+----------------------------+--------------------------+
; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+---------------------+----------------------------+--------------------------+
; Placement (by node) ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 1719 ) ; 0.00 % ( 0 / 1719 )        ; 0.00 % ( 0 / 1719 )      ;
;     -- Achieved     ; 0.00 % ( 0 / 1719 ) ; 0.00 % ( 0 / 1719 )        ; 0.00 % ( 0 / 1719 )      ;
;                     ;                     ;                            ;                          ;
; Routing (by net)    ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+---------------------+---------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                                                     ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top                            ; 0.00 % ( 0 / 1707 )   ; N/A                     ; Source File       ; N/A                 ;       ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 12 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Projects/Archives/2015 ACync/Altera/output_files/ACync.pin.


+---------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                             ;
+---------------------------------------------+-----------------------------+
; Resource                                    ; Usage                       ;
+---------------------------------------------+-----------------------------+
; Total logic elements                        ; 1,152 / 15,408 ( 7 % )      ;
;     -- Combinational with no register       ; 571                         ;
;     -- Register only                        ; 213                         ;
;     -- Combinational with a register        ; 368                         ;
;                                             ;                             ;
; Logic element usage by number of LUT inputs ;                             ;
;     -- 4 input functions                    ; 580                         ;
;     -- 3 input functions                    ; 149                         ;
;     -- <=2 input functions                  ; 210                         ;
;     -- Register only                        ; 213                         ;
;                                             ;                             ;
; Logic elements by mode                      ;                             ;
;     -- normal mode                          ; 821                         ;
;     -- arithmetic mode                      ; 118                         ;
;                                             ;                             ;
; Total registers*                            ; 581 / 15,746 ( 4 % )        ;
;     -- Dedicated logic registers            ; 581 / 15,408 ( 4 % )        ;
;     -- I/O registers                        ; 0 / 338 ( 0 % )             ;
;                                             ;                             ;
; Total LABs:  partially or completely used   ; 91 / 963 ( 9 % )            ;
; Virtual pins                                ; 0                           ;
; I/O pins                                    ; 51 / 82 ( 62 % )            ;
;     -- Clock pins                           ; 4 / 7 ( 57 % )              ;
;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )               ;
;                                             ;                             ;
; Global signals                              ; 6                           ;
; M9Ks                                        ; 56 / 56 ( 100 % )           ;
; Total block memory bits                     ; 458,752 / 516,096 ( 89 % )  ;
; Total block memory implementation bits      ; 516,096 / 516,096 ( 100 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )             ;
; PLLs                                        ; 1 / 4 ( 25 % )              ;
; Global clocks                               ; 6 / 20 ( 30 % )             ;
; JTAGs                                       ; 0 / 1 ( 0 % )               ;
; CRC blocks                                  ; 0 / 1 ( 0 % )               ;
; ASMI blocks                                 ; 0 / 1 ( 0 % )               ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )               ;
; Average interconnect usage (total/H/V)      ; 6% / 5% / 6%                ;
; Peak interconnect usage (total/H/V)         ; 18% / 15% / 23%             ;
; Maximum fan-out                             ; 381                         ;
; Highest non-global fan-out                  ; 87                          ;
; Total fan-out                               ; 7092                        ;
; Average fan-out                             ; 3.80                        ;
+---------------------------------------------+-----------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+-----------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                         ;
+---------------------------------------------+----------------------+--------------------------------+
; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
+---------------------------------------------+----------------------+--------------------------------+
; Difficulty Clustering Region                ; Low                  ; Low                            ;
;                                             ;                      ;                                ;
; Total logic elements                        ; 1152 / 15408 ( 7 % ) ; 0 / 15408 ( 0 % )              ;
;     -- Combinational with no register       ; 571                  ; 0                              ;
;     -- Register only                        ; 213                  ; 0                              ;
;     -- Combinational with a register        ; 368                  ; 0                              ;
;                                             ;                      ;                                ;
; Logic element usage by number of LUT inputs ;                      ;                                ;
;     -- 4 input functions                    ; 580                  ; 0                              ;
;     -- 3 input functions                    ; 149                  ; 0                              ;
;     -- <=2 input functions                  ; 210                  ; 0                              ;
;     -- Register only                        ; 213                  ; 0                              ;
;                                             ;                      ;                                ;
; Logic elements by mode                      ;                      ;                                ;
;     -- normal mode                          ; 821                  ; 0                              ;
;     -- arithmetic mode                      ; 118                  ; 0                              ;
;                                             ;                      ;                                ;
; Total registers                             ; 581                  ; 0                              ;
;     -- Dedicated logic registers            ; 581 / 15408 ( 4 % )  ; 0 / 15408 ( 0 % )              ;
;     -- I/O registers                        ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Total LABs:  partially or completely used   ; 91 / 963 ( 9 % )     ; 0 / 963 ( 0 % )                ;
;                                             ;                      ;                                ;
; Virtual pins                                ; 0                    ; 0                              ;
; I/O pins                                    ; 51                   ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
; Total memory bits                           ; 458752               ; 0                              ;
; Total RAM block bits                        ; 516096               ; 0                              ;
; PLL                                         ; 0 / 4 ( 0 % )        ; 1 / 4 ( 25 % )                 ;
; M9K                                         ; 56 / 56 ( 100 % )    ; 0 / 56 ( 0 % )                 ;
; Clock control block                         ; 5 / 24 ( 20 % )      ; 1 / 24 ( 4 % )                 ;
;                                             ;                      ;                                ;
; Connections                                 ;                      ;                                ;
;     -- Input Connections                    ; 252                  ; 1                              ;
;     -- Registered Input Connections         ; 252                  ; 0                              ;
;     -- Output Connections                   ; 1                    ; 252                            ;
;     -- Registered Output Connections        ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Internal Connections                        ;                      ;                                ;
;     -- Total Connections                    ; 7155                 ; 260                            ;
;     -- Registered Connections               ; 4023                 ; 0                              ;
;                                             ;                      ;                                ;
; External Connections                        ;                      ;                                ;
;     -- Top                                  ; 0                    ; 253                            ;
;     -- hard_block:auto_generated_inst       ; 253                  ; 0                              ;
;                                             ;                      ;                                ;
; Partition Interface                         ;                      ;                                ;
;     -- Input Ports                          ; 18                   ; 1                              ;
;     -- Output Ports                         ; 33                   ; 1                              ;
;     -- Bidir Ports                          ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Registered Ports                            ;                      ;                                ;
;     -- Registered Input Ports               ; 0                    ; 0                              ;
;     -- Registered Output Ports              ; 0                    ; 0                              ;
;                                             ;                      ;                                ;
; Port Connectivity                           ;                      ;                                ;
;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
;     -- Input Ports with no Source           ; 0                    ; 0                              ;
;     -- Output Ports with no Source          ; 0                    ; 0                              ;
;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
+---------------------------------------------+----------------------+--------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                       ;
+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; AC60Hz      ; 53    ; 3        ; 21           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; Adc1        ; 69    ; 4        ; 37           ; 0            ; 28           ; 12                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; Adc2        ; 58    ; 4        ; 26           ; 0            ; 28           ; 12                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; Adc3        ; 71    ; 4        ; 37           ; 0            ; 7            ; 12                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; Adc4        ; 72    ; 4        ; 37           ; 0            ; 0            ; 12                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; Clk100      ; 23    ; 1        ; 0            ; 14           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[0]    ; 31    ; 2        ; 0            ; 6            ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[1]    ; 39    ; 3        ; 3            ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[2]    ; 42    ; 3        ; 5            ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[3]    ; 43    ; 3        ; 5            ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[4]    ; 44    ; 3        ; 7            ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[5]    ; 46    ; 3        ; 14           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[6]    ; 54    ; 4        ; 21           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[7]    ; 55    ; 4        ; 21           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; ExtendIn[0] ; 52    ; 3        ; 21           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; ExtendIn[1] ; 51    ; 3        ; 19           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; Master      ; 33    ; 2        ; 0            ; 4            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; PotDat      ; 127   ; 7        ; 19           ; 29           ; 7            ; 9                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; AdcClk       ; 68    ; 4        ; 35           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; AdcCs        ; 67    ; 4        ; 35           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; AdcStart     ; 66    ; 4        ; 35           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacAddr[0]   ; 59    ; 4        ; 26           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacAddr[1]   ; 60    ; 4        ; 26           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacCs        ; 64    ; 4        ; 30           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[0]    ; 132   ; 8        ; 14           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[10]   ; 87    ; 5        ; 41           ; 13           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[11]   ; 98    ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[1]    ; 133   ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[2]    ; 134   ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[3]    ; 76    ; 5        ; 41           ; 2            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[4]    ; 77    ; 5        ; 41           ; 3            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[5]    ; 80    ; 5        ; 41           ; 6            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[6]    ; 83    ; 5        ; 41           ; 10           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[7]    ; 135   ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[8]    ; 85    ; 5        ; 41           ; 13           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[9]    ; 86    ; 5        ; 41           ; 13           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacLoad      ; 65    ; 4        ; 30           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[0]    ; 100   ; 6        ; 41           ; 18           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[1]    ; 103   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[2]    ; 104   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[3]    ; 105   ; 6        ; 41           ; 23           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[4]    ; 106   ; 6        ; 41           ; 27           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[5]    ; 110   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[6]    ; 111   ; 7        ; 37           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[7]    ; 112   ; 7        ; 35           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; ExtendOut[0] ; 49    ; 3        ; 19           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; ExtendOut[1] ; 50    ; 3        ; 19           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Led          ; 144   ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; PotClk       ; 121   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; PotStart     ; 125   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Prbs         ; 113   ; 7        ; 35           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                                    ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
; Location ; Pin Name                               ; Reserved As              ; User Signal Name        ; Pin Type                  ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
; 6        ; DIFFIO_L4n, DATA1, ASDO                ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
; 8        ; DIFFIO_L6p, FLASH_nCE, nCSO            ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
; 9        ; nSTATUS                                ; -                        ; -                       ; Dedicated Programming Pin ;
; 12       ; DCLK                                   ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
; 13       ; DATA0                                  ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
; 14       ; nCONFIG                                ; -                        ; -                       ; Dedicated Programming Pin ;
; 21       ; nCE                                    ; -                        ; -                       ; Dedicated Programming Pin ;
; 86       ; DIFFIO_R21n, DEV_OE                    ; Use as regular IO        ; DacDat[9]               ; Dual Purpose Pin          ;
; 87       ; DIFFIO_R21p, DEV_CLRn                  ; Use as regular IO        ; DacDat[10]              ; Dual Purpose Pin          ;
; 92       ; CONF_DONE                              ; -                        ; -                       ; Dedicated Programming Pin ;
; 94       ; MSEL0                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; 96       ; MSEL1                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; 97       ; MSEL2                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; 97       ; MSEL3                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; 98       ; DIFFIO_R17n, INIT_DONE                 ; Use as regular IO        ; DacDat[11]              ; Dual Purpose Pin          ;
; 101      ; DIFFIO_R16n, nCEO                      ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
; 103      ; DIFFIO_R16p, CLKUSR                    ; Use as regular IO        ; DigOut[1]               ; Dual Purpose Pin          ;
; 106      ; DIFFIO_R2n, PADD20, DQS2R/CQ3R,CDPCLK5 ; Use as regular IO        ; DigOut[4]               ; Dual Purpose Pin          ;
; 121      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8  ; Use as regular IO        ; PotClk                  ; Dual Purpose Pin          ;
; 125      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO        ; PotStart                ; Dual Purpose Pin          ;
; 132      ; DIFFIO_T12n, DATA2                     ; Use as regular IO        ; DacDat[0]               ; Dual Purpose Pin          ;
; 133      ; DIFFIO_T12p, DATA3                     ; Use as regular IO        ; DacDat[1]               ; Dual Purpose Pin          ;
; 134      ; DIFFIO_T11n, PADD18                    ; Use as regular IO        ; DacDat[2]               ; Dual Purpose Pin          ;
; 135      ; DIFFIO_T11p, DATA4                     ; Use as regular IO        ; DacDat[7]               ; Dual Purpose Pin          ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+


+-------------------------------------------------------------+
; I/O Bank Usage                                              ;
+----------+-------------------+---------------+--------------+
; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1        ; 5 / 8 ( 63 % )    ; 3.3V          ; --           ;
; 2        ; 2 / 7 ( 29 % )    ; 3.3V          ; --           ;
; 3        ; 10 / 10 ( 100 % ) ; 3.3V          ; --           ;
; 4        ; 13 / 14 ( 93 % )  ; 3.3V          ; --           ;
; 5        ; 7 / 9 ( 78 % )    ; 3.3V          ; --           ;
; 6        ; 7 / 10 ( 70 % )   ; 3.3V          ; --           ;
; 7        ; 7 / 12 ( 58 % )   ; 3.3V          ; --           ;
; 8        ; 5 / 12 ( 42 % )   ; 3.3V          ; --           ;
+----------+-------------------+---------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                                        ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1        ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 2        ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 3        ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 4        ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 5        ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 6        ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; On           ;
; 7        ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 8        ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; On           ;
; 9        ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 10       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 11       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 12       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; On           ;
; 13       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; On           ;
; 14       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 15       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 16       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 17       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 18       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 19       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 20       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
; 21       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 22       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 23       ; 39         ; 1        ; Clk100                                                    ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 24       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 25       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 26       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 27       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 28       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 29       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 30       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 31       ; 72         ; 2        ; DigIn[0]                                                  ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 32       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 33       ; 78         ; 2        ; Master                                                    ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 34       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 35       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 36       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 37       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 38       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 39       ; 96         ; 3        ; DigIn[1]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 40       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 41       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 42       ; 101        ; 3        ; DigIn[2]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 43       ; 102        ; 3        ; DigIn[3]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 44       ; 103        ; 3        ; DigIn[4]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 45       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 46       ; 119        ; 3        ; DigIn[5]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 47       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 48       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 49       ; 128        ; 3        ; ExtendOut[0]                                              ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 50       ; 131        ; 3        ; ExtendOut[1]                                              ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 51       ; 132        ; 3        ; ExtendIn[1]                                               ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 52       ; 134        ; 3        ; ExtendIn[0]                                               ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 53       ; 135        ; 3        ; AC60Hz                                                    ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 54       ; 136        ; 4        ; DigIn[6]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 55       ; 137        ; 4        ; DigIn[7]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 56       ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 57       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 58       ; 143        ; 4        ; Adc2                                                      ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 59       ; 145        ; 4        ; DacAddr[0]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 60       ; 146        ; 4        ; DacAddr[1]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 61       ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 62       ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 63       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 64       ; 154        ; 4        ; DacCs                                                     ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 65       ; 155        ; 4        ; DacLoad                                                   ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 66       ; 164        ; 4        ; AdcStart                                                  ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 67       ; 165        ; 4        ; AdcCs                                                     ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 68       ; 167        ; 4        ; AdcClk                                                    ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 69       ; 168        ; 4        ; Adc1                                                      ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 70       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 71       ; 171        ; 4        ; Adc3                                                      ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 72       ; 172        ; 4        ; Adc4                                                      ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 73       ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 74       ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 75       ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 76       ; 181        ; 5        ; DacDat[3]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 77       ; 182        ; 5        ; DacDat[4]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 78       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 79       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 80       ; 194        ; 5        ; DacDat[5]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 81       ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 82       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 83       ; 208        ; 5        ; DacDat[6]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 84       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 85       ; 215        ; 5        ; DacDat[8]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 86       ; 216        ; 5        ; DacDat[9]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 87       ; 217        ; 5        ; DacDat[10]                                                ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 88       ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 89       ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 90       ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 91       ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 92       ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 93       ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 94       ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 95       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 96       ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 97       ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 97       ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 98       ; 234        ; 6        ; DacDat[11]                                                ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 99       ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 100      ; 237        ; 6        ; DigOut[0]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 101      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; Off          ;
; 102      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 103      ; 240        ; 6        ; DigOut[1]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 104      ; 241        ; 6        ; DigOut[2]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 105      ; 257        ; 6        ; DigOut[3]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 106      ; 270        ; 6        ; DigOut[4]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 107      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 108      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 109      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 110      ; 279        ; 7        ; DigOut[5]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 111      ; 281        ; 7        ; DigOut[6]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 112      ; 284        ; 7        ; DigOut[7]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 113      ; 285        ; 7        ; Prbs                                                      ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 114      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 115      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 116      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 117      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 118      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 119      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 120      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 121      ; 306        ; 7        ; PotClk                                                    ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 122      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 123      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 124      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 125      ; 315        ; 7        ; PotStart                                                  ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 126      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 127      ; 320        ; 7        ; PotDat                                                    ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 128      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 129      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 130      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 131      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 132      ; 332        ; 8        ; DacDat[0]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 133      ; 333        ; 8        ; DacDat[1]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 134      ; 334        ; 8        ; DacDat[2]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 135      ; 335        ; 8        ; DacDat[7]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 136      ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 137      ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 138      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 139      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 140      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 141      ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 142      ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 143      ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 144      ; 363        ; 8        ; Led                                                       ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; EPAD     ;            ;          ; GND                                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+-------------------+
; Migration Devices ;
+-------------------+
; Migration Device  ;
+-------------------+
; EP4CE15E22C7      ;
; EP4CE15E22C8      ;
; EP4CE15E22I7      ;
+-------------------+


+----------------------------------------------------------------------------------------------------------+
; PLL Summary                                                                                              ;
+-------------------------------+--------------------------------------------------------------------------+
; Name                          ; altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|pll1 ;
+-------------------------------+--------------------------------------------------------------------------+
; SDC pin name                  ; 60MHz|altpll_component|auto_generated|pll1                               ;
; PLL mode                      ; Normal                                                                   ;
; Compensate clock              ; clock0                                                                   ;
; Compensated input/output pins ; --                                                                       ;
; Switchover type               ; --                                                                       ;
; Input frequency 0             ; 100.0 MHz                                                                ;
; Input frequency 1             ; --                                                                       ;
; Nominal PFD frequency         ; 100.0 MHz                                                                ;
; Nominal VCO frequency         ; 600.0 MHz                                                                ;
; VCO post scale K counter      ; 2                                                                        ;
; VCO frequency control         ; Auto                                                                     ;
; VCO phase shift step          ; 208 ps                                                                   ;
; VCO multiply                  ; --                                                                       ;
; VCO divide                    ; --                                                                       ;
; Freq min lock                 ; 50.01 MHz                                                                ;
; Freq max lock                 ; 108.37 MHz                                                               ;
; M VCO Tap                     ; 0                                                                        ;
; M Initial                     ; 1                                                                        ;
; M value                       ; 6                                                                        ;
; N value                       ; 1                                                                        ;
; Charge pump current           ; setting 1                                                                ;
; Loop filter resistance        ; setting 27                                                               ;
; Loop filter capacitance       ; setting 0                                                                ;
; Bandwidth                     ; 1.03 MHz to 1.97 MHz                                                     ;
; Bandwidth type                ; Medium                                                                   ;
; Real time reconfigurable      ; Off                                                                      ;
; Scan chain MIF file           ; --                                                                       ;
; Preserve PLL counter order    ; Off                                                                      ;
; PLL location                  ; PLL_1                                                                    ;
; Inclk0 signal                 ; Clk100                                                                   ;
; Inclk1 signal                 ; --                                                                       ;
; Inclk0 signal type            ; Dedicated Pin                                                            ;
; Inclk1 signal type            ; --                                                                       ;
+-------------------------------+--------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage                                                                                                                                                                                                                                                                                                        ;
+--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------+
; Name                                                                                 ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                      ;
+--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------+
; altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] ; clock0       ; 3    ; 5   ; 60.0 MHz         ; 0 (0 ps)    ; 4.50 (208 ps)    ; 50/50      ; C0      ; 10            ; 5/5 Even   ; --            ; 1       ; 0       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                            ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                   ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                ; Library Name ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |ACync_block                                 ; 1152 (1)    ; 581 (0)                   ; 0 (0)         ; 458752      ; 56   ; 0            ; 0       ; 0         ; 51   ; 0            ; 571 (1)      ; 213 (0)           ; 368 (0)          ; |ACync_block                                                                                                                       ; work         ;
;    |FifoA:FifoAnalog|                        ; 189 (0)     ; 146 (0)                   ; 0 (0)         ; 196608      ; 24   ; 0            ; 0       ; 0         ; 0    ; 0            ; 43 (0)       ; 70 (0)            ; 76 (0)           ; |ACync_block|FifoA:FifoAnalog                                                                                                      ; work         ;
;       |dcfifo:dcfifo_component|              ; 189 (0)     ; 146 (0)                   ; 0 (0)         ; 196608      ; 24   ; 0            ; 0       ; 0         ; 0    ; 0            ; 43 (0)       ; 70 (0)            ; 76 (0)           ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component                                                                              ; work         ;
;          |dcfifo_s1l1:auto_generated|        ; 189 (60)    ; 146 (56)                  ; 0 (0)         ; 196608      ; 24   ; 0            ; 0       ; 0         ; 0    ; 0            ; 43 (4)       ; 70 (35)           ; 76 (3)           ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated                                                   ; work         ;
;             |a_graycounter_4lc:wrptr_g1p|    ; 36 (36)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 18 (18)      ; 1 (1)             ; 17 (17)          ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p                       ; work         ;
;             |a_graycounter_877:rdptr_g1p|    ; 34 (34)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 3 (3)             ; 21 (21)          ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p                       ; work         ;
;             |alt_synch_pipe_tld:rs_dgwp|     ; 26 (0)      ; 26 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (0)            ; 14 (0)           ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp                        ; work         ;
;                |dffpipe_se9:dffpipe12|       ; 26 (26)     ; 26 (26)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (12)           ; 14 (14)          ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12  ; work         ;
;             |alt_synch_pipe_uld:ws_dgrp|     ; 26 (0)      ; 26 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (0)            ; 7 (0)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp                        ; work         ;
;                |dffpipe_te9:dffpipe15|       ; 26 (26)     ; 26 (26)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (19)           ; 7 (7)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15  ; work         ;
;             |altsyncram_sm31:fifo_ram|       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 196608      ; 24   ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram                          ; work         ;
;             |cmpr_c66:rdempty_eq_comp1_msb|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_c66:rdempty_eq_comp1_msb                     ; work         ;
;             |cmpr_q76:rdfull_eq_comp|        ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_q76:rdfull_eq_comp                           ; work         ;
;             |mux_j28:rdemp_eq_comp_lsb_mux|  ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 8 (8)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux                     ; work         ;
;             |mux_j28:rdemp_eq_comp_msb_mux|  ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 6 (6)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux                     ; work         ;
;             |mux_j28:wrfull_eq_comp_lsb_mux| ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 9 (9)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux                    ; work         ;
;             |mux_j28:wrfull_eq_comp_msb_mux| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 4 (4)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux                    ; work         ;
;    |FifoD:FifoDigital|                       ; 261 (0)     ; 183 (0)                   ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 78 (0)       ; 91 (0)            ; 92 (0)           ; |ACync_block|FifoD:FifoDigital                                                                                                     ; work         ;
;       |dcfifo:dcfifo_component|              ; 261 (0)     ; 183 (0)                   ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 78 (0)       ; 91 (0)            ; 92 (0)           ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component                                                                             ; work         ;
;          |dcfifo_h0l1:auto_generated|        ; 261 (72)    ; 183 (69)                  ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 78 (3)       ; 91 (48)           ; 92 (4)           ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated                                                  ; work         ;
;             |a_graycounter_7lc:wrptr_g1p|    ; 43 (43)     ; 21 (21)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 18 (18)      ; 0 (0)             ; 25 (25)          ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p                      ; work         ;
;             |a_graycounter_b77:rdptr_g1p|    ; 39 (39)     ; 23 (23)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (13)      ; 1 (1)             ; 25 (25)          ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p                      ; work         ;
;             |alt_synch_pipe_0md:rs_dgwp|     ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (0)            ; 13 (0)           ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp                       ; work         ;
;                |dffpipe_ve9:dffpipe14|       ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (19)           ; 13 (13)          ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14 ; work         ;
;             |alt_synch_pipe_1md:ws_dgrp|     ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 20 (0)            ; 12 (0)           ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp                       ; work         ;
;                |dffpipe_0f9:dffpipe17|       ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 20 (20)           ; 12 (12)          ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17 ; work         ;
;             |altsyncram_qj31:fifo_ram|       ; 30 (6)      ; 6 (6)                     ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 21 (0)       ; 3 (3)             ; 6 (3)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram                         ; work         ;
;                |decode_d87:decode12|         ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 3 (3)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12     ; work         ;
;                |mux_t28:mux13|               ; 16 (16)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 0 (0)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|mux_t28:mux13           ; work         ;
;             |cmpr_t76:rdfull_eq_comp|        ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 8 (8)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp                          ; work         ;
;             |mux_j28:rdemp_eq_comp_lsb_mux|  ; 12 (12)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 7 (7)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux                    ; work         ;
;             |mux_j28:rdemp_eq_comp_msb_mux|  ; 12 (12)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 6 (6)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux                    ; work         ;
;             |mux_j28:wrfull_eq_comp_lsb_mux| ; 11 (11)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 7 (7)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux                   ; work         ;
;             |mux_j28:wrfull_eq_comp_msb_mux| ; 11 (11)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 5 (5)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux                   ; work         ;
;    |altpll0:60MHz|                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ACync_block|altpll0:60MHz                                                                                                         ; work         ;
;       |altpll:altpll_component|              ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ACync_block|altpll0:60MHz|altpll:altpll_component                                                                                 ; work         ;
;          |altpll0_altpll:auto_generated|     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ACync_block|altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated                                                   ; work         ;
;    |uberACync:Sink|                          ; 701 (701)   ; 252 (252)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 449 (449)    ; 52 (52)           ; 200 (200)        ; |ACync_block|uberACync:Sink                                                                                                        ; work         ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                          ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+
; Name         ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+
; Prbs         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; AdcClk       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; AdcCs        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; AdcStart     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacLoad      ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacCs        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; PotClk       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; PotStart     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Led          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacAddr[1]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacAddr[0]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[11]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[10]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[9]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[8]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[7]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[6]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[5]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[4]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[3]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[2]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[1]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[0]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[7]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[6]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[5]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[4]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[3]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[2]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[1]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[0]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; ExtendOut[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; ExtendOut[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Clk100       ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; ExtendIn[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; ExtendIn[1]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Master       ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Adc3         ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; Adc2         ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Adc1         ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Adc4         ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[7]     ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; DigIn[6]     ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; DigIn[5]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[4]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[3]     ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; DigIn[2]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[1]     ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; DigIn[0]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; AC60Hz       ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; PotDat       ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+


+---------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                            ;
+---------------------------------------------+-------------------+---------+
; Source Pin / Fanout                         ; Pad To Core Index ; Setting ;
+---------------------------------------------+-------------------+---------+
; Clk100                                      ;                   ;         ;
; ExtendIn[0]                                 ;                   ;         ;
; ExtendIn[1]                                 ;                   ;         ;
;      - uberACync:Sink|ExtendInBuf[1]        ; 0                 ; 6       ;
; Master                                      ;                   ;         ;
;      - uberACync:Sink|MasterBuf             ; 0                 ; 6       ;
; Adc3                                        ;                   ;         ;
;      - uberACync:Sink|FifoOutAna[35]        ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[27]        ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[26]        ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[25]        ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[29]~feeder ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[33]~feeder ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[34]~feeder ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[24]~feeder ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[32]~feeder ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[31]~feeder ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[30]~feeder ; 1                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[28]~feeder ; 1                 ; 6       ;
; Adc2                                        ;                   ;         ;
;      - uberACync:Sink|FifoOutAna[23]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[20]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[19]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[17]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[15]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[14]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[12]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[13]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[21]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[22]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[18]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[16]~feeder ; 0                 ; 6       ;
; Adc1                                        ;                   ;         ;
;      - uberACync:Sink|FifoOutAna[11]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[10]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[9]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[8]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[7]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[6]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[5]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[4]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[3]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[2]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[1]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[0]~feeder  ; 0                 ; 6       ;
; Adc4                                        ;                   ;         ;
;      - uberACync:Sink|FifoOutAna[47]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[46]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[45]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[44]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[43]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[42]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[41]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[40]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[39]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[38]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[37]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[36]        ; 0                 ; 6       ;
; DigIn[7]                                    ;                   ;         ;
; DigIn[6]                                    ;                   ;         ;
; DigIn[5]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[5]           ; 0                 ; 6       ;
; DigIn[4]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[4]~feeder    ; 0                 ; 6       ;
; DigIn[3]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[3]~feeder    ; 1                 ; 6       ;
; DigIn[2]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[2]~feeder    ; 0                 ; 6       ;
; DigIn[1]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[1]~feeder    ; 1                 ; 6       ;
; DigIn[0]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[0]~feeder    ; 0                 ; 6       ;
; AC60Hz                                      ;                   ;         ;
; PotDat                                      ;                   ;         ;
+---------------------------------------------+-------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                                                                                                             ;
+----------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; Name                                                                                                                             ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+----------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; Clk100                                                                                                                           ; PIN_23             ; 1       ; Clock                      ; no     ; --                   ; --               ; --                        ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|int_rdempty                                                  ; LCCOMB_X21_Y14_N28 ; 50      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|valid_wrreq                                                  ; LCCOMB_X22_Y14_N20 ; 51      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode651w[2] ; LCCOMB_X21_Y21_N30 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode664w[2] ; LCCOMB_X21_Y21_N8  ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode672w[2] ; LCCOMB_X21_Y21_N28 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode680w[2] ; LCCOMB_X21_Y21_N16 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_NEW_REG16_RTM018                                ; LCCOMB_X19_Y17_N26 ; 56      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|valid_wrreq                                                 ; LCCOMB_X21_Y21_N26 ; 30      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0]                                             ; PLL_1              ; 252     ; Clock                      ; yes    ; Global Clock         ; GCLK3            ; --                        ;
; uberACync:Sink|CtrAna[7]~26                                                                                                      ; LCCOMB_X29_Y13_N6  ; 9       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|CtrDig[5]~18                                                                                                      ; LCCOMB_X30_Y15_N0  ; 9       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|DacDat[2]~101                                                                                                     ; LCCOMB_X28_Y15_N28 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|DacDat[9]~73                                                                                                      ; LCCOMB_X26_Y15_N4  ; 9       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|DelayTimer[4]~64                                                                                                  ; LCCOMB_X17_Y17_N22 ; 21      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|DigOut[2]~1                                                                                                       ; LCCOMB_X29_Y14_N26 ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|Equal6~4                                                                                                          ; LCCOMB_X16_Y23_N18 ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoAnaRdClk                                                                                                      ; FF_X29_Y15_N3      ; 98      ; Clock                      ; yes    ; Global Clock         ; GCLK8            ; --                        ;
; uberACync:Sink|FifoAnaWrClk                                                                                                      ; FF_X29_Y15_N1      ; 96      ; Clock                      ; yes    ; Global Clock         ; GCLK9            ; --                        ;
; uberACync:Sink|FifoDigRdClk                                                                                                      ; FF_X31_Y15_N3      ; 128     ; Clock                      ; yes    ; Global Clock         ; GCLK5            ; --                        ;
; uberACync:Sink|FifoDigWrClk                                                                                                      ; FF_X31_Y15_N13     ; 119     ; Clock                      ; yes    ; Global Clock         ; GCLK7            ; --                        ;
; uberACync:Sink|FifoOutAna[0]~17                                                                                                  ; LCCOMB_X26_Y13_N4  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[10]~7                                                                                                  ; LCCOMB_X28_Y14_N0  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[14]~15                                                                                                 ; LCCOMB_X26_Y13_N10 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[19]~18                                                                                                 ; LCCOMB_X27_Y12_N26 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[1]~16                                                                                                  ; LCCOMB_X28_Y14_N30 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[20]~9                                                                                                  ; LCCOMB_X28_Y14_N18 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[39]~14                                                                                                 ; LCCOMB_X27_Y14_N28 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[41]~19                                                                                                 ; LCCOMB_X27_Y12_N4  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[45]~8                                                                                                  ; LCCOMB_X27_Y14_N10 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[47]~6                                                                                                  ; LCCOMB_X28_Y14_N12 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[4]~13                                                                                                  ; LCCOMB_X28_Y14_N4  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[6]~11                                                                                                  ; LCCOMB_X28_Y14_N24 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifosClear                                                                                                        ; FF_X1_Y14_N5       ; 3       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifosClear                                                                                                        ; FF_X1_Y14_N5       ; 381     ; Async. clear               ; yes    ; Global Clock         ; GCLK2            ; --                        ;
; uberACync:Sink|LessThan6~3                                                                                                       ; LCCOMB_X23_Y28_N2  ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|PhaseDelayTime[8]~2                                                                                               ; LCCOMB_X17_Y23_N26 ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|PrbsShift[1]~1                                                                                                    ; LCCOMB_X23_Y28_N4  ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|RetriggerInhibit[11]~23                                                                                           ; LCCOMB_X17_Y17_N4  ; 21      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateMode.000                                                                                                     ; FF_X28_Y13_N21     ; 24      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateMode.010                                                                                                     ; FF_X29_Y14_N19     ; 22      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateMode.110                                                                                                     ; FF_X29_Y14_N1      ; 46      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateZero.00                                                                                                      ; FF_X17_Y17_N19     ; 25      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateZero.01                                                                                                      ; FF_X17_Y17_N27     ; 27      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|WideOr10                                                                                                          ; LCCOMB_X29_Y13_N0  ; 11      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+----------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                                                                                                  ;
+--------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name                                                                                 ; Location       ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1          ; 252     ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
; uberACync:Sink|FifoAnaRdClk                                                          ; FF_X29_Y15_N3  ; 98      ; 0                                    ; Global Clock         ; GCLK8            ; --                        ;
; uberACync:Sink|FifoAnaWrClk                                                          ; FF_X29_Y15_N1  ; 96      ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
; uberACync:Sink|FifoDigRdClk                                                          ; FF_X31_Y15_N3  ; 128     ; 0                                    ; Global Clock         ; GCLK5            ; --                        ;
; uberACync:Sink|FifoDigWrClk                                                          ; FF_X31_Y15_N13 ; 119     ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
; uberACync:Sink|FifosClear                                                            ; FF_X1_Y14_N5   ; 381     ; 0                                    ; Global Clock         ; GCLK2            ; --                        ;
+--------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                                                                                            ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Name                                                                                                                                             ; Fan-Out ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; uberACync:Sink|CtrAna[5]                                                                                                                         ; 87      ;
; uberACync:Sink|CtrAna[3]                                                                                                                         ; 85      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|valid_wrreq                                                                  ; 75      ;
; uberACync:Sink|CtrAna[0]                                                                                                                         ; 64      ;
; uberACync:Sink|CtrAna[1]                                                                                                                         ; 62      ;
; uberACync:Sink|CtrAna[2]                                                                                                                         ; 59      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_NEW_REG16_RTM018                                                ; 56      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|int_rdempty                                                                  ; 50      ;
; uberACync:Sink|StateMode.110                                                                                                                     ; 46      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                                      ; 43      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                                      ; 41      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                                      ; 41      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                                      ; 41      ;
; uberACync:Sink|CtrAna[4]                                                                                                                         ; 41      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                                      ; 40      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                                      ; 40      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                                      ; 40      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                                     ; 39      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                                     ; 39      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                                      ; 39      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                                      ; 39      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                                     ; 38      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                                 ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                                 ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                                 ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[6]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                                  ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                                       ; 33      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                                       ; 33      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                                       ; 33      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty~_wirecell                                                       ; 32      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0~_wirecell                            ; 32      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                                       ; 32      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                                       ; 32      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                                       ; 31      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                                       ; 31      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                                       ; 31      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|valid_wrreq                                                                 ; 30      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                                       ; 30      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                                      ; 29      ;
; uberACync:Sink|StateZero.01                                                                                                                      ; 27      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[10]                                                                  ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[9]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[8]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[7]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[6]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[5]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[4]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[3]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[2]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[1]                                                                   ; 26      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[0]                                                                   ; 26      ;
; uberACync:Sink|StateZero.00                                                                                                                      ; 25      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|int_rdempty~_wirecell                                                        ; 24      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0~_wirecell                             ; 24      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|ram_address_b[11]                                                            ; 24      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|ram_address_a[11]                                                            ; 24      ;
; uberACync:Sink|StateMode.000                                                                                                                     ; 24      ;
; uberACync:Sink|CtrPot[1]                                                                                                                         ; 23      ;
; uberACync:Sink|CtrPot[0]                                                                                                                         ; 22      ;
; uberACync:Sink|Selector95~2                                                                                                                      ; 22      ;
; uberACync:Sink|StateMode.010                                                                                                                     ; 22      ;
; uberACync:Sink|RetriggerInhibit[11]~23                                                                                                           ; 21      ;
; uberACync:Sink|DelayTimer[4]~64                                                                                                                  ; 21      ;
; uberACync:Sink|CtrPot[3]                                                                                                                         ; 21      ;
; uberACync:Sink|CtrPot[4]                                                                                                                         ; 20      ;
; uberACync:Sink|StateMode.100                                                                                                                     ; 20      ;
; uberACync:Sink|DacDat[0]                                                                                                                         ; 20      ;
; uberACync:Sink|Equal6~4                                                                                                                          ; 19      ;
; uberACync:Sink|CtrPot[7]                                                                                                                         ; 19      ;
; uberACync:Sink|CtrPot[2]                                                                                                                         ; 18      ;
; ~GND                                                                                                                                             ; 17      ;
; uberACync:Sink|CtrAna[6]                                                                                                                         ; 17      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode680w[2]                 ; 16      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode651w[2]                 ; 16      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode672w[2]                 ; 16      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode664w[2]                 ; 16      ;
; uberACync:Sink|LessThan6~3                                                                                                                       ; 16      ;
; uberACync:Sink|PrbsShift[1]~1                                                                                                                    ; 16      ;
; uberACync:Sink|DacDat[11]                                                                                                                        ; 15      ;
; uberACync:Sink|CtrAna[8]                                                                                                                         ; 14      ;
; uberACync:Sink|CtrAna[7]                                                                                                                         ; 14      ;
; Adc4~input                                                                                                                                       ; 12      ;
; Adc1~input                                                                                                                                       ; 12      ;
; Adc2~input                                                                                                                                       ; 12      ;
; Adc3~input                                                                                                                                       ; 12      ;
; uberACync:Sink|PhaseDelayTime[8]~2                                                                                                               ; 12      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                                       ; 12      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1]                               ; 12      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0]                               ; 12      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                                         ; 11      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                                      ; 11      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                                      ; 11      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                                       ; 11      ;
; uberACync:Sink|WideOr10                                                                                                                          ; 11      ;
; uberACync:Sink|StateMode.011                                                                                                                     ; 11      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                                      ; 10      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                                      ; 10      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                                      ; 10      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                                       ; 10      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                                      ; 10      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                                       ; 10      ;
; uberACync:Sink|Selector95~3                                                                                                                      ; 10      ;
; uberACync:Sink|DacDat[9]~46                                                                                                                      ; 10      ;
; uberACync:Sink|DacDat[9]~39                                                                                                                      ; 10      ;
; uberACync:Sink|DacDat[9]~35                                                                                                                      ; 10      ;
; uberACync:Sink|CtrPot[5]                                                                                                                         ; 10      ;
; uberACync:Sink|CtrPot[6]                                                                                                                         ; 10      ;
; PotDat~input                                                                                                                                     ; 9       ;
; uberACync:Sink|DacDat[9]~105                                                                                                                     ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                                      ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                                      ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                                      ; 9       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                                       ; 9       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                                       ; 9       ;
; uberACync:Sink|CtrDig[5]~18                                                                                                                      ; 9       ;
; uberACync:Sink|CtrAna[7]~26                                                                                                                      ; 9       ;
; uberACync:Sink|DacDat[9]~73                                                                                                                      ; 9       ;
; uberACync:Sink|DacDat[9]~48                                                                                                                      ; 9       ;
; uberACync:Sink|DacDat[9]~43                                                                                                                      ; 9       ;
; uberACync:Sink|DacDat[3]                                                                                                                         ; 9       ;
; uberACync:Sink|CtrDig[1]                                                                                                                         ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                                         ; 8       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                                          ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                                     ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                                     ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                                      ; 8       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                                       ; 8       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                                       ; 8       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                                       ; 8       ;
; uberACync:Sink|DigOut[2]~1                                                                                                                       ; 8       ;
; uberACync:Sink|DacDat[9]~33                                                                                                                      ; 8       ;
; uberACync:Sink|DacDat[2]~26                                                                                                                      ; 8       ;
; uberACync:Sink|DacDat[1]                                                                                                                         ; 8       ;
; uberACync:Sink|CtrDig[2]                                                                                                                         ; 8       ;
; uberACync:Sink|CtrDig[0]                                                                                                                         ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                                         ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                                     ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                                     ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                                      ; 7       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                                          ; 7       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                                       ; 7       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                                       ; 7       ;
; uberACync:Sink|DacDat[2]                                                                                                                         ; 7       ;
; uberACync:Sink|DacDat[8]                                                                                                                         ; 7       ;
; uberACync:Sink|DacDat[9]                                                                                                                         ; 7       ;
; uberACync:Sink|DacDat[10]                                                                                                                        ; 7       ;
; uberACync:Sink|AdcClk                                                                                                                            ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15~0                                   ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14~0                                   ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1                                             ; 6       ;
; uberACync:Sink|PreloadDig[0]                                                                                                                     ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                                     ; 6       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                                      ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                                  ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp|aneb_result_wire[0]~9                               ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp|aneb_result_wire[0]~4                               ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                                  ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                                 ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[15]                                                                 ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[13]                                                                 ; 6       ;
; uberACync:Sink|FifoOutAna[47]~5                                                                                                                  ; 6       ;
; uberACync:Sink|LessThan1~1                                                                                                                       ; 6       ;
; uberACync:Sink|DacDat[9]~28                                                                                                                      ; 6       ;
; uberACync:Sink|ExtendInBuf[1]                                                                                                                    ; 6       ;
; uberACync:Sink|ExtendInBuf[0]                                                                                                                    ; 6       ;
; uberACync:Sink|Selector198~0                                                                                                                     ; 6       ;
; uberACync:Sink|DacDat[4]                                                                                                                         ; 6       ;
; uberACync:Sink|DacDat[5]                                                                                                                         ; 6       ;
; uberACync:Sink|DacDat[6]                                                                                                                         ; 6       ;
; uberACync:Sink|DacDat[7]                                                                                                                         ; 6       ;
; uberACync:Sink|PotClk                                                                                                                            ; 6       ;
; uberACync:Sink|DacCs                                                                                                                             ; 6       ;
; uberACync:Sink|PotBuf[9]                                                                                                                         ; 5       ;
; uberACync:Sink|PreloadDig[1]                                                                                                                     ; 5       ;
; uberACync:Sink|AcLineBuf                                                                                                                         ; 5       ;
; uberACync:Sink|FifoOutAna[4]~12                                                                                                                  ; 5       ;
; uberACync:Sink|DigInBuf[0]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[1]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[2]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[3]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[4]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[5]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[6]                                                                                                                       ; 5       ;
; uberACync:Sink|Decoder0~1                                                                                                                        ; 5       ;
; uberACync:Sink|DigInBuf[7]                                                                                                                       ; 5       ;
; uberACync:Sink|Decoder1~1                                                                                                                        ; 5       ;
; uberACync:Sink|LessThan2~1                                                                                                                       ; 5       ;
; uberACync:Sink|LessThan3~3                                                                                                                       ; 5       ;
; uberACync:Sink|DacDat[2]~25                                                                                                                      ; 5       ;
; uberACync:Sink|PotBuf[6]~0                                                                                                                       ; 5       ;
; uberACync:Sink|FifoOutAna[41]~19                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[19]~18                                                                                                                 ; 4       ;
; uberACync:Sink|Selector95~40                                                                                                                     ; 4       ;
; uberACync:Sink|Selector213~1                                                                                                                     ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2                                              ; 4       ;
; uberACync:Sink|Selector44~2                                                                                                                      ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~7                                             ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5                                             ; 4       ;
; uberACync:Sink|PreloadDig[2]                                                                                                                     ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]                 ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                                     ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                                     ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12~0                                    ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11~0                                    ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5                                              ; 4       ;
; uberACync:Sink|PreloadAna[1]                                                                                                                     ; 4       ;
; uberACync:Sink|PreloadAna[0]                                                                                                                     ; 4       ;
; uberACync:Sink|PreloadAna[2]                                                                                                                     ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                                      ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                                      ; 4       ;
; uberACync:Sink|StateZero.10                                                                                                                      ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                                       ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                                       ; 4       ;
; uberACync:Sink|FifoOutAna[0]~17                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[1]~16                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[14]~15                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[39]~14                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[4]~13                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[6]~11                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[20]~9                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[45]~8                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[10]~7                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[47]~6                                                                                                                  ; 4       ;
; uberACync:Sink|CtrDig[5]~9                                                                                                                       ; 4       ;
; uberACync:Sink|DacDat[2]~85                                                                                                                      ; 4       ;
; uberACync:Sink|LessThan4~3                                                                                                                       ; 4       ;
; uberACync:Sink|DacDat[9]~40                                                                                                                      ; 4       ;
; uberACync:Sink|MasterBuf                                                                                                                         ; 4       ;
; uberACync:Sink|PhaseDelayTime[8]~0                                                                                                               ; 4       ;
; uberACync:Sink|Decoder1~0                                                                                                                        ; 4       ;
; uberACync:Sink|FifoOutAna[47]~4                                                                                                                  ; 4       ;
; uberACync:Sink|WideOr42~0                                                                                                                        ; 4       ;
; uberACync:Sink|AdcCs                                                                                                                             ; 4       ;
; uberACync:Sink|DelayTimer[0]                                                                                                                     ; 4       ;
; uberACync:Sink|CtrPrbs[15]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[14]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[10]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[9]                                                                                                                        ; 4       ;
; uberACync:Sink|CtrPrbs[6]                                                                                                                        ; 4       ;
; uberACync:Sink|CtrPrbs[5]                                                                                                                        ; 4       ;
; uberACync:Sink|CtrPrbs[11]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[12]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[13]                                                                                                                       ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13                              ; 3       ;
; uberACync:Sink|PotBuf[0]~14                                                                                                                      ; 3       ;
; uberACync:Sink|PotBuf[1]~11                                                                                                                      ; 3       ;
; uberACync:Sink|Selector213~0                                                                                                                     ; 3       ;
; uberACync:Sink|PotBuf[8]                                                                                                                         ; 3       ;
; uberACync:Sink|PotBuf[7]                                                                                                                         ; 3       ;
; uberACync:Sink|PotBuf[4]                                                                                                                         ; 3       ;
; uberACync:Sink|PotBuf[11]                                                                                                                        ; 3       ;
; uberACync:Sink|PotBuf[10]                                                                                                                        ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~2                                             ; 3       ;
; uberACync:Sink|Selector44~4                                                                                                                      ; 3       ;
; uberACync:Sink|StateZero.11                                                                                                                      ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~1                                             ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14]                ; 3       ;
; uberACync:Sink|Selector131~0                                                                                                                     ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11]                 ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12]                 ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10]                 ; 3       ;
; uberACync:Sink|Selector44~0                                                                                                                      ; 3       ;
; uberACync:Sink|DelayTimer[4]~27                                                                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                                 ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[11]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[12]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdemp_eq_comp_msb_aeb                                                        ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                                        ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_q76:rdfull_eq_comp|aneb_result_wire[0]~7                                ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[1]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[0]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[3]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[2]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[5]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_q76:rdfull_eq_comp|aneb_result_wire[0]~4                                ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[4]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[7]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[6]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[9]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[11]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[8]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[12]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[10]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                                   ; 3       ;
; uberACync:Sink|Selector56~2                                                                                                                      ; 3       ;
; uberACync:Sink|Selector98~5                                                                                                                      ; 3       ;
; uberACync:Sink|AtZeroCrossing                                                                                                                    ; 3       ;
; uberACync:Sink|always1~0                                                                                                                         ; 3       ;
; uberACync:Sink|Selector95~23                                                                                                                     ; 3       ;
; uberACync:Sink|DacDat[2]~95                                                                                                                      ; 3       ;
; uberACync:Sink|DacDat[2]~84                                                                                                                      ; 3       ;
; uberACync:Sink|DacDat[2]~81                                                                                                                      ; 3       ;
; uberACync:Sink|DacDat[2]~77                                                                                                                      ; 3       ;
; uberACync:Sink|Selector147~0                                                                                                                     ; 3       ;
; uberACync:Sink|DacDat[9]~45                                                                                                                      ; 3       ;
; uberACync:Sink|DacDat[9]~37                                                                                                                      ; 3       ;
; uberACync:Sink|LessThan3~1                                                                                                                       ; 3       ;
; uberACync:Sink|StateMode.101                                                                                                                     ; 3       ;
; uberACync:Sink|Clk3662Hz[0]                                                                                                                      ; 3       ;
; uberACync:Sink|PotClk~4                                                                                                                          ; 3       ;
; uberACync:Sink|Selector83~4                                                                                                                      ; 3       ;
; uberACync:Sink|DacAddr[1]~0                                                                                                                      ; 3       ;
; uberACync:Sink|DacDat[2]~24                                                                                                                      ; 3       ;
; uberACync:Sink|DacLoad                                                                                                                           ; 3       ;
; uberACync:Sink|RetriggerInhibit[20]                                                                                                              ; 3       ;
; uberACync:Sink|CtrDig[5]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[4]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[8]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[7]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[6]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[3]                                                                                                                         ; 3       ;
; uberACync:Sink|Add19~0                                                                                                                           ; 3       ;
; uberACync:Sink|CtrPrbs[7]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[2]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[1]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[0]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[3]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[4]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[8]                                                                                                                        ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_BDD117             ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN112_BDD113             ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN110_BDD111             ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15                              ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11                              ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9                               ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5                              ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3                              ; 2       ;
; uberACync:Sink|DacDat[9]~111                                                                                                                     ; 2       ;
; uberACync:Sink|DacDat[2]~106                                                                                                                     ; 2       ;
; uberACync:Sink|DacDat[9]~104                                                                                                                     ; 2       ;
; uberACync:Sink|PotBuf[5]~22                                                                                                                      ; 2       ;
; uberACync:Sink|PotBuf[6]~7                                                                                                                       ; 2       ;
; uberACync:Sink|PotBuf[10]~2                                                                                                                      ; 2       ;
; uberACync:Sink|PotBuf[6]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[5]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[3]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[2]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[1]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[0]                                                                                                                         ; 2       ;
; uberACync:Sink|PreloadDig~0                                                                                                                      ; 2       ;
; uberACync:Sink|Decoder0~2                                                                                                                        ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~3                                             ; 2       ;
; uberACync:Sink|PreloadAna[2]~1                                                                                                                   ; 2       ;
; uberACync:Sink|Decoder1~2                                                                                                                        ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~6                                              ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~1                                              ; 2       ;
; uberACync:Sink|Selector44~3                                                                                                                      ; 2       ;
; uberACync:Sink|WideOr1~5                                                                                                                         ; 2       ;
; uberACync:Sink|WideOr1~4                                                                                                                         ; 2       ;
; uberACync:Sink|Selector44~1                                                                                                                      ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~9                                             ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~6                              ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9                              ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4                              ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]                 ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~7                                              ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~2                                              ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~1                                              ; 2       ;
; uberACync:Sink|Selector101~0                                                                                                                     ; 2       ;
; uberACync:Sink|WideOr10~0                                                                                                                        ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10]                 ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11]                 ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12]                 ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]                  ; 2       ;
; uberACync:Sink|FifoDigWrClk                                                                                                                      ; 2       ;
; uberACync:Sink|FifoOutAna[20]~10                                                                                                                 ; 2       ;
; uberACync:Sink|FifosClear                                                                                                                        ; 2       ;
; uberACync:Sink|FifoAnaRdClk                                                                                                                      ; 2       ;
; uberACync:Sink|FifoAnaWrClk                                                                                                                      ; 2       ;
; uberACync:Sink|Selector56~1                                                                                                                      ; 2       ;
; uberACync:Sink|Selector56~0                                                                                                                      ; 2       ;
; uberACync:Sink|StateMode.001                                                                                                                     ; 2       ;
; uberACync:Sink|Selector95~22                                                                                                                     ; 2       ;
; uberACync:Sink|Selector95~15                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[12]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[0]                                                                                                                     ; 2       ;
; uberACync:Sink|Selector95~7                                                                                                                      ; 2       ;
; uberACync:Sink|FifoOutAna[36]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[24]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[37]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[1]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[25]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[13]                                                                                                                    ; 2       ;
; uberACync:Sink|DacDat[2]~101                                                                                                                     ; 2       ;
; uberACync:Sink|DacDat[2]~90                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[2]~82                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[2]~80                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[2]~79                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[2]~75                                                                                                                      ; 2       ;
; uberACync:Sink|FifoOutAna[38]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[2]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[26]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[14]                                                                                                                    ; 2       ;
; uberACync:Sink|Selector144~3                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[39]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[3]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[27]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[15]                                                                                                                    ; 2       ;
; uberACync:Sink|Selector144~0                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[40]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[4]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[28]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[16]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[41]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[5]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[29]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[17]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[42]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[6]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[30]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[18]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[43]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[7]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[31]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[19]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[44]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[8]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[32]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[20]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[45]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[9]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[33]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[21]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[46]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[10]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[34]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[22]                                                                                                                    ; 2       ;
; uberACync:Sink|DacDat[2]~62                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[9]~61                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[9]~60                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[9]~55                                                                                                                      ; 2       ;
; uberACync:Sink|LessThan4~1                                                                                                                       ; 2       ;
; uberACync:Sink|LessThan4~0                                                                                                                       ; 2       ;
; uberACync:Sink|DacDat[9]~49                                                                                                                      ; 2       ;
; uberACync:Sink|Selector119~1                                                                                                                     ; 2       ;
; uberACync:Sink|Selector119~0                                                                                                                     ; 2       ;
; uberACync:Sink|DacDat[9]~42                                                                                                                      ; 2       ;
; uberACync:Sink|FifoOutAna[47]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[11]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[23]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[35]                                                                                                                    ; 2       ;
; uberACync:Sink|DacDat[9]~38                                                                                                                      ; 2       ;
; uberACync:Sink|Selector136~0                                                                                                                     ; 2       ;
; uberACync:Sink|LessThan3~2                                                                                                                       ; 2       ;
; uberACync:Sink|LessThan3~0                                                                                                                       ; 2       ;
; uberACync:Sink|DacDat[9]~30                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[9]~29                                                                                                                      ; 2       ;
; uberACync:Sink|DacDat[9]~27                                                                                                                      ; 2       ;
; uberACync:Sink|DacAddr[0]~4                                                                                                                      ; 2       ;
; uberACync:Sink|Selector149~0                                                                                                                     ; 2       ;
; uberACync:Sink|Selector148~2                                                                                                                     ; 2       ;
; uberACync:Sink|Selector148~0                                                                                                                     ; 2       ;
; uberACync:Sink|Selector214~7                                                                                                                     ; 2       ;
; uberACync:Sink|PotClk~5                                                                                                                          ; 2       ;
; uberACync:Sink|Selector83~7                                                                                                                      ; 2       ;
; uberACync:Sink|WideOr40~0                                                                                                                        ; 2       ;
; uberACync:Sink|DacDat[9]~23                                                                                                                      ; 2       ;
; uberACync:Sink|Selector98~4                                                                                                                      ; 2       ;
; uberACync:Sink|Selector134~2                                                                                                                     ; 2       ;
; uberACync:Sink|Selector99~3                                                                                                                      ; 2       ;
; uberACync:Sink|Selector98~0                                                                                                                      ; 2       ;
; uberACync:Sink|LessThan6~0                                                                                                                       ; 2       ;
; uberACync:Sink|PrbsShift[10]                                                                                                                     ; 2       ;
; uberACync:Sink|ExtendOut[0]                                                                                                                      ; 2       ;
; uberACync:Sink|ExtendOut[1]                                                                                                                      ; 2       ;
; uberACync:Sink|DacAddr[0]                                                                                                                        ; 2       ;
; uberACync:Sink|DacAddr[1]                                                                                                                        ; 2       ;
; uberACync:Sink|PotStart                                                                                                                          ; 2       ;
; uberACync:Sink|AdcStart                                                                                                                          ; 2       ;
; uberACync:Sink|RetriggerInhibit[19]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[18]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[17]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[16]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[15]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[14]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[13]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[12]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[11]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[10]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[9]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[8]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[7]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[6]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[5]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[4]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[3]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[2]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[1]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[0]                                                                                                               ; 2       ;
; uberACync:Sink|DelayTimer[16]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[15]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[14]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[13]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[12]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[11]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[10]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[9]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[8]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[7]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[6]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[5]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[4]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[3]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[2]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[1]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[20]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[19]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[18]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[17]                                                                                                                    ; 2       ;
; uberACync:Sink|Add7~4                                                                                                                            ; 2       ;
; uberACync:Sink|Clk3662Hz[13]                                                                                                                     ; 2       ;
; uberACync:Sink|Clk3662Hz[12]                                                                                                                     ; 2       ;
; uberACync:Sink|Clk3662Hz[11]                                                                                                                     ; 2       ;
; uberACync:Sink|Clk3662Hz[10]                                                                                                                     ; 2       ;
; uberACync:Sink|Clk3662Hz[9]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[8]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[7]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[6]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[5]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[4]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[3]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[2]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[1]                                                                                                                      ; 2       ;
; uberACync:Sink|PrbsShift[0]                                                                                                                      ; 2       ;
; uberACync:Sink|StateMode.000~feeder                                                                                                              ; 1       ;
; AC60Hz~input                                                                                                                                     ; 1       ;
; DigIn[0]~input                                                                                                                                   ; 1       ;
; DigIn[1]~input                                                                                                                                   ; 1       ;
; DigIn[2]~input                                                                                                                                   ; 1       ;
; DigIn[3]~input                                                                                                                                   ; 1       ;
; DigIn[4]~input                                                                                                                                   ; 1       ;
; DigIn[5]~input                                                                                                                                   ; 1       ;
; DigIn[6]~input                                                                                                                                   ; 1       ;
; DigIn[7]~input                                                                                                                                   ; 1       ;
; Master~input                                                                                                                                     ; 1       ;
; ExtendIn[1]~input                                                                                                                                ; 1       ;
; ExtendIn[0]~input                                                                                                                                ; 1       ;
; Clk100~input                                                                                                                                     ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_RESYN252_BDD253    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_RESYN250_BDD251    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_RESYN248_BDD249    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_RESYN246_BDD247    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_RESYN244_BDD245      ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_RESYN242_BDD243      ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_RESYN240_BDD241      ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_RESYN238_BDD239      ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_RTM019_RESYN236_BDD237                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_RTM019_RESYN234_BDD235                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9~0_RESYN232_BDD233                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0_RESYN230_BDD231                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0_RESYN228_BDD229                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12~0_RESYN226_BDD227                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|cntr_cout[13]~0_RESYN224_BDD225                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3~0_RESYN222_BDD223                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4~0_RESYN220_BDD221                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14~0_RESYN218_BDD219                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15~0_RESYN216_BDD217                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13~0_RESYN214_BDD215                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~3_RESYN212_BDD213                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~2_RESYN210_BDD211                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1_RESYN208_BDD209                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1_RESYN206_BDD207                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9~0_RESYN204_BDD205                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10~0_RESYN202_BDD203                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12~0_RESYN200_BDD201                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11~0_RESYN198_BDD199                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~6_RESYN196_BDD197                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3~0_RESYN194_BDD195                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6~0_RESYN192_BDD193                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2_RESYN190_BDD191                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2_RESYN188_BDD189                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4~0_RESYN186_BDD187                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~0_RESYN184_BDD185                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~9_RESYN182_BDD183                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~7_RESYN180_BDD181                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5_RESYN178_BDD179                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN176_BDD177              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN174_BDD175              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN172_BDD173              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN170_BDD171              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~8_RESYN168_BDD169                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~7_RESYN166_BDD167                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5_RESYN164_BDD165                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5_RESYN162_BDD163                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN160_BDD161               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN158_BDD159               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN156_BDD157               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN154_BDD155               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN152_BDD153               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9_RESYN150_BDD151               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9_RESYN148_BDD149               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9_RESYN146_BDD147               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9_RESYN144_BDD145               ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode680w[2]_RESYN142_BDD143 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode651w[2]_RESYN140_BDD141 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode672w[2]_RESYN138_BDD139 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode664w[2]_RESYN136_BDD137 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8~0_RESYN134_BDD135                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11~0_RESYN132_BDD133                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2~0_RESYN130_BDD131                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5~0_RESYN128_BDD129                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8~0_RESYN126_BDD127                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5~0_RESYN124_BDD125                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2~0_RESYN122_BDD123                     ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11~0_RESYN120_BDD121                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5_RESYN118_BDD119                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN104_BDD105              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8~0_RESYN102_BDD103                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5~0_RESYN100_BDD101                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~3_RESYN92_BDD93                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN88_BDD89                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN86_BDD87                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_BDD83                ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN78_BDD79                ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN76_BDD77                ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6_OTERM30                                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0_OTERM27                               ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6_OTERM24                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0_OTERM21                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_RTM019                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1                              ; 1       ;
; uberACync:Sink|Led~3_wirecell                                                                                                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]~0                                                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]~0                                                                ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|wrptr_g[0]~0                                                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdptr_g[0]~0                                                                 ; 1       ;
; uberACync:Sink|CtrPot[0]~0                                                                                                                       ; 1       ;
; uberACync:Sink|Clk3662Hz[0]~39                                                                                                                   ; 1       ;
; uberACync:Sink|Selector214~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector214~8                                                                                                                     ; 1       ;
; uberACync:Sink|DacDat[9]~110                                                                                                                     ; 1       ;
; uberACync:Sink|Selector131~5                                                                                                                     ; 1       ;
; uberACync:Sink|Selector131~4                                                                                                                     ; 1       ;
; uberACync:Sink|DacDat[9]~14                                                                                                                      ; 1       ;
; uberACync:Sink|DacDat[9]~109                                                                                                                     ; 1       ;
; uberACync:Sink|DacDat[2]~108                                                                                                                     ; 1       ;
; uberACync:Sink|DacDat[2]~107                                                                                                                     ; 1       ;
; uberACync:Sink|Selector145~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector143~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector142~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector141~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector140~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector139~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector138~9                                                                                                                     ; 1       ;
; uberACync:Sink|PotClk~14                                                                                                                         ; 1       ;
; uberACync:Sink|PotClk~13                                                                                                                         ; 1       ;
; uberACync:Sink|Selector83~8                                                                                                                      ; 1       ;
; uberACync:Sink|Selector132~6                                                                                                                     ; 1       ;
; uberACync:Sink|Selector134~6                                                                                                                     ; 1       ;
; uberACync:Sink|PrbsShift~16                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~15                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[1]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~14                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[2]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~13                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[3]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~12                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[4]                                                                                                                      ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~14                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~13                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~12                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~11                                            ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~12                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~11                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~10                                             ; 1       ;
; uberACync:Sink|PotBuf[8]~47                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~46                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~45                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~44                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[0]~43                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~42                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~41                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~40                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~39                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~38                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~37                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~36                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~35                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~34                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~33                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~32                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[2]~31                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[5]~30                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[5]~29                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[4]~28                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[4]~27                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[4]~26                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[3]~25                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[3]~24                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[3]~23                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[2]~21                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[2]~20                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[2]~19                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[1]~18                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[1]~17                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[1]~16                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[0]~15                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[0]~13                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[0]~12                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[11]~10                                                                                                                     ; 1       ;
; uberACync:Sink|PotBuf[11]~9                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[11]~8                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[10]~6                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[10]~5                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[9]~4                                                                                                                       ; 1       ;
; uberACync:Sink|PotBuf[9]~3                                                                                                                       ; 1       ;
; uberACync:Sink|PotBuf[10]~1                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~11                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[5]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~10                                                                                                                      ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~15                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~14                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~13                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~12                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~10                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                                ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~12                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~11                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~10                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[1]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[3]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[0]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[5]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[2]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[7]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[4]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[9]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[6]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[11]                                                          ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[8]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[12]                                                          ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|delayed_wrptr_g[10]                                                          ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~9                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                                 ; 1       ;
; uberACync:Sink|PhaseDelayTime[8]~1                                                                                                               ; 1       ;
; uberACync:Sink|WideOr1                                                                                                                           ; 1       ;
; uberACync:Sink|Selector46~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector44~6                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~9                                                                                                                       ; 1       ;
; uberACync:Sink|PrbsShift[6]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~8                                                                                                                       ; 1       ;
; uberACync:Sink|PrbsShift[11]                                                                                                                     ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~11                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~10                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[2]                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                                 ; 1       ;
; uberACync:Sink|Selector80~1                                                                                                                      ; 1       ;
; uberACync:Sink|Selector80~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector81~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector79~1                                                                                                                      ; 1       ;
; uberACync:Sink|Selector79~0                                                                                                                      ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|cntr_cout[13]~0                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~7                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~4                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~0                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~9                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                                  ; 1       ;
; uberACync:Sink|Selector200~1                                                                                                                     ; 1       ;
; uberACync:Sink|Selector200~0                                                                                                                     ; 1       ;
; uberACync:Sink|PreloadAna[0]~3                                                                                                                   ; 1       ;
; uberACync:Sink|PreloadAna[2]~2                                                                                                                   ; 1       ;
; uberACync:Sink|PreloadAna[2]~0                                                                                                                   ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10~0                                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12~0                                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11~0                                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~5                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~0                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]                  ; 1       ;
; uberACync:Sink|Selector43~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector45~0                                                                                                                      ; 1       ;
; uberACync:Sink|PhaseDelayTime[16]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[15]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[14]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[13]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[12]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[11]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[10]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[9]                                                                                                                 ; 1       ;
; uberACync:Sink|PhaseDelayTime[8]                                                                                                                 ; 1       ;
; uberACync:Sink|PhaseDelayTime[19]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[18]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[17]                                                                                                                ; 1       ;
; uberACync:Sink|Selector44~5                                                                                                                      ; 1       ;
; uberACync:Sink|WideOr1~3                                                                                                                         ; 1       ;
; uberACync:Sink|WideOr1~2                                                                                                                         ; 1       ;
; uberACync:Sink|WideOr1~1                                                                                                                         ; 1       ;
; uberACync:Sink|WideOr1~0                                                                                                                         ; 1       ;
; uberACync:Sink|PrbsShift~7                                                                                                                       ; 1       ;
; uberACync:Sink|PrbsShift[7]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~6                                                                                                                       ; 1       ;
; uberACync:Sink|PrbsShift[12]                                                                                                                     ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|_~1                                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|_~0                                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~6                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~3                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~2                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1~0                                    ; 1       ;
; uberACync:Sink|Selector70~7                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~6                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~5                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~4                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~3                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~2                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~1                                                                                                                      ; 1       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+----------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
; Name                                                                                                     ; Type ; Mode             ; Clock Mode  ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size   ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
+----------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks ; 4096         ; 48           ; 4096         ; 48           ; yes                    ; no                      ; yes                    ; yes                     ; 196608 ; 4096                        ; 48                          ; 4096                        ; 48                          ; 196608              ; 24   ; None ; M9K_X25_Y11_N0, M9K_X25_Y14_N0, M9K_X25_Y18_N0, M9K_X25_Y22_N0, M9K_X25_Y23_N0, M9K_X25_Y28_N0, M9K_X25_Y20_N0, M9K_X25_Y15_N0, M9K_X13_Y28_N0, M9K_X25_Y16_N0, M9K_X25_Y25_N0, M9K_X25_Y17_N0, M9K_X13_Y16_N0, M9K_X13_Y27_N0, M9K_X25_Y21_N0, M9K_X25_Y26_N0, M9K_X25_Y27_N0, M9K_X25_Y19_N0, M9K_X25_Y13_N0, M9K_X25_Y10_N0, M9K_X25_Y9_N0, M9K_X25_Y24_N0, M9K_X25_Y12_N0, M9K_X25_Y8_N0                                                                                                                   ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 32768        ; 8            ; 32768        ; 8            ; yes                    ; no                      ; yes                    ; yes                     ; 262144 ; 32768                       ; 8                           ; 32768                       ; 8                           ; 262144              ; 32   ; None ; M9K_X25_Y1_N0, M9K_X13_Y8_N0, M9K_X25_Y7_N0, M9K_X25_Y6_N0, M9K_X13_Y13_N0, M9K_X13_Y12_N0, M9K_X13_Y11_N0, M9K_X13_Y23_N0, M9K_X13_Y1_N0, M9K_X13_Y3_N0, M9K_X13_Y7_N0, M9K_X13_Y5_N0, M9K_X25_Y2_N0, M9K_X25_Y3_N0, M9K_X13_Y9_N0, M9K_X13_Y6_N0, M9K_X13_Y17_N0, M9K_X13_Y2_N0, M9K_X13_Y20_N0, M9K_X13_Y25_N0, M9K_X25_Y4_N0, M9K_X13_Y4_N0, M9K_X13_Y10_N0, M9K_X25_Y5_N0, M9K_X13_Y15_N0, M9K_X13_Y22_N0, M9K_X13_Y18_N0, M9K_X13_Y14_N0, M9K_X13_Y24_N0, M9K_X13_Y19_N0, M9K_X13_Y21_N0, M9K_X13_Y26_N0 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+----------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


+------------------------------------------------+
; Routing Usage Summary                          ;
+-----------------------+------------------------+
; Routing Resource Type ; Usage                  ;
+-----------------------+------------------------+
; Block interconnects   ; 2,969 / 47,787 ( 6 % ) ;
; C16 interconnects     ; 147 / 1,804 ( 8 % )    ;
; C4 interconnects      ; 1,750 / 31,272 ( 6 % ) ;
; Direct links          ; 241 / 47,787 ( < 1 % ) ;
; Global clocks         ; 6 / 20 ( 30 % )        ;
; Local interconnects   ; 761 / 15,408 ( 5 % )   ;
; R24 interconnects     ; 105 / 1,775 ( 6 % )    ;
; R4 interconnects      ; 2,070 / 41,310 ( 5 % ) ;
+-----------------------+------------------------+


+----------------------------------------------------------------------------+
; LAB Logic Elements                                                         ;
+---------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 12.67) ; Number of LABs  (Total = 91) ;
+---------------------------------------------+------------------------------+
; 1                                           ; 7                            ;
; 2                                           ; 2                            ;
; 3                                           ; 2                            ;
; 4                                           ; 3                            ;
; 5                                           ; 1                            ;
; 6                                           ; 0                            ;
; 7                                           ; 0                            ;
; 8                                           ; 4                            ;
; 9                                           ; 2                            ;
; 10                                          ; 4                            ;
; 11                                          ; 0                            ;
; 12                                          ; 2                            ;
; 13                                          ; 1                            ;
; 14                                          ; 4                            ;
; 15                                          ; 8                            ;
; 16                                          ; 51                           ;
+---------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 1.76) ; Number of LABs  (Total = 91) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 36                           ;
; 1 Clock                            ; 68                           ;
; 1 Clock enable                     ; 31                           ;
; 1 Sync. clear                      ; 2                            ;
; 1 Sync. load                       ; 7                            ;
; 2 Clock enables                    ; 7                            ;
; 2 Clocks                           ; 9                            ;
+------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Signals Sourced                                                         ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 18.56) ; Number of LABs  (Total = 91) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 3                            ;
; 2                                            ; 4                            ;
; 3                                            ; 0                            ;
; 4                                            ; 2                            ;
; 5                                            ; 1                            ;
; 6                                            ; 2                            ;
; 7                                            ; 1                            ;
; 8                                            ; 2                            ;
; 9                                            ; 0                            ;
; 10                                           ; 0                            ;
; 11                                           ; 0                            ;
; 12                                           ; 0                            ;
; 13                                           ; 0                            ;
; 14                                           ; 2                            ;
; 15                                           ; 7                            ;
; 16                                           ; 11                           ;
; 17                                           ; 7                            ;
; 18                                           ; 3                            ;
; 19                                           ; 1                            ;
; 20                                           ; 3                            ;
; 21                                           ; 5                            ;
; 22                                           ; 4                            ;
; 23                                           ; 3                            ;
; 24                                           ; 5                            ;
; 25                                           ; 7                            ;
; 26                                           ; 5                            ;
; 27                                           ; 1                            ;
; 28                                           ; 3                            ;
; 29                                           ; 4                            ;
; 30                                           ; 2                            ;
; 31                                           ; 1                            ;
; 32                                           ; 2                            ;
+----------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 7.07) ; Number of LABs  (Total = 91) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 11                           ;
; 2                                               ; 2                            ;
; 3                                               ; 10                           ;
; 4                                               ; 8                            ;
; 5                                               ; 6                            ;
; 6                                               ; 10                           ;
; 7                                               ; 6                            ;
; 8                                               ; 4                            ;
; 9                                               ; 2                            ;
; 10                                              ; 11                           ;
; 11                                              ; 5                            ;
; 12                                              ; 3                            ;
; 13                                              ; 5                            ;
; 14                                              ; 4                            ;
; 15                                              ; 2                            ;
; 16                                              ; 2                            ;
+-------------------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                         ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 12.84) ; Number of LABs  (Total = 91) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 1                            ;
; 2                                            ; 6                            ;
; 3                                            ; 3                            ;
; 4                                            ; 3                            ;
; 5                                            ; 3                            ;
; 6                                            ; 5                            ;
; 7                                            ; 3                            ;
; 8                                            ; 3                            ;
; 9                                            ; 6                            ;
; 10                                           ; 4                            ;
; 11                                           ; 8                            ;
; 12                                           ; 3                            ;
; 13                                           ; 7                            ;
; 14                                           ; 4                            ;
; 15                                           ; 2                            ;
; 16                                           ; 3                            ;
; 17                                           ; 2                            ;
; 18                                           ; 6                            ;
; 19                                           ; 2                            ;
; 20                                           ; 0                            ;
; 21                                           ; 3                            ;
; 22                                           ; 0                            ;
; 23                                           ; 0                            ;
; 24                                           ; 3                            ;
; 25                                           ; 2                            ;
; 26                                           ; 0                            ;
; 27                                           ; 1                            ;
; 28                                           ; 4                            ;
; 29                                           ; 0                            ;
; 30                                           ; 1                            ;
; 31                                           ; 0                            ;
; 32                                           ; 1                            ;
; 33                                           ; 0                            ;
; 34                                           ; 0                            ;
; 35                                           ; 1                            ;
+----------------------------------------------+------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 9     ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 21    ;
+----------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                                             ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+--------+------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Device ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+--------+------+-------------------+
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; ALL    ; I/O  ;                   ;
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; ALL    ; I/O  ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; ALL    ; I/O  ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; ALL    ; I/O  ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; ALL    ; I/O  ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; ALL    ; I/O  ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; ALL    ; I/O  ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; ALL    ; I/O  ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+--------+------+-------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass         ; 51        ; 0            ; 51        ; 0            ; 0            ; 51        ; 51        ; 0            ; 51        ; 51        ; 0            ; 0            ; 0            ; 0            ; 18           ; 0            ; 0            ; 18           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 51        ; 0            ; 0            ;
; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable ; 0         ; 51           ; 0         ; 51           ; 51           ; 0         ; 0         ; 51           ; 0         ; 0         ; 51           ; 51           ; 51           ; 51           ; 33           ; 51           ; 51           ; 33           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 0         ; 51           ; 51           ;
; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Prbs               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; AdcClk             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; AdcCs              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; AdcStart           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacLoad            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacCs              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; PotClk             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; PotStart           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Led                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacAddr[1]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacAddr[0]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[11]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[10]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[9]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[8]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ExtendOut[1]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ExtendOut[0]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Clk100             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ExtendIn[0]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ExtendIn[1]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Master             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Adc3               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Adc2               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Adc1               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Adc4               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[7]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[6]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[5]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[4]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[3]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[2]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[1]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[0]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; AC60Hz             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; PotDat             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+---------------------------------------------------------------------------------------------+
; Fitter Device Options                                                                       ;
+------------------------------------------------------------------+--------------------------+
; Option                                                           ; Setting                  ;
+------------------------------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
; Enable INIT_DONE output                                          ; Off                      ;
; Configuration scheme                                             ; Active Serial            ;
; Error detection CRC                                              ; Off                      ;
; Enable open drain on CRC_ERROR pin                               ; Off                      ;
; Enable input tri-state on active configuration pins in user mode ; Off                      ;
; Configuration Voltage Level                                      ; 3.3V                     ;
; Force Configuration Voltage Level                                ; Off                      ;
; nCEO                                                             ; As output driving ground ;
; Data[0]                                                          ; As input tri-stated      ;
; Data[1]/ASDO                                                     ; As input tri-stated      ;
; Data[7..2]                                                       ; Unreserved               ;
; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
; Other Active Parallel pins                                       ; Unreserved               ;
; DCLK                                                             ; As output driving ground ;
; Base pin-out file on sameframe device                            ; Off                      ;
+------------------------------------------------------------------+--------------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 °C   ;
; High Junction Temperature ; 85 °C  ;
+---------------------------+--------+


+-----------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Summary                                                       ;
+---------------------------------------------------+-----------------------------+-------------------+
; Source Clock(s)                                   ; Destination Clock(s)        ; Delay Added in ns ;
+---------------------------------------------------+-----------------------------+-------------------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 51.6              ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 28.2              ;
+---------------------------------------------------+-----------------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Details                                                                                                                                      ;
+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-------------------+
; Source Register               ; Destination Register                                                                                                           ; Delay Added in ns ;
+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-------------------+
; uberACync:Sink|FifoOutAna[31] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a31~porta_datain_reg0  ; 1.596             ;
; uberACync:Sink|FifoOutAna[7]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a7~porta_datain_reg0   ; 1.596             ;
; uberACync:Sink|DigInBuf[1]    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_datain_reg0  ; 1.543             ;
; uberACync:Sink|FifoOutAna[22] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a22~porta_datain_reg0  ; 1.346             ;
; uberACync:Sink|FifoOutAna[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a10~porta_datain_reg0  ; 1.342             ;
; uberACync:Sink|FifoOutAna[44] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a44~porta_datain_reg0  ; 1.337             ;
; uberACync:Sink|FifoOutAna[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a8~porta_datain_reg0   ; 1.329             ;
; uberACync:Sink|FifoOutAna[20] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a20~porta_datain_reg0  ; 1.328             ;
; uberACync:Sink|FifoOutAna[28] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a28~porta_datain_reg0  ; 1.328             ;
; uberACync:Sink|FifoOutAna[16] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a16~porta_datain_reg0  ; 1.324             ;
; uberACync:Sink|FifoOutAna[47] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a47~porta_datain_reg0  ; 1.320             ;
; uberACync:Sink|FifoOutAna[18] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a18~porta_datain_reg0  ; 1.318             ;
; uberACync:Sink|FifoOutAna[6]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a6~porta_datain_reg0   ; 1.318             ;
; uberACync:Sink|FifoOutAna[32] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a32~porta_datain_reg0  ; 1.315             ;
; uberACync:Sink|FifoOutAna[35] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a35~porta_datain_reg0  ; 1.311             ;
; uberACync:Sink|FifoOutAna[23] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a23~porta_datain_reg0  ; 1.303             ;
; uberACync:Sink|FifoOutAna[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a11~porta_datain_reg0  ; 1.303             ;
; uberACync:Sink|DigInBuf[7]    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_datain_reg0 ; 1.282             ;
; uberACync:Sink|DigInBuf[5]    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_datain_reg0 ; 1.265             ;
; uberACync:Sink|DigInBuf[3]    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_datain_reg0  ; 1.138             ;
; uberACync:Sink|DigInBuf[0]    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_datain_reg0  ; 1.137             ;
; uberACync:Sink|FifoOutAna[15] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a15~porta_datain_reg0  ; 1.076             ;
; uberACync:Sink|FifoOutAna[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a3~porta_datain_reg0   ; 1.076             ;
; uberACync:Sink|FifoOutAna[34] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a34~porta_datain_reg0  ; 1.057             ;
; uberACync:Sink|FifoOutAna[30] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a30~porta_datain_reg0  ; 1.055             ;
; uberACync:Sink|FifoOutAna[42] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a42~porta_datain_reg0  ; 1.055             ;
; uberACync:Sink|FifoOutAna[46] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a46~porta_datain_reg0  ; 1.054             ;
; uberACync:Sink|FifoOutAna[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a4~porta_datain_reg0   ; 1.053             ;
; uberACync:Sink|FifoOutAna[40] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a40~porta_datain_reg0  ; 1.053             ;
; uberACync:Sink|FifosClear     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                 ; 0.993             ;
; uberACync:Sink|DigInBuf[2]    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_datain_reg0  ; 0.983             ;
; uberACync:Sink|DigInBuf[4]    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0 ; 0.979             ;
; uberACync:Sink|FifoOutAna[33] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a33~porta_datain_reg0  ; 0.804             ;
; uberACync:Sink|FifoOutAna[27] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a27~porta_datain_reg0  ; 0.786             ;
; uberACync:Sink|FifoOutAna[39] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a39~porta_datain_reg0  ; 0.782             ;
; uberACync:Sink|FifoOutAna[21] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a21~porta_datain_reg0  ; 0.774             ;
; uberACync:Sink|FifoOutAna[41] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a41~porta_datain_reg0  ; 0.707             ;
; uberACync:Sink|DigInBuf[6]    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_datain_reg0  ; 0.707             ;
; uberACync:Sink|FifoOutAna[29] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a29~porta_datain_reg0  ; 0.631             ;
; uberACync:Sink|FifoOutAna[9]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a9~porta_datain_reg0   ; 0.560             ;
; uberACync:Sink|FifoOutAna[45] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a45~porta_datain_reg0  ; 0.526             ;
; uberACync:Sink|FifoOutAna[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a5~porta_datain_reg0   ; 0.421             ;
; uberACync:Sink|FifoOutAna[17] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a17~porta_datain_reg0  ; 0.396             ;
; uberACync:Sink|FifoOutAna[19] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a19~porta_datain_reg0  ; 0.231             ;
; uberACync:Sink|FifoOutAna[43] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ram_block11a43~porta_datain_reg0  ; 0.231             ;
; uberACync:Sink|FifoAnaRdClk   ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.173             ;
; uberACync:Sink|CtrAna[7]      ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|CtrAna[6]      ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|CtrAna[5]      ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|CtrAna[4]      ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|CtrAna[3]      ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|CtrAna[1]      ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|CtrAna[8]      ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|CtrAna[2]      ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|StateMode.010  ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|StateMode.100  ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|StateMode.110  ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
; uberACync:Sink|StateMode.000  ; uberACync:Sink|FifoAnaRdClk                                                                                                    ; 0.086             ;
+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-------------------+
Note: This table only shows the top 58 path(s) that have the largest delay added for hold.


+-----------------+
; Fitter Messages ;
+-----------------+
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (119006): Selected device EP4CE15E22C6 for design "ACync"
Info (119018): Selected Migration Device List
    Info (119019): Selected EP4CE15E22C7 for migration
    Info (119019): Selected EP4CE15E22C8 for migration
    Info (119019): Selected EP4CE15E22I7 for migration
Info (119021): Selected migration device list is legal with 133 total of migratable pins
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (15535): Implemented PLL "altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|pll1" as Cyclone IV E PLL type
    Info (15552): PLL constraints from migration devices are also being used
    Info (15099): Implementing clock multiplication of 3, clock division of 5, and phase shift of 0 degrees (0 ps) for altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] port
Info (171001): Fitter is performing a Fast Fit compilation, which decreases Fitter effort to reduce compilation time
Warning (176443): Devices selected for migration have different speed grades -- frequency limits are checked only for current device, not all devices
Info (169124): Fitter converted 5 user pins into dedicated programming pins
    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12
    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13
    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info (169197): Configuration voltage level is automatically enforced for the device family 'Cyclone IV E' with the configuration scheme 'Active Serial'
Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity dcfifo_h0l1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a* 
    Info (332165): Entity dcfifo_s1l1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_te9:dffpipe15|dffe16a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_se9:dffpipe12|dffe13a* 
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ACync.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained generated clocks found in the design
Info (332144): No user constrained base clocks found in the design
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info (332127): Assuming a default timing requirement
Info (332111): Found 6 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   16.666 60MHz|altpll_component|auto_generated|pll1|clk[0]
    Info (332111):   10.000       Clk100
    Info (332111):    1.000 uberACync:Sink|FifoAnaRdClk
    Info (332111):    1.000 uberACync:Sink|FifoAnaWrClk
    Info (332111):    1.000 uberACync:Sink|FifoDigRdClk
    Info (332111):    1.000 uberACync:Sink|FifoDigWrClk
Info (176353): Automatically promoted node altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1)
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info (176353): Automatically promoted node uberACync:Sink|FifoDigRdClk 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node uberACync:Sink|Selector70~4
Info (176353): Automatically promoted node uberACync:Sink|FifoAnaRdClk 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node uberACync:Sink|Selector131~2
        Info (176357): Destination node uberACync:Sink|Selector131~4
Info (176353): Automatically promoted node uberACync:Sink|FifoAnaWrClk 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node uberACync:Sink|Selector130~0
        Info (176357): Destination node uberACync:Sink|Selector130~1
Info (176353): Automatically promoted node uberACync:Sink|FifoDigWrClk 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node uberACync:Sink|Selector69~0
        Info (176357): Destination node uberACync:Sink|Selector69~1
Info (176353): Automatically promoted node uberACync:Sink|FifosClear 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]
        Info (176357): Destination node FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]
Warning (128008): Can't perform fitting netlist optimizations during fast fit compilation
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 5% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19
Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
Info (11888): Total time spent on timing analysis during the Fitter is 2.23 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
Info (169197): Configuration voltage level is automatically enforced for the device family 'Cyclone IV E' with the configuration scheme 'Active Serial'
Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169177): 18 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin Clk100 uses I/O standard 3.3-V LVCMOS at 23
    Info (169178): Pin ExtendIn[0] uses I/O standard 3.3-V LVCMOS at 52
    Info (169178): Pin ExtendIn[1] uses I/O standard 3.3-V LVCMOS at 51
    Info (169178): Pin Master uses I/O standard 3.3-V LVCMOS at 33
    Info (169178): Pin Adc3 uses I/O standard 3.3-V LVCMOS at 71
    Info (169178): Pin Adc2 uses I/O standard 3.3-V LVCMOS at 58
    Info (169178): Pin Adc1 uses I/O standard 3.3-V LVCMOS at 69
    Info (169178): Pin Adc4 uses I/O standard 3.3-V LVCMOS at 72
    Info (169178): Pin DigIn[7] uses I/O standard 3.3-V LVCMOS at 55
    Info (169178): Pin DigIn[6] uses I/O standard 3.3-V LVCMOS at 54
    Info (169178): Pin DigIn[5] uses I/O standard 3.3-V LVCMOS at 46
    Info (169178): Pin DigIn[4] uses I/O standard 3.3-V LVCMOS at 44
    Info (169178): Pin DigIn[3] uses I/O standard 3.3-V LVCMOS at 43
    Info (169178): Pin DigIn[2] uses I/O standard 3.3-V LVCMOS at 42
    Info (169178): Pin DigIn[1] uses I/O standard 3.3-V LVCMOS at 39
    Info (169178): Pin DigIn[0] uses I/O standard 3.3-V LVCMOS at 31
    Info (169178): Pin AC60Hz uses I/O standard 3.3-V LVCMOS at 53
    Info (169178): Pin PotDat uses I/O standard 3.3-V LVCMOS at 127
Info (144001): Generated suppressed messages file C:/Projects/Archives/2015 ACync/Altera/output_files/ACync.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 1022 megabytes
    Info: Processing ended: Thu Mar 12 16:10:27 2015
    Info: Elapsed time: 00:00:25
    Info: Total CPU time (on all processors): 00:00:26


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Projects/Archives/2015 ACync/Altera/output_files/ACync.fit.smsg.


