Analysis & Synthesis report for ACync
Thu Mar 12 16:09:48 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |ACync_block|uberACync:Sink|StateMode
 11. State Machine - |ACync_block|uberACync:Sink|StateZero
 12. Registers Removed During Synthesis
 13. General Register Statistics
 14. Inverted Register Statistics
 15. Physical Synthesis Netlist Optimizations
 16. Multiplexer Restructuring Statistics (Restructuring Performed)
 17. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component
 18. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated
 19. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p
 20. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p
 21. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram
 22. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp
 23. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12
 24. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp
 25. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15
 26. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component
 27. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated
 28. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p
 29. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p
 30. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram
 31. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp
 32. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14
 33. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp
 34. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17
 35. Parameter Settings for User Entity Instance: altpll0:60MHz|altpll:altpll_component
 36. Parameter Settings for User Entity Instance: FifoA:FifoAnalog|dcfifo:dcfifo_component
 37. Parameter Settings for User Entity Instance: FifoD:FifoDigital|dcfifo:dcfifo_component
 38. altpll Parameter Settings by Entity Instance
 39. dcfifo Parameter Settings by Entity Instance
 40. Elapsed Time Per Partition
 41. Analysis & Synthesis Messages
 42. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Mar 12 16:09:48 2015       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; ACync                                       ;
; Top-level Entity Name              ; ACync_block                                 ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 1,246                                       ;
;     Total combinational functions  ; 938                                         ;
;     Dedicated logic registers      ; 581                                         ;
; Total registers                    ; 581                                         ;
; Total pins                         ; 51                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 458,752                                     ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 1                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE15E22C6       ;                    ;
; Top-level entity name                                                      ; ACync_block        ; ACync              ;
; Family name                                                                ; Cyclone IV E       ; Cyclone IV GX      ;
; Verilog Show LMF Mapping Messages                                          ; Off                ;                    ;
; Verilog Version                                                            ; SystemVerilog_2005 ; Verilog_2001       ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ; < 0.1%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                 ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                       ; Library ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+
; ACync_block.bdf                  ; yes             ; User Block Diagram/Schematic File  ; C:/Projects/Archives/2015 ACync/Altera/ACync_block.bdf             ;         ;
; uberACync.sv                     ; yes             ; User SystemVerilog HDL File        ; C:/Projects/Archives/2015 ACync/Altera/uberACync.sv                ;         ;
; altpll0.v                        ; yes             ; User Wizard-Generated File         ; C:/Projects/Archives/2015 ACync/Altera/altpll0.v                   ;         ;
; FifoD.v                          ; yes             ; User Wizard-Generated File         ; C:/Projects/Archives/2015 ACync/Altera/FifoD.v                     ;         ;
; FifoA.v                          ; yes             ; User Wizard-Generated File         ; C:/Projects/Archives/2015 ACync/Altera/FifoA.v                     ;         ;
; altpll.tdf                       ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altpll.tdf          ;         ;
; aglobal131.inc                   ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc      ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_pll.inc     ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratixii_pll.inc   ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc   ;         ;
; db/altpll0_altpll.v              ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/altpll0_altpll.v         ;         ;
; dcfifo.tdf                       ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dcfifo.tdf          ;         ;
; lpm_counter.inc                  ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc     ;         ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc     ;         ;
; altdpram.inc                     ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc        ;         ;
; a_graycounter.inc                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_graycounter.inc   ;         ;
; a_fefifo.inc                     ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_fefifo.inc        ;         ;
; a_gray2bin.inc                   ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_gray2bin.inc      ;         ;
; dffpipe.inc                      ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dffpipe.inc         ;         ;
; alt_sync_fifo.inc                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/alt_sync_fifo.inc   ;         ;
; lpm_compare.inc                  ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc     ;         ;
; altsyncram_fifo.inc              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram_fifo.inc ;         ;
; db/dcfifo_s1l1.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/dcfifo_s1l1.tdf          ;         ;
; db/a_graycounter_877.tdf         ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/a_graycounter_877.tdf    ;         ;
; db/a_graycounter_4lc.tdf         ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/a_graycounter_4lc.tdf    ;         ;
; db/altsyncram_sm31.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/altsyncram_sm31.tdf      ;         ;
; db/alt_synch_pipe_tld.tdf        ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/alt_synch_pipe_tld.tdf   ;         ;
; db/dffpipe_se9.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/dffpipe_se9.tdf          ;         ;
; db/alt_synch_pipe_uld.tdf        ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/alt_synch_pipe_uld.tdf   ;         ;
; db/dffpipe_te9.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/dffpipe_te9.tdf          ;         ;
; db/cmpr_d66.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/cmpr_d66.tdf             ;         ;
; db/cmpr_c66.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/cmpr_c66.tdf             ;         ;
; db/cmpr_q76.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/cmpr_q76.tdf             ;         ;
; db/mux_j28.tdf                   ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/mux_j28.tdf              ;         ;
; db/dcfifo_h0l1.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/dcfifo_h0l1.tdf          ;         ;
; db/a_graycounter_b77.tdf         ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/a_graycounter_b77.tdf    ;         ;
; db/a_graycounter_7lc.tdf         ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/a_graycounter_7lc.tdf    ;         ;
; db/altsyncram_qj31.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/altsyncram_qj31.tdf      ;         ;
; db/decode_d87.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/decode_d87.tdf           ;         ;
; db/mux_t28.tdf                   ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/mux_t28.tdf              ;         ;
; db/alt_synch_pipe_0md.tdf        ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/alt_synch_pipe_0md.tdf   ;         ;
; db/dffpipe_ve9.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/dffpipe_ve9.tdf          ;         ;
; db/alt_synch_pipe_1md.tdf        ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/alt_synch_pipe_1md.tdf   ;         ;
; db/dffpipe_0f9.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/dffpipe_0f9.tdf          ;         ;
; db/cmpr_e66.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/cmpr_e66.tdf             ;         ;
; db/cmpr_t76.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Projects/Archives/2015 ACync/Altera/db/cmpr_t76.tdf             ;         ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+


+-------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                             ;
+---------------------------------------------+---------------------------+
; Resource                                    ; Usage                     ;
+---------------------------------------------+---------------------------+
; Estimated Total logic elements              ; 1,246                     ;
;                                             ;                           ;
; Total combinational functions               ; 938                       ;
; Logic element usage by number of LUT inputs ;                           ;
;     -- 4 input functions                    ; 580                       ;
;     -- 3 input functions                    ; 149                       ;
;     -- <=2 input functions                  ; 209                       ;
;                                             ;                           ;
; Logic elements by mode                      ;                           ;
;     -- normal mode                          ; 820                       ;
;     -- arithmetic mode                      ; 118                       ;
;                                             ;                           ;
; Total registers                             ; 581                       ;
;     -- Dedicated logic registers            ; 581                       ;
;     -- I/O registers                        ; 0                         ;
;                                             ;                           ;
; I/O pins                                    ; 51                        ;
; Total memory bits                           ; 458752                    ;
; Embedded Multiplier 9-bit elements          ; 0                         ;
; Total PLLs                                  ; 1                         ;
;     -- PLLs                                 ; 1                         ;
;                                             ;                           ;
; Maximum fan-out node                        ; uberACync:Sink|FifosClear ;
; Maximum fan-out                             ; 407                       ;
; Total fan-out                               ; 7643                      ;
; Average fan-out                             ; 4.49                      ;
+---------------------------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                          ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                   ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                ; Library Name ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |ACync_block                                 ; 938 (1)           ; 581 (0)      ; 458752      ; 0            ; 0       ; 0         ; 51   ; 0            ; |ACync_block                                                                                                                       ; work         ;
;    |FifoA:FifoAnalog|                        ; 119 (0)           ; 146 (0)      ; 196608      ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog                                                                                                      ; work         ;
;       |dcfifo:dcfifo_component|              ; 119 (0)           ; 146 (0)      ; 196608      ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component                                                                              ; work         ;
;          |dcfifo_s1l1:auto_generated|        ; 119 (7)           ; 146 (56)     ; 196608      ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated                                                   ; work         ;
;             |a_graycounter_4lc:wrptr_g1p|    ; 35 (35)           ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p                       ; work         ;
;             |a_graycounter_877:rdptr_g1p|    ; 31 (31)           ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p                       ; work         ;
;             |alt_synch_pipe_tld:rs_dgwp|     ; 0 (0)             ; 26 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp                        ; work         ;
;                |dffpipe_se9:dffpipe12|       ; 0 (0)             ; 26 (26)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12  ; work         ;
;             |alt_synch_pipe_uld:ws_dgrp|     ; 0 (0)             ; 26 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp                        ; work         ;
;                |dffpipe_te9:dffpipe15|       ; 0 (0)             ; 26 (26)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15  ; work         ;
;             |altsyncram_sm31:fifo_ram|       ; 0 (0)             ; 0 (0)        ; 196608      ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram                          ; work         ;
;             |cmpr_c66:rdempty_eq_comp1_msb|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_c66:rdempty_eq_comp1_msb                     ; work         ;
;             |cmpr_q76:rdfull_eq_comp|        ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_q76:rdfull_eq_comp                           ; work         ;
;             |mux_j28:rdemp_eq_comp_lsb_mux|  ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux                     ; work         ;
;             |mux_j28:rdemp_eq_comp_msb_mux|  ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux                     ; work         ;
;             |mux_j28:wrfull_eq_comp_lsb_mux| ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux                    ; work         ;
;             |mux_j28:wrfull_eq_comp_msb_mux| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux                    ; work         ;
;    |FifoD:FifoDigital|                       ; 170 (0)           ; 183 (0)      ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital                                                                                                     ; work         ;
;       |dcfifo:dcfifo_component|              ; 170 (0)           ; 183 (0)      ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component                                                                             ; work         ;
;          |dcfifo_h0l1:auto_generated|        ; 170 (7)           ; 183 (69)     ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated                                                  ; work         ;
;             |a_graycounter_7lc:wrptr_g1p|    ; 43 (43)           ; 21 (21)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p                      ; work         ;
;             |a_graycounter_b77:rdptr_g1p|    ; 38 (38)           ; 23 (23)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p                      ; work         ;
;             |alt_synch_pipe_0md:rs_dgwp|     ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp                       ; work         ;
;                |dffpipe_ve9:dffpipe14|       ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14 ; work         ;
;             |alt_synch_pipe_1md:ws_dgrp|     ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp                       ; work         ;
;                |dffpipe_0f9:dffpipe17|       ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17 ; work         ;
;             |altsyncram_qj31:fifo_ram|       ; 26 (2)            ; 6 (6)        ; 262144      ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram                         ; work         ;
;                |decode_d87:decode12|         ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12     ; work         ;
;                |mux_t28:mux13|               ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|mux_t28:mux13           ; work         ;
;             |cmpr_t76:rdfull_eq_comp|        ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp                          ; work         ;
;             |mux_j28:rdemp_eq_comp_lsb_mux|  ; 12 (12)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux                    ; work         ;
;             |mux_j28:rdemp_eq_comp_msb_mux|  ; 12 (12)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux                    ; work         ;
;             |mux_j28:wrfull_eq_comp_lsb_mux| ; 11 (11)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux                   ; work         ;
;             |mux_j28:wrfull_eq_comp_msb_mux| ; 11 (11)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux                   ; work         ;
;    |altpll0:60MHz|                           ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|altpll0:60MHz                                                                                                         ; work         ;
;       |altpll:altpll_component|              ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|altpll0:60MHz|altpll:altpll_component                                                                                 ; work         ;
;          |altpll0_altpll:auto_generated|     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated                                                   ; work         ;
;    |uberACync:Sink|                          ; 648 (648)         ; 252 (252)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ACync_block|uberACync:Sink                                                                                                        ; work         ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                               ;
+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; Name                                                                                                     ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF  ;
+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 4096         ; 48           ; 4096         ; 48           ; 196608 ; None ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32768        ; 8            ; 32768        ; 8            ; 262144 ; None ;
+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                             ;
+--------+--------------+---------+--------------+--------------+--------------------------------+--------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                ; IP Include File                                  ;
+--------+--------------+---------+--------------+--------------+--------------------------------+--------------------------------------------------+
; Altera ; ALTPLL       ; 13.1    ; N/A          ; N/A          ; |ACync_block|altpll0:60MHz     ; C:/Projects/Archives/2015 ACync/Altera/altpll0.v ;
; Altera ; FIFO         ; 13.1    ; N/A          ; N/A          ; |ACync_block|FifoA:FifoAnalog  ; C:/Projects/Archives/2015 ACync/Altera/FifoA.v   ;
; Altera ; FIFO         ; 13.1    ; N/A          ; N/A          ; |ACync_block|FifoD:FifoDigital ; C:/Projects/Archives/2015 ACync/Altera/FifoD.v   ;
+--------+--------------+---------+--------------+--------------+--------------------------------+--------------------------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |ACync_block|uberACync:Sink|StateMode                                                                                         ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+
; Name          ; StateMode.111 ; StateMode.110 ; StateMode.101 ; StateMode.100 ; StateMode.011 ; StateMode.010 ; StateMode.001 ; StateMode.000 ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+
; StateMode.000 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ;
; StateMode.001 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 1             ;
; StateMode.010 ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 1             ;
; StateMode.011 ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 1             ;
; StateMode.100 ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 1             ;
; StateMode.101 ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; StateMode.110 ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; StateMode.111 ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------+
; State Machine - |ACync_block|uberACync:Sink|StateZero                    ;
+--------------+--------------+--------------+--------------+--------------+
; Name         ; StateZero.11 ; StateZero.10 ; StateZero.01 ; StateZero.00 ;
+--------------+--------------+--------------+--------------+--------------+
; StateZero.00 ; 0            ; 0            ; 0            ; 0            ;
; StateZero.01 ; 0            ; 0            ; 1            ; 1            ;
; StateZero.10 ; 0            ; 1            ; 0            ; 1            ;
; StateZero.11 ; 1            ; 0            ; 0            ; 1            ;
+--------------+--------------+--------------+--------------+--------------+


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; uberACync:Sink|PhaseDelayTime[0..7,20] ; Stuck at GND due to stuck port data_in ;
; uberACync:Sink|StateMode.111           ; Lost fanout                            ;
; uberACync:Sink|StateMode~9             ; Lost fanout                            ;
; uberACync:Sink|StateMode~10            ; Lost fanout                            ;
; uberACync:Sink|StateMode~11            ; Lost fanout                            ;
; uberACync:Sink|StateZero~6             ; Lost fanout                            ;
; uberACync:Sink|StateZero~7             ; Lost fanout                            ;
; Total Number of Removed Registers = 15 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 581   ;
; Number of registers using Synchronous Clear  ; 37    ;
; Number of registers using Synchronous Load   ; 51    ;
; Number of registers using Asynchronous Clear ; 325   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 237   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                          ;
+-------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                           ; Fan out ;
+-------------------------------------------------------------------------------------------------------------+---------+
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdemp_eq_comp_lsb_aeb                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|rdemp_eq_comp_msb_aeb                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0  ; 10      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                  ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                  ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0 ; 10      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0  ; 12      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6     ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0 ; 11      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6    ; 7       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9     ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9    ; 8       ;
; Total number of inverted registers = 12                                                                     ;         ;
+-------------------------------------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Physical Synthesis Netlist Optimizations                                                                                                                                                  ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------------------+---------------------+
; Node                                                                                                                                             ; Action           ; Reason              ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------------------+---------------------+
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~0                                              ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~0_RESYN184_BDD185                              ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2                                              ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2_RESYN188_BDD189                              ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2_RESYN190_BDD191                              ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~3                                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~4                                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~6                                              ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~6_RESYN196_BDD197                              ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~7                                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~8                                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2~0_RESYN122_BDD123                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3~0_RESYN194_BDD195                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4~0_RESYN186_BDD187                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5~0_RESYN124_BDD125                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6~0_RESYN192_BDD193                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8~0_RESYN126_BDD127                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9~0_RESYN204_BDD205                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10~0                                    ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10~0_RESYN202_BDD203                    ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11~0                                    ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11~0_RESYN198_BDD199                    ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12~0                                    ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12~0_RESYN200_BDD201                    ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~0                                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~3                                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5                                              ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5_RESYN162_BDD163                              ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5_RESYN164_BDD165                              ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~6                                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~7                                              ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~7_RESYN166_BDD167                              ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~8                                              ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~8_RESYN168_BDD169                              ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0_NEW26_RTM028                          ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0_OTERM27                               ; Retimed Register ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5~0_RESYN100_BDD101                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8~0                                     ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8~0_RESYN102_BDD103                     ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11                                      ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9                               ; Retimed Register ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11                              ; Retimed Register ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13                              ; Retimed Register ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12                                      ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15                              ; Retimed Register ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6_NEW29_RTM031                             ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6_OTERM30                                  ; Retimed Register ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~0                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~1                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~2                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~3                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN86_BDD87                 ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN88_BDD89                 ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~6                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9                               ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9_RESYN144_BDD145               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9_RESYN146_BDD147               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9_RESYN148_BDD149               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9_RESYN150_BDD151               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~0                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~1                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~2                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~3                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~3_RESYN92_BDD93                 ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~4                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~5                               ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7                               ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN152_BDD153               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN154_BDD155               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN156_BDD157               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN158_BDD159               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7_RESYN160_BDD161               ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~0                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~1                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~2                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~3                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~4                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~7                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~8                              ; Deleted          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9                              ; Modified         ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN76_BDD77                ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN78_BDD79                ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_BDD83                ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_RESYN238_BDD239      ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_RESYN240_BDD241      ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_RESYN242_BDD243      ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN82_RESYN244_BDD245      ; Created          ; Timing optimization ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|ram_address_b[11]                                                            ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1                                             ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1_RESYN206_BDD207                             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1_RESYN208_BDD209                             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~2                                             ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~2_RESYN210_BDD211                             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~3                                             ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~3_RESYN212_BDD213                             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~5                                             ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~6                                             ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~8                                             ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~9                                             ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|cntr_cout[13]~0                                 ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2~0                                    ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2~0_RESYN130_BDD131                    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3~0                                    ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3~0_RESYN222_BDD223                    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4~0                                    ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4~0_RESYN220_BDD221                    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5~0                                    ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5~0_RESYN128_BDD129                    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8~0                                    ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8~0_RESYN134_BDD135                    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9~0                                    ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9~0_RESYN232_BDD233                    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0                                   ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0_RESYN228_BDD229                   ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0_RESYN230_BDD231                   ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11~0                                   ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11~0_RESYN132_BDD133                   ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12~0                                   ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12~0_RESYN226_BDD227                   ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13~0                                   ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13~0_RESYN214_BDD215                   ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14~0                                   ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14~0_RESYN218_BDD219                   ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15~0                                   ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15~0_RESYN216_BDD217                   ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~0                                             ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~2                                             ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~4                                             ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5                                             ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5_RESYN118_BDD119                             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5_RESYN178_BDD179                             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~7                                             ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~7_RESYN180_BDD181                             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~8                                             ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~9                                             ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~9_RESYN182_BDD183                             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|cntr_cout[13]~0                                 ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|cntr_cout[13]~0_RESYN224_BDD225                 ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0_NEW20_RTM022                         ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0_OTERM21                              ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1~0                                    ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11~0                                   ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11~0_RESYN120_BDD121                   ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14                                     ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7                              ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15                                     ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1                              ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3                              ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5                              ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6_NEW23_RTM025                            ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6_OTERM24                                 ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|_~1                                                ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode651w[2]                 ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode651w[2]_RESYN140_BDD141 ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode664w[2]                 ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode664w[2]_RESYN136_BDD137 ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode672w[2]                 ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode672w[2]_RESYN138_BDD139 ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode680w[2]                 ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode680w[2]_RESYN142_BDD143 ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_e66:rdempty_eq_comp_lsb|data_wire[0]~0                                 ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_e66:rdempty_eq_comp_msb|data_wire[0]~0                                 ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty                                                                 ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_NEW_REG16_RTM018                                                ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_NEW_REG16_RTM018                                                ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                                         ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_RTM019                                                          ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_RTM019                                                          ; Retimed Register ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_RTM019_RESYN234_BDD235                                          ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_RTM019_RESYN236_BDD237                                          ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty~_wirecell                                                       ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~0                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~1                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~2                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~3                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4                              ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN104_BDD105              ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN170_BDD171              ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN172_BDD173              ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN174_BDD175              ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4_RESYN176_BDD177              ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~0                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~1                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~2                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~4                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~5                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~9                              ; Deleted          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10                             ; Modified         ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN110_BDD111             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN112_BDD113             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_BDD117             ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_RESYN246_BDD247    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_RESYN248_BDD249    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_RESYN250_BDD251    ; Created          ; Timing optimization ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN116_RESYN252_BDD253    ; Created          ; Timing optimization ;
; uberACync:Sink|Add7~1                                                                                                                            ; Modified         ; Timing optimization ;
; uberACync:Sink|Add10~1                                                                                                                           ; Modified         ; Timing optimization ;
; uberACync:Sink|Add12~1                                                                                                                           ; Modified         ; Timing optimization ;
; uberACync:Sink|Add19~0                                                                                                                           ; Modified         ; Timing optimization ;
; uberACync:Sink|Led~3                                                                                                                             ; Deleted          ; Timing optimization ;
; uberACync:Sink|Led~3_wirecell                                                                                                                    ; Modified         ; Timing optimization ;
; uberACync:Sink|PotClk~9                                                                                                                          ; Modified         ; Timing optimization ;
; uberACync:Sink|Selector95~40                                                                                                                     ; Modified         ; Timing optimization ;
; uberACync:Sink|Selector144~0                                                                                                                     ; Modified         ; Timing optimization ;
; uberACync:Sink|Selector146~7                                                                                                                     ; Modified         ; Timing optimization ;
; uberACync:Sink|Selector214~4                                                                                                                     ; Modified         ; Timing optimization ;
; uberACync:Sink|Selector214~5                                                                                                                     ; Modified         ; Timing optimization ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------------------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------+
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |ACync_block|uberACync:Sink|PrbsShift[1]         ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[0]        ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[1]        ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[14]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[39]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[4]        ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[41]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[6]        ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[19]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[20]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[45]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[10]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|FifoOutAna[47]       ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|DigOut[2]            ;
; 5:1                ; 9 bits    ; 27 LEs        ; 9 LEs                ; 18 LEs                 ; Yes        ; |ACync_block|uberACync:Sink|DelayTimer[4]        ;
; 5:1                ; 12 bits   ; 36 LEs        ; 12 LEs               ; 24 LEs                 ; Yes        ; |ACync_block|uberACync:Sink|DelayTimer[12]       ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|CtrDig[5]            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |ACync_block|uberACync:Sink|PreloadAna[2]        ;
; 5:1                ; 21 bits   ; 63 LEs        ; 21 LEs               ; 42 LEs                 ; Yes        ; |ACync_block|uberACync:Sink|RetriggerInhibit[11] ;
; 6:1                ; 9 bits    ; 36 LEs        ; 9 LEs                ; 27 LEs                 ; Yes        ; |ACync_block|uberACync:Sink|CtrAna[7]            ;
; 73:1               ; 2 bits    ; 96 LEs        ; 18 LEs               ; 78 LEs                 ; Yes        ; |ACync_block|uberACync:Sink|DacDat[2]            ;
; 76:1               ; 9 bits    ; 450 LEs       ; 90 LEs               ; 360 LEs                ; Yes        ; |ACync_block|uberACync:Sink|DacDat[9]            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |ACync_block|uberACync:Sink|PreloadDig           ;
; 7:1                ; 4 bits    ; 16 LEs        ; 12 LEs               ; 4 LEs                  ; No         ; |ACync_block|uberACync:Sink|Selector56           ;
; 8:1                ; 4 bits    ; 20 LEs        ; 12 LEs               ; 8 LEs                  ; No         ; |ACync_block|uberACync:Sink|Selector44           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------+


+-----------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+----------------+
; Assignment                      ; Value ; From ; To             ;
+---------------------------------+-------+------+----------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -              ;
+---------------------------------+-------+------+----------------+


+----------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated         ;
+---------------------------------------+------------------------+------+----------------------------+
; Assignment                            ; Value                  ; From ; To                         ;
+---------------------------------------+------------------------+------+----------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                    ; -    ; -                          ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF                    ; -    ; -                          ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF                    ; -    ; -                          ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3                      ; -    ; -                          ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rdemp_eq_comp_lsb_aeb      ;
; POWER_UP_LEVEL                        ; HIGH                   ; -    ; rdemp_eq_comp_lsb_aeb      ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rdemp_eq_comp_msb_aeb      ;
; POWER_UP_LEVEL                        ; HIGH                   ; -    ; rdemp_eq_comp_msb_aeb      ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rs_dgwp_reg                ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; wrfull_eq_comp_lsb_mux_reg ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; wrfull_eq_comp_msb_mux_reg ;
; POWER_UP_LEVEL                        ; LOW                    ; -    ; wrptr_g                    ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; ws_dgrp_reg                ;
+---------------------------------------+------------------------+------+----------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                     ;
+----------------+-------+------+----------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                             ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                ;
+----------------+-------+------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                     ;
+----------------+-------+------+----------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                             ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                ;
+----------------+-------+------+----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram ;
+---------------------------------+--------------------+------+-------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                    ;
+---------------------------------+--------------------+------+-------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                     ;
+---------------------------------+--------------------+------+-------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp ;
+-----------------------------+------------------------+------+---------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                      ;
+-----------------------------+------------------------+------+---------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                       ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                       ;
+-----------------------------+------------------------+------+---------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                         ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                          ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp ;
+-----------------------------+------------------------+------+---------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                      ;
+-----------------------------+------------------------+------+---------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                       ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                       ;
+-----------------------------+------------------------+------+---------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                         ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                          ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------+
; Assignment                      ; Value ; From ; To              ;
+---------------------------------+-------+------+-----------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -               ;
+---------------------------------+-------+------+-----------------+


+----------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated        ;
+---------------------------------------+------------------------+------+----------------------------+
; Assignment                            ; Value                  ; From ; To                         ;
+---------------------------------------+------------------------+------+----------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                    ; -    ; -                          ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF                    ; -    ; -                          ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF                    ; -    ; -                          ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3                      ; -    ; -                          ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rdemp_eq_comp_lsb_aeb      ;
; POWER_UP_LEVEL                        ; HIGH                   ; -    ; rdemp_eq_comp_lsb_aeb      ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rdemp_eq_comp_msb_aeb      ;
; POWER_UP_LEVEL                        ; HIGH                   ; -    ; rdemp_eq_comp_msb_aeb      ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rs_dgwp_reg                ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; wrfull_eq_comp_lsb_mux_reg ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; wrfull_eq_comp_msb_mux_reg ;
; POWER_UP_LEVEL                        ; LOW                    ; -    ; wrptr_g                    ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; ws_dgrp_reg                ;
+---------------------------------------+------------------------+------+----------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                      ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                 ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                      ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                 ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                     ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                      ;
+---------------------------------+--------------------+------+--------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                       ;
+-----------------------------+------------------------+------+----------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                        ;
+-----------------------------+------------------------+------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                       ;
+-----------------------------+------------------------+------+----------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                        ;
+-----------------------------+------------------------+------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altpll0:60MHz|altpll:altpll_component ;
+-------------------------------+---------------------------+------------------------+
; Parameter Name                ; Value                     ; Type                   ;
+-------------------------------+---------------------------+------------------------+
; OPERATION_MODE                ; NORMAL                    ; Untyped                ;
; PLL_TYPE                      ; AUTO                      ; Untyped                ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=altpll0 ; Untyped                ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                ;
; INCLK0_INPUT_FREQUENCY        ; 10000                     ; Signed Integer         ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                ;
; LOCK_HIGH                     ; 1                         ; Untyped                ;
; LOCK_LOW                      ; 1                         ; Untyped                ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                ;
; SKIP_VCO                      ; OFF                       ; Untyped                ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                ;
; BANDWIDTH                     ; 0                         ; Untyped                ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                ;
; DOWN_SPREAD                   ; 0                         ; Untyped                ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK1_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK0_MULTIPLY_BY              ; 3                         ; Signed Integer         ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK1_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK0_DIVIDE_BY                ; 5                         ; Signed Integer         ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK1_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer         ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                ;
; DPA_DIVIDER                   ; 0                         ; Untyped                ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                ;
; VCO_MIN                       ; 0                         ; Untyped                ;
; VCO_MAX                       ; 0                         ; Untyped                ;
; VCO_CENTER                    ; 0                         ; Untyped                ;
; PFD_MIN                       ; 0                         ; Untyped                ;
; PFD_MAX                       ; 0                         ; Untyped                ;
; M_INITIAL                     ; 0                         ; Untyped                ;
; M                             ; 0                         ; Untyped                ;
; N                             ; 1                         ; Untyped                ;
; M2                            ; 1                         ; Untyped                ;
; N2                            ; 1                         ; Untyped                ;
; SS                            ; 1                         ; Untyped                ;
; C0_HIGH                       ; 0                         ; Untyped                ;
; C1_HIGH                       ; 0                         ; Untyped                ;
; C2_HIGH                       ; 0                         ; Untyped                ;
; C3_HIGH                       ; 0                         ; Untyped                ;
; C4_HIGH                       ; 0                         ; Untyped                ;
; C5_HIGH                       ; 0                         ; Untyped                ;
; C6_HIGH                       ; 0                         ; Untyped                ;
; C7_HIGH                       ; 0                         ; Untyped                ;
; C8_HIGH                       ; 0                         ; Untyped                ;
; C9_HIGH                       ; 0                         ; Untyped                ;
; C0_LOW                        ; 0                         ; Untyped                ;
; C1_LOW                        ; 0                         ; Untyped                ;
; C2_LOW                        ; 0                         ; Untyped                ;
; C3_LOW                        ; 0                         ; Untyped                ;
; C4_LOW                        ; 0                         ; Untyped                ;
; C5_LOW                        ; 0                         ; Untyped                ;
; C6_LOW                        ; 0                         ; Untyped                ;
; C7_LOW                        ; 0                         ; Untyped                ;
; C8_LOW                        ; 0                         ; Untyped                ;
; C9_LOW                        ; 0                         ; Untyped                ;
; C0_INITIAL                    ; 0                         ; Untyped                ;
; C1_INITIAL                    ; 0                         ; Untyped                ;
; C2_INITIAL                    ; 0                         ; Untyped                ;
; C3_INITIAL                    ; 0                         ; Untyped                ;
; C4_INITIAL                    ; 0                         ; Untyped                ;
; C5_INITIAL                    ; 0                         ; Untyped                ;
; C6_INITIAL                    ; 0                         ; Untyped                ;
; C7_INITIAL                    ; 0                         ; Untyped                ;
; C8_INITIAL                    ; 0                         ; Untyped                ;
; C9_INITIAL                    ; 0                         ; Untyped                ;
; C0_MODE                       ; BYPASS                    ; Untyped                ;
; C1_MODE                       ; BYPASS                    ; Untyped                ;
; C2_MODE                       ; BYPASS                    ; Untyped                ;
; C3_MODE                       ; BYPASS                    ; Untyped                ;
; C4_MODE                       ; BYPASS                    ; Untyped                ;
; C5_MODE                       ; BYPASS                    ; Untyped                ;
; C6_MODE                       ; BYPASS                    ; Untyped                ;
; C7_MODE                       ; BYPASS                    ; Untyped                ;
; C8_MODE                       ; BYPASS                    ; Untyped                ;
; C9_MODE                       ; BYPASS                    ; Untyped                ;
; C0_PH                         ; 0                         ; Untyped                ;
; C1_PH                         ; 0                         ; Untyped                ;
; C2_PH                         ; 0                         ; Untyped                ;
; C3_PH                         ; 0                         ; Untyped                ;
; C4_PH                         ; 0                         ; Untyped                ;
; C5_PH                         ; 0                         ; Untyped                ;
; C6_PH                         ; 0                         ; Untyped                ;
; C7_PH                         ; 0                         ; Untyped                ;
; C8_PH                         ; 0                         ; Untyped                ;
; C9_PH                         ; 0                         ; Untyped                ;
; L0_HIGH                       ; 1                         ; Untyped                ;
; L1_HIGH                       ; 1                         ; Untyped                ;
; G0_HIGH                       ; 1                         ; Untyped                ;
; G1_HIGH                       ; 1                         ; Untyped                ;
; G2_HIGH                       ; 1                         ; Untyped                ;
; G3_HIGH                       ; 1                         ; Untyped                ;
; E0_HIGH                       ; 1                         ; Untyped                ;
; E1_HIGH                       ; 1                         ; Untyped                ;
; E2_HIGH                       ; 1                         ; Untyped                ;
; E3_HIGH                       ; 1                         ; Untyped                ;
; L0_LOW                        ; 1                         ; Untyped                ;
; L1_LOW                        ; 1                         ; Untyped                ;
; G0_LOW                        ; 1                         ; Untyped                ;
; G1_LOW                        ; 1                         ; Untyped                ;
; G2_LOW                        ; 1                         ; Untyped                ;
; G3_LOW                        ; 1                         ; Untyped                ;
; E0_LOW                        ; 1                         ; Untyped                ;
; E1_LOW                        ; 1                         ; Untyped                ;
; E2_LOW                        ; 1                         ; Untyped                ;
; E3_LOW                        ; 1                         ; Untyped                ;
; L0_INITIAL                    ; 1                         ; Untyped                ;
; L1_INITIAL                    ; 1                         ; Untyped                ;
; G0_INITIAL                    ; 1                         ; Untyped                ;
; G1_INITIAL                    ; 1                         ; Untyped                ;
; G2_INITIAL                    ; 1                         ; Untyped                ;
; G3_INITIAL                    ; 1                         ; Untyped                ;
; E0_INITIAL                    ; 1                         ; Untyped                ;
; E1_INITIAL                    ; 1                         ; Untyped                ;
; E2_INITIAL                    ; 1                         ; Untyped                ;
; E3_INITIAL                    ; 1                         ; Untyped                ;
; L0_MODE                       ; BYPASS                    ; Untyped                ;
; L1_MODE                       ; BYPASS                    ; Untyped                ;
; G0_MODE                       ; BYPASS                    ; Untyped                ;
; G1_MODE                       ; BYPASS                    ; Untyped                ;
; G2_MODE                       ; BYPASS                    ; Untyped                ;
; G3_MODE                       ; BYPASS                    ; Untyped                ;
; E0_MODE                       ; BYPASS                    ; Untyped                ;
; E1_MODE                       ; BYPASS                    ; Untyped                ;
; E2_MODE                       ; BYPASS                    ; Untyped                ;
; E3_MODE                       ; BYPASS                    ; Untyped                ;
; L0_PH                         ; 0                         ; Untyped                ;
; L1_PH                         ; 0                         ; Untyped                ;
; G0_PH                         ; 0                         ; Untyped                ;
; G1_PH                         ; 0                         ; Untyped                ;
; G2_PH                         ; 0                         ; Untyped                ;
; G3_PH                         ; 0                         ; Untyped                ;
; E0_PH                         ; 0                         ; Untyped                ;
; E1_PH                         ; 0                         ; Untyped                ;
; E2_PH                         ; 0                         ; Untyped                ;
; E3_PH                         ; 0                         ; Untyped                ;
; M_PH                          ; 0                         ; Untyped                ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                ;
; CLK0_COUNTER                  ; G0                        ; Untyped                ;
; CLK1_COUNTER                  ; G0                        ; Untyped                ;
; CLK2_COUNTER                  ; G0                        ; Untyped                ;
; CLK3_COUNTER                  ; G0                        ; Untyped                ;
; CLK4_COUNTER                  ; G0                        ; Untyped                ;
; CLK5_COUNTER                  ; G0                        ; Untyped                ;
; CLK6_COUNTER                  ; E0                        ; Untyped                ;
; CLK7_COUNTER                  ; E1                        ; Untyped                ;
; CLK8_COUNTER                  ; E2                        ; Untyped                ;
; CLK9_COUNTER                  ; E3                        ; Untyped                ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                ;
; M_TIME_DELAY                  ; 0                         ; Untyped                ;
; N_TIME_DELAY                  ; 0                         ; Untyped                ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                ;
; VCO_POST_SCALE                ; 0                         ; Untyped                ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E              ; Untyped                ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                ;
; PORT_CLK1                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                ;
; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                ;
; CBXI_PARAMETER                ; altpll0_altpll            ; Untyped                ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                ;
; WIDTH_CLOCK                   ; 5                         ; Signed Integer         ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                ;
; DEVICE_FAMILY                 ; Cyclone IV E              ; Untyped                ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE         ;
+-------------------------------+---------------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FifoA:FifoAnalog|dcfifo:dcfifo_component ;
+-------------------------+--------------+----------------------------------------------+
; Parameter Name          ; Value        ; Type                                         ;
+-------------------------+--------------+----------------------------------------------+
; WIDTH_BYTEENA           ; 1            ; Untyped                                      ;
; AUTO_CARRY_CHAINS       ; ON           ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF          ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS     ; ON           ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF          ; IGNORE_CASCADE                               ;
; LPM_WIDTH               ; 48           ; Signed Integer                               ;
; LPM_NUMWORDS            ; 4096         ; Signed Integer                               ;
; LPM_WIDTHU              ; 12           ; Signed Integer                               ;
; LPM_SHOWAHEAD           ; OFF          ; Untyped                                      ;
; UNDERFLOW_CHECKING      ; ON           ; Untyped                                      ;
; OVERFLOW_CHECKING       ; ON           ; Untyped                                      ;
; USE_EAB                 ; ON           ; Untyped                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF          ; Untyped                                      ;
; DELAY_RDUSEDW           ; 1            ; Untyped                                      ;
; DELAY_WRUSEDW           ; 1            ; Untyped                                      ;
; RDSYNC_DELAYPIPE        ; 5            ; Signed Integer                               ;
; WRSYNC_DELAYPIPE        ; 5            ; Signed Integer                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE        ; Untyped                                      ;
; MAXIMIZE_SPEED          ; 5            ; Untyped                                      ;
; DEVICE_FAMILY           ; Cyclone IV E ; Untyped                                      ;
; ADD_USEDW_MSB_BIT       ; OFF          ; Untyped                                      ;
; WRITE_ACLR_SYNCH        ; OFF          ; Untyped                                      ;
; READ_ACLR_SYNCH         ; OFF          ; Untyped                                      ;
; CBXI_PARAMETER          ; dcfifo_s1l1  ; Untyped                                      ;
+-------------------------+--------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FifoD:FifoDigital|dcfifo:dcfifo_component ;
+-------------------------+--------------+-----------------------------------------------+
; Parameter Name          ; Value        ; Type                                          ;
+-------------------------+--------------+-----------------------------------------------+
; WIDTH_BYTEENA           ; 1            ; Untyped                                       ;
; AUTO_CARRY_CHAINS       ; ON           ; AUTO_CARRY                                    ;
; IGNORE_CARRY_BUFFERS    ; OFF          ; IGNORE_CARRY                                  ;
; AUTO_CASCADE_CHAINS     ; ON           ; AUTO_CASCADE                                  ;
; IGNORE_CASCADE_BUFFERS  ; OFF          ; IGNORE_CASCADE                                ;
; LPM_WIDTH               ; 8            ; Signed Integer                                ;
; LPM_NUMWORDS            ; 32768        ; Signed Integer                                ;
; LPM_WIDTHU              ; 15           ; Signed Integer                                ;
; LPM_SHOWAHEAD           ; OFF          ; Untyped                                       ;
; UNDERFLOW_CHECKING      ; ON           ; Untyped                                       ;
; OVERFLOW_CHECKING       ; ON           ; Untyped                                       ;
; USE_EAB                 ; ON           ; Untyped                                       ;
; ADD_RAM_OUTPUT_REGISTER ; OFF          ; Untyped                                       ;
; DELAY_RDUSEDW           ; 1            ; Untyped                                       ;
; DELAY_WRUSEDW           ; 1            ; Untyped                                       ;
; RDSYNC_DELAYPIPE        ; 5            ; Signed Integer                                ;
; WRSYNC_DELAYPIPE        ; 5            ; Signed Integer                                ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE        ; Untyped                                       ;
; MAXIMIZE_SPEED          ; 5            ; Untyped                                       ;
; DEVICE_FAMILY           ; Cyclone IV E ; Untyped                                       ;
; ADD_USEDW_MSB_BIT       ; OFF          ; Untyped                                       ;
; WRITE_ACLR_SYNCH        ; OFF          ; Untyped                                       ;
; READ_ACLR_SYNCH         ; OFF          ; Untyped                                       ;
; CBXI_PARAMETER          ; dcfifo_h0l1  ; Untyped                                       ;
+-------------------------+--------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                          ;
+-------------------------------+---------------------------------------+
; Name                          ; Value                                 ;
+-------------------------------+---------------------------------------+
; Number of entity instances    ; 1                                     ;
; Entity Instance               ; altpll0:60MHz|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                ;
;     -- PLL_TYPE               ; AUTO                                  ;
;     -- PRIMARY_CLOCK          ; INCLK0                                ;
;     -- INCLK0_INPUT_FREQUENCY ; 10000                                 ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                     ;
;     -- VCO_MULTIPLY_BY        ; 0                                     ;
;     -- VCO_DIVIDE_BY          ; 0                                     ;
+-------------------------------+---------------------------------------+


+------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                           ;
+----------------------------+-------------------------------------------+
; Name                       ; Value                                     ;
+----------------------------+-------------------------------------------+
; Number of entity instances ; 2                                         ;
; Entity Instance            ; FifoA:FifoAnalog|dcfifo:dcfifo_component  ;
;     -- FIFO Type           ; Dual Clock                                ;
;     -- LPM_WIDTH           ; 48                                        ;
;     -- LPM_NUMWORDS        ; 4096                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                       ;
;     -- USE_EAB             ; ON                                        ;
; Entity Instance            ; FifoD:FifoDigital|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                ;
;     -- LPM_WIDTH           ; 8                                         ;
;     -- LPM_NUMWORDS        ; 32768                                     ;
;     -- LPM_SHOWAHEAD       ; OFF                                       ;
;     -- USE_EAB             ; ON                                        ;
+----------------------------+-------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:33     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Info: Processing started: Thu Mar 12 16:09:10 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ACync -c ACync
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file acync_block.bdf
    Info (12023): Found entity 1: ACync_block
Info (12021): Found 1 design units, including 1 entities, in source file uberacync.sv
    Info (12023): Found entity 1: uberACync
Info (12021): Found 1 design units, including 1 entities, in source file altpll0.v
    Info (12023): Found entity 1: altpll0
Info (12021): Found 1 design units, including 1 entities, in source file fifod.v
    Info (12023): Found entity 1: FifoD
Info (12021): Found 1 design units, including 1 entities, in source file fifoa.v
    Info (12023): Found entity 1: FifoA
Info (12127): Elaborating entity "ACync_block" for the top level hierarchy
Info (12128): Elaborating entity "uberACync" for hierarchy "uberACync:Sink"
Warning (10230): Verilog HDL assignment warning at uberACync.sv(365): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at uberACync.sv(375): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at uberACync.sv(385): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at uberACync.sv(395): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at uberACync.sv(670): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at uberACync.sv(680): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at uberACync.sv(690): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at uberACync.sv(700): truncated value with size 32 to match size of target (12)
Info (12128): Elaborating entity "altpll0" for hierarchy "altpll0:60MHz"
Info (12128): Elaborating entity "altpll" for hierarchy "altpll0:60MHz|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "altpll0:60MHz|altpll:altpll_component"
Info (12133): Instantiated megafunction "altpll0:60MHz|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "5"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "3"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "10000"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll0"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/altpll0_altpll.v
    Info (12023): Found entity 1: altpll0_altpll
Info (12128): Elaborating entity "altpll0_altpll" for hierarchy "altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated"
Info (12128): Elaborating entity "FifoA" for hierarchy "FifoA:FifoAnalog"
Info (12128): Elaborating entity "dcfifo" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component"
Info (12130): Elaborated megafunction instantiation "FifoA:FifoAnalog|dcfifo:dcfifo_component"
Info (12133): Instantiated megafunction "FifoA:FifoAnalog|dcfifo:dcfifo_component" with the following parameter:
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_numwords" = "4096"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "48"
    Info (12134): Parameter "lpm_widthu" = "12"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "5"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_s1l1.tdf
    Info (12023): Found entity 1: dcfifo_s1l1
Info (12128): Elaborating entity "dcfifo_s1l1" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_877.tdf
    Info (12023): Found entity 1: a_graycounter_877
Info (12128): Elaborating entity "a_graycounter_877" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_877:rdptr_g1p"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_4lc.tdf
    Info (12023): Found entity 1: a_graycounter_4lc
Info (12128): Elaborating entity "a_graycounter_4lc" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|a_graycounter_4lc:wrptr_g1p"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_sm31.tdf
    Info (12023): Found entity 1: altsyncram_sm31
Info (12128): Elaborating entity "altsyncram_sm31" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|altsyncram_sm31:fifo_ram"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tld.tdf
    Info (12023): Found entity 1: alt_synch_pipe_tld
Info (12128): Elaborating entity "alt_synch_pipe_tld" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_se9.tdf
    Info (12023): Found entity 1: dffpipe_se9
Info (12128): Elaborating entity "dffpipe_se9" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_uld.tdf
    Info (12023): Found entity 1: alt_synch_pipe_uld
Info (12128): Elaborating entity "alt_synch_pipe_uld" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_te9.tdf
    Info (12023): Found entity 1: dffpipe_te9
Info (12128): Elaborating entity "dffpipe_te9" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_d66.tdf
    Info (12023): Found entity 1: cmpr_d66
Info (12128): Elaborating entity "cmpr_d66" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_d66:rdempty_eq_comp1_lsb"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_c66.tdf
    Info (12023): Found entity 1: cmpr_c66
Info (12128): Elaborating entity "cmpr_c66" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_c66:rdempty_eq_comp1_msb"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_q76.tdf
    Info (12023): Found entity 1: cmpr_q76
Info (12128): Elaborating entity "cmpr_q76" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|cmpr_q76:rdfull_eq_comp"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_j28.tdf
    Info (12023): Found entity 1: mux_j28
Info (12128): Elaborating entity "mux_j28" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_s1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux"
Info (12128): Elaborating entity "FifoD" for hierarchy "FifoD:FifoDigital"
Info (12128): Elaborating entity "dcfifo" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component"
Info (12130): Elaborated megafunction instantiation "FifoD:FifoDigital|dcfifo:dcfifo_component"
Info (12133): Instantiated megafunction "FifoD:FifoDigital|dcfifo:dcfifo_component" with the following parameter:
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_numwords" = "32768"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "8"
    Info (12134): Parameter "lpm_widthu" = "15"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "5"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_h0l1.tdf
    Info (12023): Found entity 1: dcfifo_h0l1
Info (12128): Elaborating entity "dcfifo_h0l1" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_b77.tdf
    Info (12023): Found entity 1: a_graycounter_b77
Info (12128): Elaborating entity "a_graycounter_b77" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_7lc.tdf
    Info (12023): Found entity 1: a_graycounter_7lc
Info (12128): Elaborating entity "a_graycounter_7lc" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qj31.tdf
    Info (12023): Found entity 1: altsyncram_qj31
Info (12128): Elaborating entity "altsyncram_qj31" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_d87.tdf
    Info (12023): Found entity 1: decode_d87
Info (12128): Elaborating entity "decode_d87" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_t28.tdf
    Info (12023): Found entity 1: mux_t28
Info (12128): Elaborating entity "mux_t28" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|mux_t28:mux13"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_0md.tdf
    Info (12023): Found entity 1: alt_synch_pipe_0md
Info (12128): Elaborating entity "alt_synch_pipe_0md" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ve9.tdf
    Info (12023): Found entity 1: dffpipe_ve9
Info (12128): Elaborating entity "dffpipe_ve9" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_1md.tdf
    Info (12023): Found entity 1: alt_synch_pipe_1md
Info (12128): Elaborating entity "alt_synch_pipe_1md" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_0f9.tdf
    Info (12023): Found entity 1: dffpipe_0f9
Info (12128): Elaborating entity "dffpipe_0f9" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf
    Info (12023): Found entity 1: cmpr_e66
Info (12128): Elaborating entity "cmpr_e66" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_e66:rdempty_eq_comp1_lsb"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_t76.tdf
    Info (12023): Found entity 1: cmpr_t76
Info (12128): Elaborating entity "cmpr_t76" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp"
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286030): Timing-Driven Synthesis is running
Info (17049): 6 registers lost all their fanouts during netlist optimizations.
Info (128000): Starting physical synthesis optimizations for speed
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity dcfifo_h0l1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a* 
    Info (332165): Entity dcfifo_s1l1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_te9:dffpipe15|dffe16a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_se9:dffpipe12|dffe13a* 
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ACync.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained generated clocks found in the design
Info (332144): No user constrained base clocks found in the design
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info (332127): Assuming a default timing requirement
Info (332111): Found 6 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   16.666 60MHz|altpll_component|auto_generated|pll1|clk[0]
    Info (332111):   10.000       Clk100
    Info (332111):    1.000 uberACync:Sink|FifoAnaRdClk
    Info (332111):    1.000 uberACync:Sink|FifoAnaWrClk
    Info (332111):    1.000 uberACync:Sink|FifoDigRdClk
    Info (332111):    1.000 uberACync:Sink|FifoDigWrClk
Info (128002): Starting physical synthesis algorithm register retiming
Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 860 ps
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 2678 ps
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:03
Info (144001): Generated suppressed messages file C:/Projects/Archives/2015 ACync/Altera/output_files/ACync.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 1385 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 18 input pins
    Info (21059): Implemented 33 output pins
    Info (21061): Implemented 1253 logic cells
    Info (21064): Implemented 80 RAM segments
    Info (21065): Implemented 1 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Peak virtual memory: 562 megabytes
    Info: Processing ended: Thu Mar 12 16:09:48 2015
    Info: Elapsed time: 00:00:38
    Info: Total CPU time (on all processors): 00:00:37


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Projects/Archives/2015 ACync/Altera/output_files/ACync.map.smsg.


