Fitter report for ACync
Tue Mar 31 14:48:28 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. I/O Assignment Warnings
  6. Ignored Assignments
  7. Incremental Compilation Preservation Summary
  8. Incremental Compilation Partition Settings
  9. Incremental Compilation Placement Preservation
 10. Pin-Out File
 11. Fitter Resource Usage Summary
 12. Fitter Partition Statistics
 13. Input Pins
 14. Output Pins
 15. Dual Purpose and Dedicated Pins
 16. I/O Bank Usage
 17. All Package Pins
 18. PLL Summary
 19. PLL Usage
 20. Fitter Resource Utilization by Entity
 21. Delay Chain Summary
 22. Pad To Core Delay Chain Fanout
 23. Control Signals
 24. Global & Other Fast Signals
 25. Non-Global High Fan-Out Signals
 26. Fitter RAM Summary
 27. Routing Usage Summary
 28. LAB Logic Elements
 29. LAB-wide Signals
 30. LAB Signals Sourced
 31. LAB Signals Sourced Out
 32. LAB Distinct Inputs
 33. I/O Rules Summary
 34. I/O Rules Details
 35. I/O Rules Matrix
 36. Fitter Device Options
 37. Operating Settings and Conditions
 38. Estimated Delay Added for Hold Timing Summary
 39. Estimated Delay Added for Hold Timing Details
 40. Fitter Messages
 41. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Fitter Summary                                                                   ;
+------------------------------------+---------------------------------------------+
; Fitter Status                      ; Successful - Tue Mar 31 14:48:28 2015       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; ACync                                       ;
; Top-level Entity Name              ; ACync_block                                 ;
; Family                             ; Cyclone IV E                                ;
; Device                             ; EP4CE22E22C8                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 967 / 22,320 ( 4 % )                        ;
;     Total combinational functions  ; 739 / 22,320 ( 3 % )                        ;
;     Dedicated logic registers      ; 603 / 22,320 ( 3 % )                        ;
; Total registers                    ; 603                                         ;
; Total pins                         ; 56 / 80 ( 70 % )                            ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 524,288 / 608,256 ( 86 % )                  ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                             ;
; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
+------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                            ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                                     ; Setting                               ; Default Value                         ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                                     ; EP4CE22E22C8                          ;                                       ;
; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
; Device I/O Standard                                                        ; 3.3-V LVCMOS                          ;                                       ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; On                                    ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; On                                    ; Off                                   ;
; Perform Register Retiming for Performance                                  ; On                                    ; Off                                   ;
; Fitter Effort                                                              ; Fast Fit                              ; Auto Fit                              ;
; Synchronizer Identification                                                ; Auto                                  ; Off                                   ;
; Use smart compilation                                                      ; Off                                   ; Off                                   ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
; Enable compact report table                                                ; Off                                   ; Off                                   ;
; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
; SSN Optimization                                                           ; Off                                   ; Off                                   ;
; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
; PCI I/O                                                                    ; Off                                   ; Off                                   ;
; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
; Auto Delay Chains                                                          ; On                                    ; On                                    ;
; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
; Auto Global Clock                                                          ; On                                    ; On                                    ;
; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.19        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  18.8%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+-----------------------------------------------------+
; I/O Assignment Warnings                             ;
+--------------+--------------------------------------+
; Pin Name     ; Reason                               ;
+--------------+--------------------------------------+
; Prbs         ; Missing drive strength               ;
; AdcClk       ; Missing drive strength and slew rate ;
; DacLoad      ; Missing drive strength               ;
; PotClk       ; Missing drive strength               ;
; PotStart     ; Missing drive strength               ;
; Led          ; Missing drive strength               ;
; DacWr        ; Missing drive strength               ;
; AdcConvert   ; Missing drive strength and slew rate ;
; DacAddr[3]   ; Missing drive strength               ;
; DacAddr[2]   ; Missing drive strength               ;
; DacAddr[1]   ; Missing drive strength               ;
; DacAddr[0]   ; Missing drive strength               ;
; DacDat[15]   ; Missing drive strength               ;
; DacDat[14]   ; Missing drive strength               ;
; DacDat[13]   ; Missing drive strength               ;
; DacDat[12]   ; Missing drive strength               ;
; DacDat[11]   ; Missing drive strength               ;
; DacDat[10]   ; Missing drive strength               ;
; DacDat[9]    ; Missing drive strength               ;
; DacDat[8]    ; Missing drive strength               ;
; DacDat[7]    ; Missing drive strength               ;
; DacDat[6]    ; Missing drive strength               ;
; DacDat[5]    ; Missing drive strength               ;
; DacDat[4]    ; Missing drive strength               ;
; DacDat[3]    ; Missing drive strength               ;
; DacDat[2]    ; Missing drive strength               ;
; DacDat[1]    ; Missing drive strength               ;
; DacDat[0]    ; Missing drive strength               ;
; DigOut[7]    ; Missing drive strength               ;
; DigOut[6]    ; Missing drive strength               ;
; DigOut[5]    ; Missing drive strength               ;
; DigOut[4]    ; Missing drive strength               ;
; DigOut[3]    ; Missing drive strength               ;
; DigOut[2]    ; Missing drive strength               ;
; DigOut[1]    ; Missing drive strength               ;
; DigOut[0]    ; Missing drive strength               ;
; ExtendOut[1] ; Missing drive strength               ;
; ExtendOut[0] ; Missing drive strength               ;
+--------------+--------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Ignored Assignments                                                                                                             ;
+-----------------------------+----------------+--------------+-------------+------------------------+----------------------------+
; Name                        ; Ignored Entity ; Ignored From ; Ignored To  ; Ignored Value          ; Ignored Source             ;
+-----------------------------+----------------+--------------+-------------+------------------------+----------------------------+
; Synchronizer Identification ; dcfifo_h0l1    ;              ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
; Synchronizer Identification ; dcfifo_o1l1    ;              ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+-----------------------------+----------------+--------------+-------------+------------------------+----------------------------+


+---------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary                                                      ;
+---------------------+---------------------+----------------------------+--------------------------+
; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+---------------------+----------------------------+--------------------------+
; Placement (by node) ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 1566 ) ; 0.00 % ( 0 / 1566 )        ; 0.00 % ( 0 / 1566 )      ;
;     -- Achieved     ; 0.00 % ( 0 / 1566 ) ; 0.00 % ( 0 / 1566 )        ; 0.00 % ( 0 / 1566 )      ;
;                     ;                     ;                            ;                          ;
; Routing (by net)    ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+---------------------+---------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                                                     ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top                            ; 0.00 % ( 0 / 1556 )   ; N/A                     ; Source File       ; N/A                 ;       ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Projects/2015 ACync/Altera/output_files/ACync.pin.


+--------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                            ;
+---------------------------------------------+----------------------------+
; Resource                                    ; Usage                      ;
+---------------------------------------------+----------------------------+
; Total logic elements                        ; 967 / 22,320 ( 4 % )       ;
;     -- Combinational with no register       ; 364                        ;
;     -- Register only                        ; 228                        ;
;     -- Combinational with a register        ; 375                        ;
;                                             ;                            ;
; Logic element usage by number of LUT inputs ;                            ;
;     -- 4 input functions                    ; 465                        ;
;     -- 3 input functions                    ; 100                        ;
;     -- <=2 input functions                  ; 174                        ;
;     -- Register only                        ; 228                        ;
;                                             ;                            ;
; Logic elements by mode                      ;                            ;
;     -- normal mode                          ; 650                        ;
;     -- arithmetic mode                      ; 89                         ;
;                                             ;                            ;
; Total registers*                            ; 603 / 22,648 ( 3 % )       ;
;     -- Dedicated logic registers            ; 603 / 22,320 ( 3 % )       ;
;     -- I/O registers                        ; 0 / 328 ( 0 % )            ;
;                                             ;                            ;
; Total LABs:  partially or completely used   ; 79 / 1,395 ( 6 % )         ;
; Virtual pins                                ; 0                          ;
; I/O pins                                    ; 56 / 80 ( 70 % )           ;
;     -- Clock pins                           ; 6 / 7 ( 86 % )             ;
;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )              ;
;                                             ;                            ;
; Global signals                              ; 6                          ;
; M9Ks                                        ; 64 / 66 ( 97 % )           ;
; Total block memory bits                     ; 524,288 / 608,256 ( 86 % ) ;
; Total block memory implementation bits      ; 589,824 / 608,256 ( 97 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )            ;
; PLLs                                        ; 1 / 4 ( 25 % )             ;
; Global clocks                               ; 6 / 20 ( 30 % )            ;
; JTAGs                                       ; 0 / 1 ( 0 % )              ;
; CRC blocks                                  ; 0 / 1 ( 0 % )              ;
; ASMI blocks                                 ; 0 / 1 ( 0 % )              ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )              ;
; Average interconnect usage (total/H/V)      ; 4% / 3% / 4%               ;
; Peak interconnect usage (total/H/V)         ; 12% / 10% / 15%            ;
; Maximum fan-out                             ; 390                        ;
; Highest non-global fan-out                  ; 89                         ;
; Total fan-out                               ; 6784                       ;
; Average fan-out                             ; 3.93                       ;
+---------------------------------------------+----------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                        ;
+---------------------------------------------+---------------------+--------------------------------+
; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
+---------------------------------------------+---------------------+--------------------------------+
; Difficulty Clustering Region                ; Low                 ; Low                            ;
;                                             ;                     ;                                ;
; Total logic elements                        ; 967 / 22320 ( 4 % ) ; 0 / 22320 ( 0 % )              ;
;     -- Combinational with no register       ; 364                 ; 0                              ;
;     -- Register only                        ; 228                 ; 0                              ;
;     -- Combinational with a register        ; 375                 ; 0                              ;
;                                             ;                     ;                                ;
; Logic element usage by number of LUT inputs ;                     ;                                ;
;     -- 4 input functions                    ; 465                 ; 0                              ;
;     -- 3 input functions                    ; 100                 ; 0                              ;
;     -- <=2 input functions                  ; 174                 ; 0                              ;
;     -- Register only                        ; 228                 ; 0                              ;
;                                             ;                     ;                                ;
; Logic elements by mode                      ;                     ;                                ;
;     -- normal mode                          ; 650                 ; 0                              ;
;     -- arithmetic mode                      ; 89                  ; 0                              ;
;                                             ;                     ;                                ;
; Total registers                             ; 603                 ; 0                              ;
;     -- Dedicated logic registers            ; 603 / 22320 ( 3 % ) ; 0 / 22320 ( 0 % )              ;
;     -- I/O registers                        ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Total LABs:  partially or completely used   ; 79 / 1395 ( 6 % )   ; 0 / 1395 ( 0 % )               ;
;                                             ;                     ;                                ;
; Virtual pins                                ; 0                   ; 0                              ;
; I/O pins                                    ; 56                  ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )     ; 0 / 132 ( 0 % )                ;
; Total memory bits                           ; 524288              ; 0                              ;
; Total RAM block bits                        ; 589824              ; 0                              ;
; PLL                                         ; 0 / 4 ( 0 % )       ; 1 / 4 ( 25 % )                 ;
; M9K                                         ; 64 / 66 ( 96 % )    ; 0 / 66 ( 0 % )                 ;
; Clock control block                         ; 5 / 24 ( 20 % )     ; 1 / 24 ( 4 % )                 ;
;                                             ;                     ;                                ;
; Connections                                 ;                     ;                                ;
;     -- Input Connections                    ; 273                 ; 1                              ;
;     -- Registered Input Connections         ; 273                 ; 0                              ;
;     -- Output Connections                   ; 1                   ; 273                            ;
;     -- Registered Output Connections        ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Internal Connections                        ;                     ;                                ;
;     -- Total Connections                    ; 6842                ; 280                            ;
;     -- Registered Connections               ; 3902                ; 0                              ;
;                                             ;                     ;                                ;
; External Connections                        ;                     ;                                ;
;     -- Top                                  ; 0                   ; 274                            ;
;     -- hard_block:auto_generated_inst       ; 274                 ; 0                              ;
;                                             ;                     ;                                ;
; Partition Interface                         ;                     ;                                ;
;     -- Input Ports                          ; 18                  ; 1                              ;
;     -- Output Ports                         ; 38                  ; 1                              ;
;     -- Bidir Ports                          ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Registered Ports                            ;                     ;                                ;
;     -- Registered Input Ports               ; 0                   ; 0                              ;
;     -- Registered Output Ports              ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Port Connectivity                           ;                     ;                                ;
;     -- Input Ports driven by GND            ; 0                   ; 0                              ;
;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
;     -- Input Ports with no Source           ; 0                   ; 0                              ;
;     -- Output Ports with no Source          ; 0                   ; 0                              ;
;     -- Input Ports with no Fanout           ; 0                   ; 0                              ;
;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
+---------------------------------------------+---------------------+--------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                       ;
+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; AC60Hz      ; 53    ; 3        ; 27           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; Adc1        ; 86    ; 5        ; 53           ; 14           ; 7            ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; Adc2        ; 87    ; 5        ; 53           ; 14           ; 0            ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; Adc3        ; 88    ; 5        ; 53           ; 17           ; 21           ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; Adc4        ; 89    ; 5        ; 53           ; 17           ; 14           ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; Clk100      ; 23    ; 1        ; 0            ; 16           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[0]    ; 30    ; 2        ; 0            ; 11           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[1]    ; 31    ; 2        ; 0            ; 10           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[2]    ; 32    ; 2        ; 0            ; 7            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[3]    ; 33    ; 2        ; 0            ; 6            ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[4]    ; 39    ; 3        ; 1            ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[5]    ; 42    ; 3        ; 3            ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[6]    ; 43    ; 3        ; 5            ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; DigIn[7]    ; 44    ; 3        ; 5            ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; ExtendIn[0] ; 55    ; 4        ; 27           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; ExtendIn[1] ; 54    ; 4        ; 27           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; Master      ; 24    ; 2        ; 0            ; 16           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
; PotDat      ; 126   ; 7        ; 25           ; 34           ; 0            ; 9                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVCMOS ; --                        ; User                 ;
+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; AdcClk       ; 85    ; 5        ; 53           ; 13           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; AdcConvert   ; 83    ; 5        ; 53           ; 11           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacAddr[0]   ; 67    ; 4        ; 43           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacAddr[1]   ; 66    ; 4        ; 43           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacAddr[2]   ; 65    ; 4        ; 38           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacAddr[3]   ; 64    ; 4        ; 38           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[0]    ; 71    ; 4        ; 49           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[10]   ; 110   ; 7        ; 51           ; 34           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[11]   ; 111   ; 7        ; 49           ; 34           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[12]   ; 112   ; 7        ; 47           ; 34           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[13]   ; 113   ; 7        ; 45           ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[14]   ; 114   ; 7        ; 45           ; 34           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[15]   ; 115   ; 7        ; 45           ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[1]    ; 72    ; 4        ; 49           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[2]    ; 98    ; 6        ; 53           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[3]    ; 99    ; 6        ; 53           ; 20           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[4]    ; 100   ; 6        ; 53           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[5]    ; 101   ; 6        ; 53           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[6]    ; 103   ; 6        ; 53           ; 22           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[7]    ; 104   ; 6        ; 53           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[8]    ; 105   ; 6        ; 53           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacDat[9]    ; 106   ; 6        ; 53           ; 30           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacLoad      ; 69    ; 4        ; 47           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DacWr        ; 68    ; 4        ; 45           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[0]    ; 125   ; 7        ; 29           ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[1]    ; 132   ; 8        ; 20           ; 34           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[2]    ; 133   ; 8        ; 20           ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[3]    ; 135   ; 8        ; 18           ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[4]    ; 136   ; 8        ; 18           ; 34           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[5]    ; 137   ; 8        ; 16           ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[6]    ; 141   ; 8        ; 7            ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; DigOut[7]    ; 142   ; 8        ; 3            ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; ExtendOut[0] ; 58    ; 4        ; 34           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; ExtendOut[1] ; 59    ; 4        ; 34           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Led          ; 144   ; 8        ; 1            ; 34           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; PotClk       ; 120   ; 7        ; 38           ; 34           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; PotStart     ; 121   ; 7        ; 34           ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; Prbs         ; 143   ; 8        ; 1            ; 34           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                                    ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
; Location ; Pin Name                               ; Reserved As              ; User Signal Name        ; Pin Type                  ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
; 6        ; DIFFIO_L3n, DATA1, ASDO                ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
; 8        ; DIFFIO_L4p, FLASH_nCE, nCSO            ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
; 9        ; nSTATUS                                ; -                        ; -                       ; Dedicated Programming Pin ;
; 12       ; DCLK                                   ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
; 13       ; DATA0                                  ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
; 14       ; nCONFIG                                ; -                        ; -                       ; Dedicated Programming Pin ;
; 21       ; nCE                                    ; -                        ; -                       ; Dedicated Programming Pin ;
; 86       ; DIFFIO_R9n, DEV_OE                     ; Use as regular IO        ; Adc1                    ; Dual Purpose Pin          ;
; 87       ; DIFFIO_R9p, DEV_CLRn                   ; Use as regular IO        ; Adc2                    ; Dual Purpose Pin          ;
; 92       ; CONF_DONE                              ; -                        ; -                       ; Dedicated Programming Pin ;
; 94       ; MSEL0                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; 96       ; MSEL1                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; 97       ; MSEL2                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; 97       ; MSEL3                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; 98       ; DIFFIO_R5n, INIT_DONE                  ; Use as regular IO        ; DacDat[2]               ; Dual Purpose Pin          ;
; 99       ; DIFFIO_R5p, CRC_ERROR                  ; Use as regular IO        ; DacDat[3]               ; Dual Purpose Pin          ;
; 101      ; DIFFIO_R4n, nCEO                       ; Use as programming pin   ; DacDat[5]               ; Dual Purpose Pin          ;
; 103      ; DIFFIO_R4p, CLKUSR                     ; Use as regular IO        ; DacDat[6]               ; Dual Purpose Pin          ;
; 106      ; DIFFIO_R1n, PADD20, DQS2R/CQ3R,CDPCLK5 ; Use as regular IO        ; DacDat[9]               ; Dual Purpose Pin          ;
; 120      ; DIFFIO_T19n, PADD1                     ; Use as regular IO        ; PotClk                  ; Dual Purpose Pin          ;
; 121      ; DIFFIO_T17p, PADD4, DQS2T/CQ3T,DPCLK8  ; Use as regular IO        ; PotStart                ; Dual Purpose Pin          ;
; 125      ; DIFFIO_T13p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO        ; DigOut[0]               ; Dual Purpose Pin          ;
; 132      ; DIFFIO_T10n, DATA2                     ; Use as regular IO        ; DigOut[1]               ; Dual Purpose Pin          ;
; 133      ; DIFFIO_T10p, DATA3                     ; Use as regular IO        ; DigOut[2]               ; Dual Purpose Pin          ;
; 135      ; DIFFIO_T9p, DATA4                      ; Use as regular IO        ; DigOut[3]               ; Dual Purpose Pin          ;
; 137      ; DATA5                                  ; Use as regular IO        ; DigOut[5]               ; Dual Purpose Pin          ;
; 142      ; DATA12, DQS1T/CQ1T#,CDPCLK7            ; Use as regular IO        ; DigOut[7]               ; Dual Purpose Pin          ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+


+------------------------------------------------------------+
; I/O Bank Usage                                             ;
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1        ; 5 / 8 ( 63 % )   ; 3.3V          ; --           ;
; 2        ; 5 / 7 ( 71 % )   ; 3.3V          ; --           ;
; 3        ; 5 / 10 ( 50 % )  ; 3.3V          ; --           ;
; 4        ; 12 / 13 ( 92 % ) ; 3.3V          ; --           ;
; 5        ; 6 / 9 ( 67 % )   ; 2.5V          ; --           ;
; 6        ; 8 / 10 ( 80 % )  ; 3.3V          ; --           ;
; 7        ; 10 / 12 ( 83 % ) ; 3.3V          ; --           ;
; 8        ; 9 / 11 ( 82 % )  ; 3.3V          ; --           ;
+----------+------------------+---------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                                        ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1        ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 2        ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 3        ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 4        ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 5        ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 6        ; 7          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; On           ;
; 7        ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 8        ; 9          ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; On           ;
; 9        ; 11         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 10       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 11       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 12       ; 17         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; On           ;
; 13       ; 18         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; N               ; no       ; On           ;
; 14       ; 19         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 15       ; 20         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 16       ; 21         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 17       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 18       ; 22         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; 19       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 20       ; 23         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
; 21       ; 24         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 22       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 23       ; 26         ; 1        ; Clk100                                                    ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 24       ; 27         ; 2        ; Master                                                    ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 25       ; 28         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 26       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 27       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 28       ; 31         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 29       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 30       ; 38         ; 2        ; DigIn[0]                                                  ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 31       ; 40         ; 2        ; DigIn[1]                                                  ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 32       ; 45         ; 2        ; DigIn[2]                                                  ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 33       ; 46         ; 2        ; DigIn[3]                                                  ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 34       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 35       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 36       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 37       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 38       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 39       ; 54         ; 3        ; DigIn[4]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 40       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 41       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 42       ; 59         ; 3        ; DigIn[5]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 43       ; 60         ; 3        ; DigIn[6]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 44       ; 61         ; 3        ; DigIn[7]                                                  ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 45       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 46       ; 67         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 47       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 48       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 49       ; 79         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 50       ; 81         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 51       ; 82         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 52       ; 86         ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 53       ; 87         ; 3        ; AC60Hz                                                    ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 54       ; 88         ; 4        ; ExtendIn[1]                                               ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 55       ; 89         ; 4        ; ExtendIn[0]                                               ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 56       ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 57       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 58       ; 96         ; 4        ; ExtendOut[0]                                              ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 59       ; 98         ; 4        ; ExtendOut[1]                                              ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 60       ; 99         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; 61       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 62       ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 63       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 64       ; 105        ; 4        ; DacAddr[3]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 65       ; 106        ; 4        ; DacAddr[2]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 66       ; 111        ; 4        ; DacAddr[1]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 67       ; 112        ; 4        ; DacAddr[0]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 68       ; 116        ; 4        ; DacWr                                                     ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 69       ; 117        ; 4        ; DacLoad                                                   ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 70       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 71       ; 119        ; 4        ; DacDat[0]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 72       ; 120        ; 4        ; DacDat[1]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 73       ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 74       ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 75       ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 76       ; 126        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 77       ; 127        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; 78       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 79       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 80       ; 134        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 81       ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 82       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 83       ; 138        ; 5        ; AdcConvert                                                ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 84       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 85       ; 141        ; 5        ; AdcClk                                                    ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 86       ; 142        ; 5        ; Adc1                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 87       ; 143        ; 5        ; Adc2                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 88       ; 148        ; 5        ; Adc3                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 89       ; 149        ; 5        ; Adc4                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 90       ; 150        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 91       ; 151        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; 92       ; 152        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 93       ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 94       ; 153        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 95       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 96       ; 154        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 97       ; 155        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 97       ; 156        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; 98       ; 159        ; 6        ; DacDat[2]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 99       ; 160        ; 6        ; DacDat[3]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 100      ; 161        ; 6        ; DacDat[4]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 101      ; 162        ; 6        ; DacDat[5]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 102      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 103      ; 163        ; 6        ; DacDat[6]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 104      ; 164        ; 6        ; DacDat[7]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 105      ; 167        ; 6        ; DacDat[8]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 106      ; 173        ; 6        ; DacDat[9]                                                 ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
; 107      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; 108      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 109      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 110      ; 178        ; 7        ; DacDat[10]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 111      ; 180        ; 7        ; DacDat[11]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 112      ; 181        ; 7        ; DacDat[12]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 113      ; 182        ; 7        ; DacDat[13]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 114      ; 183        ; 7        ; DacDat[14]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 115      ; 184        ; 7        ; DacDat[15]                                                ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 116      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 117      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 118      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 119      ; 190        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 120      ; 191        ; 7        ; PotClk                                                    ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 121      ; 197        ; 7        ; PotStart                                                  ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 122      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 123      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 124      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 125      ; 205        ; 7        ; DigOut[0]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 126      ; 209        ; 7        ; PotDat                                                    ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 127      ; 210        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 128      ; 211        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 129      ; 212        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; 130      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 131      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 132      ; 218        ; 8        ; DigOut[1]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 133      ; 219        ; 8        ; DigOut[2]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 134      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 135      ; 221        ; 8        ; DigOut[3]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 136      ; 224        ; 8        ; DigOut[4]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 137      ; 227        ; 8        ; DigOut[5]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 138      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; 139      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; 140      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; 141      ; 239        ; 8        ; DigOut[6]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 142      ; 242        ; 8        ; DigOut[7]                                                 ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 143      ; 245        ; 8        ; Prbs                                                      ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; 144      ; 246        ; 8        ; Led                                                       ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
; EPAD     ;            ;          ; GND                                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+----------------------------------------------------------------------------------------------------------+
; PLL Summary                                                                                              ;
+-------------------------------+--------------------------------------------------------------------------+
; Name                          ; altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|pll1 ;
+-------------------------------+--------------------------------------------------------------------------+
; SDC pin name                  ; 60MHz|altpll_component|auto_generated|pll1                               ;
; PLL mode                      ; Normal                                                                   ;
; Compensate clock              ; clock0                                                                   ;
; Compensated input/output pins ; --                                                                       ;
; Switchover type               ; --                                                                       ;
; Input frequency 0             ; 100.0 MHz                                                                ;
; Input frequency 1             ; --                                                                       ;
; Nominal PFD frequency         ; 100.0 MHz                                                                ;
; Nominal VCO frequency         ; 600.0 MHz                                                                ;
; VCO post scale K counter      ; 2                                                                        ;
; VCO frequency control         ; Auto                                                                     ;
; VCO phase shift step          ; 208 ps                                                                   ;
; VCO multiply                  ; --                                                                       ;
; VCO divide                    ; --                                                                       ;
; Freq min lock                 ; 50.01 MHz                                                                ;
; Freq max lock                 ; 108.37 MHz                                                               ;
; M VCO Tap                     ; 0                                                                        ;
; M Initial                     ; 1                                                                        ;
; M value                       ; 6                                                                        ;
; N value                       ; 1                                                                        ;
; Charge pump current           ; setting 1                                                                ;
; Loop filter resistance        ; setting 27                                                               ;
; Loop filter capacitance       ; setting 0                                                                ;
; Bandwidth                     ; 1.03 MHz to 1.97 MHz                                                     ;
; Bandwidth type                ; Medium                                                                   ;
; Real time reconfigurable      ; Off                                                                      ;
; Scan chain MIF file           ; --                                                                       ;
; Preserve PLL counter order    ; Off                                                                      ;
; PLL location                  ; PLL_1                                                                    ;
; Inclk0 signal                 ; Clk100                                                                   ;
; Inclk1 signal                 ; --                                                                       ;
; Inclk0 signal type            ; Dedicated Pin                                                            ;
; Inclk1 signal type            ; --                                                                       ;
+-------------------------------+--------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage                                                                                                                                                                                                                                                                                                        ;
+--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------+
; Name                                                                                 ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                      ;
+--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------+
; altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] ; clock0       ; 3    ; 5   ; 60.0 MHz         ; 0 (0 ps)    ; 4.50 (208 ps)    ; 50/50      ; C0      ; 10            ; 5/5 Even   ; --            ; 1       ; 0       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                            ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                   ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                ; Library Name ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |ACync_block                                 ; 967 (1)     ; 603 (0)                   ; 0 (0)         ; 524288      ; 64   ; 0            ; 0       ; 0         ; 56   ; 0            ; 364 (1)      ; 228 (0)           ; 375 (0)          ; |ACync_block                                                                                                                       ; work         ;
;    |FifoA:FifoAnalog|                        ; 193 (0)     ; 147 (0)                   ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 46 (0)       ; 78 (0)            ; 69 (0)           ; |ACync_block|FifoA:FifoAnalog                                                                                                      ; work         ;
;       |dcfifo:dcfifo_component|              ; 193 (0)     ; 147 (0)                   ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 46 (0)       ; 78 (0)            ; 69 (0)           ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component                                                                              ; work         ;
;          |dcfifo_o1l1:auto_generated|        ; 193 (60)    ; 147 (57)                  ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 46 (2)       ; 78 (37)           ; 69 (5)           ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated                                                   ; work         ;
;             |a_graycounter_4lc:wrptr_g1p|    ; 34 (34)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 1 (1)             ; 18 (18)          ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p                       ; work         ;
;             |a_graycounter_877:rdptr_g1p|    ; 31 (31)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 1 (1)             ; 20 (20)          ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p                       ; work         ;
;             |alt_synch_pipe_tld:rs_dgwp|     ; 26 (0)      ; 26 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (0)            ; 7 (0)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp                        ; work         ;
;                |dffpipe_se9:dffpipe12|       ; 26 (26)     ; 26 (26)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (19)           ; 7 (7)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12  ; work         ;
;             |alt_synch_pipe_uld:ws_dgrp|     ; 26 (0)      ; 26 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 20 (0)            ; 6 (0)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp                        ; work         ;
;                |dffpipe_te9:dffpipe15|       ; 26 (26)     ; 26 (26)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 20 (20)           ; 6 (6)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15  ; work         ;
;             |altsyncram_om31:fifo_ram|       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram                          ; work         ;
;             |cmpr_c66:rdempty_eq_comp1_msb|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|cmpr_c66:rdempty_eq_comp1_msb                     ; work         ;
;             |cmpr_q76:rdfull_eq_comp|        ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|cmpr_q76:rdfull_eq_comp                           ; work         ;
;             |mux_j28:rdemp_eq_comp_lsb_mux|  ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 4 (4)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux                     ; work         ;
;             |mux_j28:rdemp_eq_comp_msb_mux|  ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 4 (4)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux                     ; work         ;
;             |mux_j28:wrfull_eq_comp_lsb_mux| ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 8 (8)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux                    ; work         ;
;             |mux_j28:wrfull_eq_comp_msb_mux| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 3 (3)            ; |ACync_block|FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux                    ; work         ;
;    |FifoD:FifoDigital|                       ; 252 (0)     ; 183 (0)                   ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 69 (0)       ; 90 (0)            ; 93 (0)           ; |ACync_block|FifoD:FifoDigital                                                                                                     ; work         ;
;       |dcfifo:dcfifo_component|              ; 252 (0)     ; 183 (0)                   ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 69 (0)       ; 90 (0)            ; 93 (0)           ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component                                                                             ; work         ;
;          |dcfifo_h0l1:auto_generated|        ; 252 (71)    ; 183 (69)                  ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 69 (2)       ; 90 (43)           ; 93 (3)           ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated                                                  ; work         ;
;             |a_graycounter_7lc:wrptr_g1p|    ; 39 (39)     ; 21 (21)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 17 (17)      ; 0 (0)             ; 22 (22)          ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p                      ; work         ;
;             |a_graycounter_b77:rdptr_g1p|    ; 37 (37)     ; 23 (23)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 11 (11)      ; 1 (1)             ; 25 (25)          ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p                      ; work         ;
;             |alt_synch_pipe_0md:rs_dgwp|     ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (0)            ; 13 (0)           ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp                       ; work         ;
;                |dffpipe_ve9:dffpipe14|       ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (19)           ; 13 (13)          ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14 ; work         ;
;             |alt_synch_pipe_1md:ws_dgrp|     ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 24 (0)            ; 8 (0)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp                       ; work         ;
;                |dffpipe_0f9:dffpipe17|       ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 24 (24)           ; 8 (8)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17 ; work         ;
;             |altsyncram_qj31:fifo_ram|       ; 30 (6)      ; 6 (6)                     ; 0 (0)         ; 262144      ; 32   ; 0            ; 0       ; 0         ; 0    ; 0            ; 21 (0)       ; 3 (3)             ; 6 (3)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram                         ; work         ;
;                |decode_d87:decode12|         ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 3 (3)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12     ; work         ;
;                |mux_t28:mux13|               ; 16 (16)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 0 (0)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|mux_t28:mux13           ; work         ;
;             |cmpr_e66:rdempty_eq_comp_lsb|   ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_e66:rdempty_eq_comp_lsb                     ; work         ;
;             |cmpr_e66:rdempty_eq_comp_msb|   ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_e66:rdempty_eq_comp_msb                     ; work         ;
;             |cmpr_t76:rdfull_eq_comp|        ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 8 (8)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp                          ; work         ;
;             |mux_j28:rdemp_eq_comp_lsb_mux|  ; 11 (11)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 8 (8)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux                    ; work         ;
;             |mux_j28:rdemp_eq_comp_msb_mux|  ; 11 (11)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 7 (7)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux                    ; work         ;
;             |mux_j28:wrfull_eq_comp_lsb_mux| ; 11 (11)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 8 (8)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux                   ; work         ;
;             |mux_j28:wrfull_eq_comp_msb_mux| ; 11 (11)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 5 (5)            ; |ACync_block|FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux                   ; work         ;
;    |altpll0:60MHz|                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ACync_block|altpll0:60MHz                                                                                                         ; work         ;
;       |altpll:altpll_component|              ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ACync_block|altpll0:60MHz|altpll:altpll_component                                                                                 ; work         ;
;          |altpll0_altpll:auto_generated|     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ACync_block|altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated                                                   ; work         ;
;    |uberACync:Sink|                          ; 521 (521)   ; 273 (273)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 248 (248)    ; 60 (60)           ; 213 (213)        ; |ACync_block|uberACync:Sink                                                                                                        ; work         ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                          ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+
; Name         ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+
; Prbs         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; AdcClk       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacLoad      ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; PotClk       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; PotStart     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Led          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacWr        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; AdcConvert   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacAddr[3]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacAddr[2]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacAddr[1]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacAddr[0]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[15]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[14]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[13]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[12]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[11]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[10]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[9]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[8]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[7]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[6]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[5]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[4]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[3]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[2]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[1]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DacDat[0]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[7]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[6]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[5]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[4]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[3]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[2]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[1]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; DigOut[0]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; ExtendOut[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; ExtendOut[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; Clk100       ; Input    ; --            ; --            ; --                    ; --  ; --   ;
; ExtendIn[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; ExtendIn[1]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; Master       ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; Adc1         ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; Adc4         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; Adc3         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; Adc2         ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[7]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[6]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[5]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[4]     ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; DigIn[3]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[2]     ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; DigIn[1]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; DigIn[0]     ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; AC60Hz       ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; PotDat       ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+--------------+----------+---------------+---------------+-----------------------+-----+------+


+---------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                            ;
+---------------------------------------------+-------------------+---------+
; Source Pin / Fanout                         ; Pad To Core Index ; Setting ;
+---------------------------------------------+-------------------+---------+
; Clk100                                      ;                   ;         ;
; ExtendIn[0]                                 ;                   ;         ;
; ExtendIn[1]                                 ;                   ;         ;
; Master                                      ;                   ;         ;
; Adc1                                        ;                   ;         ;
;      - uberACync:Sink|FifoOutAna[14]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[13]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[12]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[11]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[10]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[9]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[8]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[7]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[6]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[5]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[4]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[3]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[2]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[1]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[0]         ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[15]~feeder ; 0                 ; 6       ;
; Adc4                                        ;                   ;         ;
; Adc3                                        ;                   ;         ;
; Adc2                                        ;                   ;         ;
;      - uberACync:Sink|FifoOutAna[31]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[30]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[25]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[21]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[16]        ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[28]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[17]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[19]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[22]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[27]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[18]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[29]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[26]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[24]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[23]~feeder ; 0                 ; 6       ;
;      - uberACync:Sink|FifoOutAna[20]~feeder ; 0                 ; 6       ;
; DigIn[7]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[7]~feeder    ; 0                 ; 6       ;
; DigIn[6]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[6]           ; 0                 ; 6       ;
; DigIn[5]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[5]~feeder    ; 0                 ; 6       ;
; DigIn[4]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[4]~feeder    ; 1                 ; 6       ;
; DigIn[3]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[3]~feeder    ; 0                 ; 6       ;
; DigIn[2]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[2]~feeder    ; 1                 ; 6       ;
; DigIn[1]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[1]           ; 0                 ; 6       ;
; DigIn[0]                                    ;                   ;         ;
;      - uberACync:Sink|DigInBuf[0]~feeder    ; 0                 ; 6       ;
; AC60Hz                                      ;                   ;         ;
; PotDat                                      ;                   ;         ;
+---------------------------------------------+-------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                                                                                                             ;
+----------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; Name                                                                                                                             ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+----------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; Clk100                                                                                                                           ; PIN_23             ; 1       ; Clock                      ; no     ; --                   ; --               ; --                        ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_NEW_REG20_RTM022                                 ; LCCOMB_X17_Y20_N22 ; 49      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|valid_wrreq                                                  ; LCCOMB_X17_Y22_N30 ; 57      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode651w[2] ; LCCOMB_X29_Y25_N0  ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode664w[2] ; LCCOMB_X29_Y25_N20 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode672w[2] ; LCCOMB_X29_Y25_N24 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode680w[2] ; LCCOMB_X29_Y25_N2  ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_NEW_REG16_RTM018                                ; LCCOMB_X31_Y26_N20 ; 56      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|valid_wrreq                                                 ; LCCOMB_X29_Y25_N8  ; 28      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0]                                             ; PLL_1              ; 273     ; Clock                      ; yes    ; Global Clock         ; GCLK3            ; --                        ;
; uberACync:Sink|CtrAna[4]~20                                                                                                      ; LCCOMB_X26_Y15_N28 ; 9       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|CtrDig[8]~18                                                                                                      ; LCCOMB_X25_Y24_N26 ; 9       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|DacAddr[2]~4                                                                                                      ; LCCOMB_X23_Y18_N6  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|DacDat[10]~3                                                                                                      ; LCCOMB_X23_Y18_N8  ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|DelayTimer[4]~64                                                                                                  ; LCCOMB_X28_Y32_N6  ; 21      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|DigOut[3]~1                                                                                                       ; LCCOMB_X26_Y24_N12 ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|Equal5~4                                                                                                          ; LCCOMB_X31_Y31_N4  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoAnaRdClk                                                                                                      ; FF_X27_Y15_N25     ; 107     ; Clock                      ; yes    ; Global Clock         ; GCLK18           ; --                        ;
; uberACync:Sink|FifoAnaWrClk                                                                                                      ; FF_X29_Y22_N17     ; 104     ; Clock                      ; yes    ; Global Clock         ; GCLK12           ; --                        ;
; uberACync:Sink|FifoDigRdClk                                                                                                      ; FF_X26_Y24_N31     ; 128     ; Clock                      ; yes    ; Global Clock         ; GCLK15           ; --                        ;
; uberACync:Sink|FifoDigWrClk                                                                                                      ; FF_X26_Y32_N13     ; 119     ; Clock                      ; yes    ; Global Clock         ; GCLK13           ; --                        ;
; uberACync:Sink|FifoOutAna[12]~18                                                                                                 ; LCCOMB_X26_Y13_N30 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[13]~16                                                                                                 ; LCCOMB_X28_Y12_N24 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[14]~15                                                                                                 ; LCCOMB_X28_Y12_N30 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[15]~13                                                                                                 ; LCCOMB_X28_Y12_N0  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[26]~20                                                                                                 ; LCCOMB_X28_Y12_N14 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[2]~28                                                                                                  ; LCCOMB_X28_Y12_N22 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[35]~34                                                                                                 ; LCCOMB_X25_Y12_N6  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[39]~25                                                                                                 ; LCCOMB_X28_Y12_N16 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[48]~31                                                                                                 ; LCCOMB_X25_Y12_N16 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[49]~29                                                                                                 ; LCCOMB_X25_Y12_N4  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[4]~27                                                                                                  ; LCCOMB_X28_Y12_N28 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[53]~26                                                                                                 ; LCCOMB_X28_Y12_N26 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[54]~33                                                                                                 ; LCCOMB_X25_Y12_N12 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[56]~23                                                                                                 ; LCCOMB_X25_Y12_N18 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[59]~19                                                                                                 ; LCCOMB_X28_Y12_N12 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifoOutAna[9]~32                                                                                                  ; LCCOMB_X25_Y12_N2  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifosClear                                                                                                        ; FF_X25_Y33_N7      ; 4       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|FifosClear                                                                                                        ; FF_X25_Y33_N7      ; 390     ; Async. clear               ; yes    ; Global Clock         ; GCLK11           ; --                        ;
; uberACync:Sink|LessThan2~3                                                                                                       ; LCCOMB_X44_Y32_N2  ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|PhaseDelayTime[8]~4                                                                                               ; LCCOMB_X30_Y31_N4  ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|PrbsShift[0]~1                                                                                                    ; LCCOMB_X44_Y32_N12 ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|RetriggerInhibit[2]~23                                                                                            ; LCCOMB_X27_Y32_N30 ; 21      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateMode.000                                                                                                     ; FF_X26_Y32_N9      ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateMode.110                                                                                                     ; FF_X25_Y33_N17     ; 41      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateZero.00                                                                                                      ; FF_X26_Y32_N11     ; 25      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|StateZero.01                                                                                                      ; FF_X26_Y32_N5      ; 27      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; uberACync:Sink|WideOr10                                                                                                          ; LCCOMB_X26_Y32_N18 ; 11      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+----------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                                                                                                  ;
+--------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name                                                                                 ; Location       ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1          ; 273     ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
; uberACync:Sink|FifoAnaRdClk                                                          ; FF_X27_Y15_N25 ; 107     ; 0                                    ; Global Clock         ; GCLK18           ; --                        ;
; uberACync:Sink|FifoAnaWrClk                                                          ; FF_X29_Y22_N17 ; 104     ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
; uberACync:Sink|FifoDigRdClk                                                          ; FF_X26_Y24_N31 ; 128     ; 0                                    ; Global Clock         ; GCLK15           ; --                        ;
; uberACync:Sink|FifoDigWrClk                                                          ; FF_X26_Y32_N13 ; 119     ; 0                                    ; Global Clock         ; GCLK13           ; --                        ;
; uberACync:Sink|FifosClear                                                            ; FF_X25_Y33_N7  ; 390     ; 0                                    ; Global Clock         ; GCLK11           ; --                        ;
+--------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                                                                                            ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Name                                                                                                                                             ; Fan-Out ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|valid_wrreq                                                                  ; 89      ;
; uberACync:Sink|DacDat[10]~1                                                                                                                      ; 64      ;
; uberACync:Sink|CtrAna[3]                                                                                                                         ; 60      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_NEW_REG16_RTM018                                                ; 56      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_NEW_REG20_RTM022                                                 ; 49      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                                       ; 42      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                                      ; 41      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                                      ; 41      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                                       ; 41      ;
; uberACync:Sink|StateMode.110                                                                                                                     ; 41      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                                      ; 40      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                                      ; 40      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                                      ; 40      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                                       ; 40      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                                       ; 40      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                                       ; 40      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                                     ; 39      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                                      ; 39      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                                      ; 39      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                                      ; 39      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                                       ; 39      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                                       ; 39      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                                     ; 38      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                                     ; 38      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                                      ; 38      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                                       ; 38      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                                       ; 38      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                                      ; 37      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                                 ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                                 ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                                 ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[6]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                                  ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                                  ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[10]                                                                  ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[8]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[6]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[5]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[4]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[2]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[1]                                                                   ; 34      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                                   ; 34      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty~_wirecell                                                       ; 32      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0~_wirecell                            ; 32      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty~_wirecell                                                        ; 32      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0~_wirecell                             ; 32      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|ram_address_b[11]                                                            ; 32      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|ram_address_a[11]                                                            ; 32      ;
; uberACync:Sink|CtrAna[0]                                                                                                                         ; 29      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|valid_wrreq                                                                 ; 28      ;
; uberACync:Sink|StateZero.01                                                                                                                      ; 27      ;
; uberACync:Sink|CtrAna[1]                                                                                                                         ; 27      ;
; uberACync:Sink|StateMode.000                                                                                                                     ; 26      ;
; uberACync:Sink|CtrAna[2]                                                                                                                         ; 26      ;
; uberACync:Sink|StateZero.00                                                                                                                      ; 25      ;
; uberACync:Sink|StateMode.100                                                                                                                     ; 22      ;
; uberACync:Sink|CtrAna[4]                                                                                                                         ; 22      ;
; uberACync:Sink|RetriggerInhibit[2]~23                                                                                                            ; 21      ;
; uberACync:Sink|DelayTimer[4]~64                                                                                                                  ; 21      ;
; uberACync:Sink|CtrPot[3]                                                                                                                         ; 20      ;
; uberACync:Sink|CtrPot[0]                                                                                                                         ; 20      ;
; uberACync:Sink|CtrPot[7]                                                                                                                         ; 20      ;
; uberACync:Sink|Equal5~4                                                                                                                          ; 19      ;
; uberACync:Sink|CtrPot[1]                                                                                                                         ; 19      ;
; uberACync:Sink|CtrPot[4]                                                                                                                         ; 19      ;
; uberACync:Sink|CtrPot[2]                                                                                                                         ; 18      ;
; uberACync:Sink|CtrAna[5]                                                                                                                         ; 18      ;
; ~GND                                                                                                                                             ; 17      ;
; Adc2~input                                                                                                                                       ; 16      ;
; Adc3~input                                                                                                                                       ; 16      ;
; Adc4~input                                                                                                                                       ; 16      ;
; Adc1~input                                                                                                                                       ; 16      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode680w[2]                 ; 16      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode651w[2]                 ; 16      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode672w[2]                 ; 16      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode664w[2]                 ; 16      ;
; uberACync:Sink|DacDat[10]~3                                                                                                                      ; 16      ;
; uberACync:Sink|LessThan2~3                                                                                                                       ; 16      ;
; uberACync:Sink|PrbsShift[0]~1                                                                                                                    ; 16      ;
; uberACync:Sink|CtrAna[6]                                                                                                                         ; 15      ;
; uberACync:Sink|PhaseDelayTime[8]~4                                                                                                               ; 12      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1]                               ; 12      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0]                               ; 12      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                                          ; 11      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                                         ; 11      ;
; uberACync:Sink|WideOr10                                                                                                                          ; 11      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                                      ; 11      ;
; uberACync:Sink|StateMode.011                                                                                                                     ; 11      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                                      ; 10      ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                                      ; 10      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                                       ; 10      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                                       ; 10      ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                                       ; 10      ;
; uberACync:Sink|CtrPot[5]                                                                                                                         ; 10      ;
; uberACync:Sink|CtrPot[6]                                                                                                                         ; 10      ;
; uberACync:Sink|StateMode.010                                                                                                                     ; 10      ;
; PotDat~input                                                                                                                                     ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                                      ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                                      ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                                      ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                                      ; 9       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                                       ; 9       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                                       ; 9       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                                       ; 9       ;
; uberACync:Sink|CtrDig[8]~18                                                                                                                      ; 9       ;
; uberACync:Sink|CtrAna[4]~20                                                                                                                      ; 9       ;
; uberACync:Sink|AdcClk                                                                                                                            ; 9       ;
; uberACync:Sink|CtrDig[1]                                                                                                                         ; 9       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                                     ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                                      ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                                      ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                                      ; 8       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                                       ; 8       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                                       ; 8       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                                       ; 8       ;
; uberACync:Sink|DigOut[3]~1                                                                                                                       ; 8       ;
; uberACync:Sink|CtrDig[2]                                                                                                                         ; 8       ;
; uberACync:Sink|CtrDig[0]                                                                                                                         ; 8       ;
; uberACync:Sink|CtrAna[8]                                                                                                                         ; 8       ;
; uberACync:Sink|CtrAna[7]                                                                                                                         ; 8       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                                         ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                                     ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                                     ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                                      ; 7       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                                          ; 7       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                                       ; 7       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                                       ; 7       ;
; uberACync:Sink|FifoOutAna[9]~21                                                                                                                  ; 7       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15~0                                   ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14~0                                   ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                                         ; 6       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                                          ; 6       ;
; uberACync:Sink|PreloadDig[0]                                                                                                                     ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                                     ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                                     ; 6       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                                      ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                                  ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp|aneb_result_wire[0]~9                               ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp|aneb_result_wire[0]~4                               ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                                  ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                                 ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[15]                                                                 ; 6       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[13]                                                                 ; 6       ;
; uberACync:Sink|FifoOutAna[9]~22                                                                                                                  ; 6       ;
; uberACync:Sink|Selector83~2                                                                                                                      ; 6       ;
; uberACync:Sink|ExtendInBuf[1]                                                                                                                    ; 6       ;
; uberACync:Sink|ExtendInBuf[0]                                                                                                                    ; 6       ;
; uberACync:Sink|WideOr35~0                                                                                                                        ; 6       ;
; uberACync:Sink|PotClk                                                                                                                            ; 6       ;
; uberACync:Sink|PotBuf[9]                                                                                                                         ; 5       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1                                             ; 5       ;
; uberACync:Sink|PreloadDig[1]                                                                                                                     ; 5       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11~0                                    ; 5       ;
; uberACync:Sink|AcLineBuf                                                                                                                         ; 5       ;
; uberACync:Sink|DigInBuf[0]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[1]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[2]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[3]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[4]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[5]                                                                                                                       ; 5       ;
; uberACync:Sink|DigInBuf[6]                                                                                                                       ; 5       ;
; uberACync:Sink|Decoder0~1                                                                                                                        ; 5       ;
; uberACync:Sink|DigInBuf[7]                                                                                                                       ; 5       ;
; uberACync:Sink|PotBuf[6]~0                                                                                                                       ; 5       ;
; uberACync:Sink|CtrPrbs[12]                                                                                                                       ; 5       ;
; uberACync:Sink|FifoOutAna[35]~34                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[54]~33                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[9]~32                                                                                                                  ; 4       ;
; uberACync:Sink|DacAddr[2]~4                                                                                                                      ; 4       ;
; uberACync:Sink|PhaseDelayTime[8]~5                                                                                                               ; 4       ;
; uberACync:Sink|Selector239~1                                                                                                                     ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~2                                             ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2                                              ; 4       ;
; uberACync:Sink|Selector46~1                                                                                                                      ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~7                                             ; 4       ;
; uberACync:Sink|PreloadDig[2]                                                                                                                     ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                                     ; 4       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                                     ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12~0                                    ; 4       ;
; uberACync:Sink|PreloadAna[1]                                                                                                                     ; 4       ;
; uberACync:Sink|PreloadAna[0]                                                                                                                     ; 4       ;
; uberACync:Sink|PreloadAna[2]                                                                                                                     ; 4       ;
; uberACync:Sink|Selector136~0                                                                                                                     ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                                      ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                                      ; 4       ;
; uberACync:Sink|StateZero.10                                                                                                                      ; 4       ;
; uberACync:Sink|FifoOutAna[48]~31                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[49]~29                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[2]~28                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[4]~27                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[53]~26                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[39]~25                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[9]~24                                                                                                                  ; 4       ;
; uberACync:Sink|FifoOutAna[56]~23                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[26]~20                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[59]~19                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[12]~18                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[13]~16                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[14]~15                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[14]~14                                                                                                                 ; 4       ;
; uberACync:Sink|FifoOutAna[15]~13                                                                                                                 ; 4       ;
; uberACync:Sink|MasterBuf                                                                                                                         ; 4       ;
; uberACync:Sink|StateMode.101                                                                                                                     ; 4       ;
; uberACync:Sink|PotStart~0                                                                                                                        ; 4       ;
; uberACync:Sink|Selector82~0                                                                                                                      ; 4       ;
; uberACync:Sink|Selector104~18                                                                                                                    ; 4       ;
; uberACync:Sink|AdcConvert                                                                                                                        ; 4       ;
; uberACync:Sink|DacWr                                                                                                                             ; 4       ;
; uberACync:Sink|DelayTimer[0]                                                                                                                     ; 4       ;
; uberACync:Sink|CtrPrbs[11]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[13]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[10]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[9]                                                                                                                        ; 4       ;
; uberACync:Sink|CtrPrbs[6]                                                                                                                        ; 4       ;
; uberACync:Sink|CtrPrbs[5]                                                                                                                        ; 4       ;
; uberACync:Sink|CtrPrbs[15]                                                                                                                       ; 4       ;
; uberACync:Sink|CtrPrbs[14]                                                                                                                       ; 4       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13                              ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9                               ; 3       ;
; uberACync:Sink|PotBuf[0]~13                                                                                                                      ; 3       ;
; uberACync:Sink|PotBuf[1]~10                                                                                                                      ; 3       ;
; uberACync:Sink|Selector239~0                                                                                                                     ; 3       ;
; uberACync:Sink|PotBuf[8]                                                                                                                         ; 3       ;
; uberACync:Sink|PotBuf[7]                                                                                                                         ; 3       ;
; uberACync:Sink|PotBuf[11]                                                                                                                        ; 3       ;
; uberACync:Sink|PotBuf[10]                                                                                                                        ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~4                                             ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~0                                              ; 3       ;
; uberACync:Sink|Selector46~3                                                                                                                      ; 3       ;
; uberACync:Sink|StateZero.11                                                                                                                      ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~9                                             ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5                                             ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15]                ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14]                ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~7                                              ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~1                                              ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11]                 ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12]                 ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10]                 ; 3       ;
; uberACync:Sink|Selector46~0                                                                                                                      ; 3       ;
; uberACync:Sink|DelayTimer[4]~27                                                                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                                       ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                                       ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                                  ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                                 ; 3       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                                 ; 3       ;
; uberACync:Sink|Selector83~1                                                                                                                      ; 3       ;
; uberACync:Sink|FifoOutAna[14]~12                                                                                                                 ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                                  ; 3       ;
; uberACync:Sink|FifosClear                                                                                                                        ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|cmpr_q76:rdfull_eq_comp|aneb_result_wire[0]~7                                ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|cmpr_q76:rdfull_eq_comp|aneb_result_wire[0]~4                                ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                                   ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                                  ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                                   ; 3       ;
; uberACync:Sink|Selector56~3                                                                                                                      ; 3       ;
; uberACync:Sink|AtZeroCrossing                                                                                                                    ; 3       ;
; uberACync:Sink|WideOr35~1                                                                                                                        ; 3       ;
; uberACync:Sink|CtrDig[8]~9                                                                                                                       ; 3       ;
; uberACync:Sink|StateMode.001                                                                                                                     ; 3       ;
; uberACync:Sink|Selector159~0                                                                                                                     ; 3       ;
; uberACync:Sink|Selector158~0                                                                                                                     ; 3       ;
; uberACync:Sink|Selector83~0                                                                                                                      ; 3       ;
; uberACync:Sink|Selector240~8                                                                                                                     ; 3       ;
; uberACync:Sink|PotClk~9                                                                                                                          ; 3       ;
; uberACync:Sink|PotClk~4                                                                                                                          ; 3       ;
; uberACync:Sink|Clk3662Hz[0]                                                                                                                      ; 3       ;
; uberACync:Sink|DacDat[10]~0                                                                                                                      ; 3       ;
; uberACync:Sink|DacLoad                                                                                                                           ; 3       ;
; uberACync:Sink|RetriggerInhibit[20]                                                                                                              ; 3       ;
; uberACync:Sink|CtrDig[5]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[4]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[8]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[7]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[6]                                                                                                                         ; 3       ;
; uberACync:Sink|CtrDig[3]                                                                                                                         ; 3       ;
; uberACync:Sink|Add16~0                                                                                                                           ; 3       ;
; uberACync:Sink|CtrPrbs[7]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[2]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[1]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[0]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[3]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[4]                                                                                                                        ; 3       ;
; uberACync:Sink|CtrPrbs[8]                                                                                                                        ; 3       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15                              ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5                              ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3                              ; 2       ;
; uberACync:Sink|Selector104~6                                                                                                                     ; 2       ;
; uberACync:Sink|PotBuf[2]~26                                                                                                                      ; 2       ;
; uberACync:Sink|PotBuf[5]~15                                                                                                                      ; 2       ;
; uberACync:Sink|PotBuf[7]~7                                                                                                                       ; 2       ;
; uberACync:Sink|PotBuf[10]~2                                                                                                                      ; 2       ;
; uberACync:Sink|PotBuf[2]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[1]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[6]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[5]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[4]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[3]                                                                                                                         ; 2       ;
; uberACync:Sink|PotBuf[0]                                                                                                                         ; 2       ;
; uberACync:Sink|PhaseDelayTime[8]~3                                                                                                               ; 2       ;
; uberACync:Sink|PhaseDelayTime[8]~2                                                                                                               ; 2       ;
; uberACync:Sink|PreloadDig~0                                                                                                                      ; 2       ;
; uberACync:Sink|Decoder0~2                                                                                                                        ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|cntr_cout[13]~0                                 ; 2       ;
; uberACync:Sink|PreloadAna[0]~1                                                                                                                   ; 2       ;
; uberACync:Sink|Decoder1~1                                                                                                                        ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~6                                              ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~1                                              ; 2       ;
; uberACync:Sink|Selector46~2                                                                                                                      ; 2       ;
; uberACync:Sink|WideOr1~5                                                                                                                         ; 2       ;
; uberACync:Sink|WideOr1~4                                                                                                                         ; 2       ;
; uberACync:Sink|Selector44~0                                                                                                                      ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~2                                             ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~1                                             ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10                             ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~10                             ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15]                ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]                 ; 2       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]                 ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5                                              ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~3                                              ; 2       ;
; uberACync:Sink|Selector226~0                                                                                                                     ; 2       ;
; uberACync:Sink|PreloadAna[0]~0                                                                                                                   ; 2       ;
; uberACync:Sink|Selector135~0                                                                                                                     ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7                               ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~9                               ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10]                 ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11]                 ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12]                 ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]                  ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]                  ; 2       ;
; uberACync:Sink|FifoDigWrClk                                                                                                                      ; 2       ;
; uberACync:Sink|Decoder1~0                                                                                                                        ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_msb_aeb                                                        ; 2       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                                        ; 2       ;
; uberACync:Sink|Selector56~2                                                                                                                      ; 2       ;
; uberACync:Sink|Selector56~1                                                                                                                      ; 2       ;
; uberACync:Sink|Selector56~0                                                                                                                      ; 2       ;
; uberACync:Sink|Selector51~0                                                                                                                      ; 2       ;
; uberACync:Sink|FifoOutAna[16]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[32]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[48]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[0]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[17]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[33]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[49]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[1]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[18]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[34]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[50]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[2]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[19]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[35]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[51]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[3]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[20]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[36]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[52]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[4]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[21]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[37]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[53]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[5]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[22]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[38]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[54]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[6]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[23]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[39]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[55]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[7]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[24]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[40]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[56]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[8]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[25]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[41]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[57]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[9]                                                                                                                     ; 2       ;
; uberACync:Sink|FifoOutAna[26]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[42]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[58]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[10]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[27]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[43]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[59]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[11]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[28]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[44]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[60]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[12]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[29]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[45]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[61]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[13]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[30]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[46]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[62]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[14]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[31]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[47]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[63]                                                                                                                    ; 2       ;
; uberACync:Sink|FifoOutAna[15]                                                                                                                    ; 2       ;
; uberACync:Sink|DacAddr[2]~2                                                                                                                      ; 2       ;
; uberACync:Sink|PotClk~7                                                                                                                          ; 2       ;
; uberACync:Sink|LessThan2~0                                                                                                                       ; 2       ;
; uberACync:Sink|PrbsShift[10]                                                                                                                     ; 2       ;
; uberACync:Sink|ExtendOut[0]                                                                                                                      ; 2       ;
; uberACync:Sink|ExtendOut[1]                                                                                                                      ; 2       ;
; uberACync:Sink|PotStart                                                                                                                          ; 2       ;
; uberACync:Sink|RetriggerInhibit[19]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[18]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[17]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[16]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[15]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[14]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[13]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[12]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[11]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[10]                                                                                                              ; 2       ;
; uberACync:Sink|RetriggerInhibit[9]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[8]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[7]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[6]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[5]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[4]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[3]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[2]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[1]                                                                                                               ; 2       ;
; uberACync:Sink|RetriggerInhibit[0]                                                                                                               ; 2       ;
; uberACync:Sink|DelayTimer[10]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[9]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[16]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[15]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[14]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[13]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[12]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[11]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[8]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[7]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[6]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[5]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[4]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[3]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[2]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[1]                                                                                                                     ; 2       ;
; uberACync:Sink|DelayTimer[20]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[19]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[18]                                                                                                                    ; 2       ;
; uberACync:Sink|DelayTimer[17]                                                                                                                    ; 2       ;
; uberACync:Sink|Clk3662Hz[13]                                                                                                                     ; 2       ;
; uberACync:Sink|Clk3662Hz[12]                                                                                                                     ; 2       ;
; uberACync:Sink|Clk3662Hz[11]                                                                                                                     ; 2       ;
; uberACync:Sink|Clk3662Hz[10]                                                                                                                     ; 2       ;
; uberACync:Sink|Clk3662Hz[9]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[8]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[7]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[6]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[5]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[4]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[3]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[2]                                                                                                                      ; 2       ;
; uberACync:Sink|Clk3662Hz[1]                                                                                                                      ; 2       ;
; uberACync:Sink|PrbsShift[0]                                                                                                                      ; 2       ;
; uberACync:Sink|StateMode.000~feeder                                                                                                              ; 1       ;
; AC60Hz~input                                                                                                                                     ; 1       ;
; DigIn[0]~input                                                                                                                                   ; 1       ;
; DigIn[1]~input                                                                                                                                   ; 1       ;
; DigIn[2]~input                                                                                                                                   ; 1       ;
; DigIn[3]~input                                                                                                                                   ; 1       ;
; DigIn[4]~input                                                                                                                                   ; 1       ;
; DigIn[5]~input                                                                                                                                   ; 1       ;
; DigIn[6]~input                                                                                                                                   ; 1       ;
; DigIn[7]~input                                                                                                                                   ; 1       ;
; Master~input                                                                                                                                     ; 1       ;
; ExtendIn[1]~input                                                                                                                                ; 1       ;
; ExtendIn[0]~input                                                                                                                                ; 1       ;
; Clk100~input                                                                                                                                     ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9~0_RESYN239_BDD240                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0_RESYN237_BDD238                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0_RESYN235_BDD236                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12~0_RESYN233_BDD234                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|cntr_cout[13]~0_RESYN231_BDD232                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13~0_RESYN229_BDD230                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~2_RESYN227_BDD228                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1_RESYN225_BDD226                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~1_RESYN223_BDD224                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10~0_RESYN221_BDD222                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9~0_RESYN219_BDD220                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12~0_RESYN217_BDD218                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11~0_RESYN215_BDD216                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~6_RESYN213_BDD214                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6~0_RESYN211_BDD212                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2_RESYN209_BDD210                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~2_RESYN207_BDD208                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~0_RESYN205_BDD206                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~7_RESYN203_BDD204                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5_RESYN201_BDD202                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~7_RESYN199_BDD200                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5_RESYN197_BDD198                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~5_RESYN195_BDD196               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~7_RESYN193_BDD194              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~7_RESYN191_BDD192              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~7_RESYN189_BDD190              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~7_RESYN187_BDD188              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~7_RESYN185_BDD186              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~7_RESYN183_BDD184              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode680w[2]_RESYN181_BDD182 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode651w[2]_RESYN179_BDD180 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode672w[2]_RESYN177_BDD178 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12|w_anode664w[2]_RESYN175_BDD176 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8~0_RESYN173_BDD174                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11~0_RESYN171_BDD172                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5~0_RESYN169_BDD170                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8~0_RESYN167_BDD168                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5~0_RESYN165_BDD166                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2~0_RESYN163_BDD164                     ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~5_RESYN161_BDD162                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN159_BDD160             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN157_BDD158             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN155_BDD156             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~10_RESYN153_BDD154             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~10_RESYN151_BDD152             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~10_RESYN149_BDD150             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~10_RESYN147_BDD148             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~10_RESYN145_BDD146             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~5_RESYN143_BDD144                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~3_RESYN141_BDD142               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~3_RESYN139_BDD140               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~3_RESYN137_BDD138               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN135_BDD136              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN133_BDD134              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN131_BDD132              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN129_BDD130              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9_RESYN127_BDD128              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6_OTERM34                                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0_OTERM31                               ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6_OTERM28                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0_OTERM25                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_RTM023                                                           ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_RTM019                                                          ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1                              ; 1       ;
; uberACync:Sink|Led~3_wirecell                                                                                                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]~0                                                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]~0                                                                ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]~0                                                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]~0                                                                 ; 1       ;
; uberACync:Sink|Clk3662Hz[0]~39                                                                                                                   ; 1       ;
; uberACync:Sink|CtrPot[0]~0                                                                                                                       ; 1       ;
; uberACync:Sink|Selector104~31                                                                                                                    ; 1       ;
; uberACync:Sink|Selector104~30                                                                                                                    ; 1       ;
; uberACync:Sink|Selector104~29                                                                                                                    ; 1       ;
; uberACync:Sink|Selector104~28                                                                                                                    ; 1       ;
; uberACync:Sink|Selector240~10                                                                                                                    ; 1       ;
; uberACync:Sink|Selector240~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector104~9                                                                                                                     ; 1       ;
; uberACync:Sink|Selector104~5                                                                                                                     ; 1       ;
; uberACync:Sink|PotClk~13                                                                                                                         ; 1       ;
; uberACync:Sink|Selector104~27                                                                                                                    ; 1       ;
; uberACync:Sink|PrbsShift~16                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~15                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[1]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~14                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[2]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~13                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[3]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~12                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[4]                                                                                                                      ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~14                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~13                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~12                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~11                                            ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~12                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~11                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~10                                             ; 1       ;
; uberACync:Sink|PotBuf[2]~44                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[2]~43                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[1]~42                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[1]~41                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[1]~40                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~39                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~38                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~37                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~36                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[8]~35                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~34                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~33                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~32                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~31                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[7]~30                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~29                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~28                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~27                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[6]~25                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[5]~24                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[5]~23                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[4]~22                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[4]~21                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[4]~20                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[4]~19                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[3]~18                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[3]~17                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[3]~16                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[0]~14                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[0]~12                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[0]~11                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[11]~9                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[11]~8                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[10]~6                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[10]~5                                                                                                                      ; 1       ;
; uberACync:Sink|PotBuf[9]~4                                                                                                                       ; 1       ;
; uberACync:Sink|PotBuf[9]~3                                                                                                                       ; 1       ;
; uberACync:Sink|PotBuf[10]~1                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~11                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift[5]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~10                                                                                                                      ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~15                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~14                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~13                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~12                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                                          ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                                         ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~10                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                                ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~12                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~11                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~10                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                                          ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                                           ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                                          ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                                          ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~9                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                                 ; 1       ;
; uberACync:Sink|WideOr1                                                                                                                           ; 1       ;
; uberACync:Sink|Selector46~5                                                                                                                      ; 1       ;
; uberACync:Sink|Selector46~4                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~9                                                                                                                       ; 1       ;
; uberACync:Sink|PrbsShift[6]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~8                                                                                                                       ; 1       ;
; uberACync:Sink|PrbsShift[11]                                                                                                                     ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~11                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~10                                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[2]                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                                 ; 1       ;
; uberACync:Sink|Selector80~1                                                                                                                      ; 1       ;
; uberACync:Sink|Selector80~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector81~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector79~1                                                                                                                      ; 1       ;
; uberACync:Sink|Selector79~0                                                                                                                      ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14]                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|cntr_cout[13]~0                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~7                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~6                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|_~0                                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~9                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                                  ; 1       ;
; uberACync:Sink|Selector226~2                                                                                                                     ; 1       ;
; uberACync:Sink|Selector226~1                                                                                                                     ; 1       ;
; uberACync:Sink|PreloadAna[0]~3                                                                                                                   ; 1       ;
; uberACync:Sink|PreloadAna[2]~2                                                                                                                   ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10~0                                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12~0                                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11~0                                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10]                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|_~5                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]                  ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]                  ; 1       ;
; uberACync:Sink|Selector43~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector45~0                                                                                                                      ; 1       ;
; uberACync:Sink|PhaseDelayTime[10]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[9]                                                                                                                 ; 1       ;
; uberACync:Sink|PhaseDelayTime[16]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[15]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[14]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[13]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[12]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[11]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[8]                                                                                                                 ; 1       ;
; uberACync:Sink|PhaseDelayTime[19]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[18]                                                                                                                ; 1       ;
; uberACync:Sink|PhaseDelayTime[17]                                                                                                                ; 1       ;
; uberACync:Sink|Selector44~1                                                                                                                      ; 1       ;
; uberACync:Sink|WideOr1~3                                                                                                                         ; 1       ;
; uberACync:Sink|WideOr1~2                                                                                                                         ; 1       ;
; uberACync:Sink|WideOr1~1                                                                                                                         ; 1       ;
; uberACync:Sink|WideOr1~0                                                                                                                         ; 1       ;
; uberACync:Sink|PrbsShift~7                                                                                                                       ; 1       ;
; uberACync:Sink|PrbsShift[7]                                                                                                                      ; 1       ;
; uberACync:Sink|PrbsShift~6                                                                                                                       ; 1       ;
; uberACync:Sink|PrbsShift[12]                                                                                                                     ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|_~1                                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|_~0                                                ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~8                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10~0                                   ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~6                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|_~3                                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2~0                                    ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1~0                                    ; 1       ;
; uberACync:Sink|Selector70~7                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~6                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~5                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~4                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~3                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~2                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~1                                                                                                                      ; 1       ;
; uberACync:Sink|Selector70~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector69~1                                                                                                                      ; 1       ;
; uberACync:Sink|Selector69~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector58~0                                                                                                                      ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~8                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~7                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~6                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_e66:rdempty_eq_comp_msb|data_wire[0]~0                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~3                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~2                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~0                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~8                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~7                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~5                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_e66:rdempty_eq_comp_lsb|data_wire[0]~0                                 ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~3                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~2                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~0                              ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~10                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~9                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~8                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~7                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~6                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~5                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~4                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~3                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~2                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~1                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~0                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~10                            ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~8                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~7                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~6                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~5                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~4                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~3                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~2                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~1                             ; 1       ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~0                             ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~8                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10~0                                    ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~6                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|_~2                                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2~0                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1~0                                     ; 1       ;
; uberACync:Sink|FifosClear~0                                                                                                                      ; 1       ;
; uberACync:Sink|Selector136~8                                                                                                                     ; 1       ;
; uberACync:Sink|Selector136~7                                                                                                                     ; 1       ;
; uberACync:Sink|Selector136~6                                                                                                                     ; 1       ;
; uberACync:Sink|Selector136~5                                                                                                                     ; 1       ;
; uberACync:Sink|Selector136~4                                                                                                                     ; 1       ;
; uberACync:Sink|Selector136~3                                                                                                                     ; 1       ;
; uberACync:Sink|Selector136~2                                                                                                                     ; 1       ;
; uberACync:Sink|Selector136~1                                                                                                                     ; 1       ;
; uberACync:Sink|Selector135~4                                                                                                                     ; 1       ;
; uberACync:Sink|Selector135~3                                                                                                                     ; 1       ;
; uberACync:Sink|Selector135~2                                                                                                                     ; 1       ;
; uberACync:Sink|Selector135~1                                                                                                                     ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|cmpr_c66:rdempty_eq_comp1_msb|data_wire[0]~0                                 ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~6                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~5                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_msb_mux|result_node[0]~3                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~8                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~7                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~6                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~5                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~4                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~3                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~2                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~1                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux|result_node[0]~0                               ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~7                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~4                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_msb_mux|result_node[0]~0                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~9                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~6                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~5                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~2                              ; 1       ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:wrfull_eq_comp_lsb_mux|result_node[0]~1                              ; 1       ;
; uberACync:Sink|Selector42~1                                                                                                                      ; 1       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+----------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
; Name                                                                                                     ; Type ; Mode             ; Clock Mode  ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size   ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
+----------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks ; 4096         ; 64           ; 4096         ; 64           ; yes                    ; no                      ; yes                    ; yes                     ; 262144 ; 4096                        ; 64                          ; 4096                        ; 64                          ; 262144              ; 32   ; None ; M9K_X33_Y13_N0, M9K_X22_Y13_N0, M9K_X33_Y5_N0, M9K_X22_Y11_N0, M9K_X22_Y3_N0, M9K_X22_Y1_N0, M9K_X33_Y3_N0, M9K_X22_Y9_N0, M9K_X22_Y20_N0, M9K_X22_Y18_N0, M9K_X33_Y9_N0, M9K_X33_Y7_N0, M9K_X22_Y14_N0, M9K_X33_Y15_N0, M9K_X22_Y4_N0, M9K_X33_Y8_N0, M9K_X22_Y7_N0, M9K_X22_Y8_N0, M9K_X22_Y10_N0, M9K_X33_Y10_N0, M9K_X33_Y14_N0, M9K_X33_Y6_N0, M9K_X22_Y2_N0, M9K_X22_Y5_N0, M9K_X22_Y12_N0, M9K_X22_Y16_N0, M9K_X33_Y16_N0, M9K_X33_Y11_N0, M9K_X33_Y12_N0, M9K_X22_Y15_N0, M9K_X22_Y6_N0, M9K_X33_Y4_N0                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 32768        ; 8            ; 32768        ; 8            ; yes                    ; no                      ; yes                    ; yes                     ; 262144 ; 32768                       ; 8                           ; 32768                       ; 8                           ; 262144              ; 32   ; None ; M9K_X33_Y27_N0, M9K_X33_Y29_N0, M9K_X33_Y30_N0, M9K_X22_Y33_N0, M9K_X33_Y32_N0, M9K_X22_Y27_N0, M9K_X22_Y28_N0, M9K_X22_Y32_N0, M9K_X22_Y26_N0, M9K_X33_Y31_N0, M9K_X22_Y19_N0, M9K_X33_Y33_N0, M9K_X22_Y21_N0, M9K_X22_Y25_N0, M9K_X22_Y29_N0, M9K_X22_Y17_N0, M9K_X33_Y26_N0, M9K_X22_Y31_N0, M9K_X22_Y30_N0, M9K_X33_Y28_N0, M9K_X33_Y24_N0, M9K_X22_Y22_N0, M9K_X22_Y24_N0, M9K_X22_Y23_N0, M9K_X33_Y23_N0, M9K_X33_Y18_N0, M9K_X33_Y19_N0, M9K_X33_Y17_N0, M9K_X33_Y20_N0, M9K_X33_Y22_N0, M9K_X33_Y25_N0, M9K_X33_Y21_N0 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+----------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


+------------------------------------------------+
; Routing Usage Summary                          ;
+-----------------------+------------------------+
; Routing Resource Type ; Usage                  ;
+-----------------------+------------------------+
; Block interconnects   ; 2,976 / 71,559 ( 4 % ) ;
; C16 interconnects     ; 137 / 2,597 ( 5 % )    ;
; C4 interconnects      ; 1,755 / 46,848 ( 4 % ) ;
; Direct links          ; 242 / 71,559 ( < 1 % ) ;
; Global clocks         ; 6 / 20 ( 30 % )        ;
; Local interconnects   ; 673 / 24,624 ( 3 % )   ;
; R24 interconnects     ; 138 / 2,496 ( 6 % )    ;
; R4 interconnects      ; 1,896 / 62,424 ( 3 % ) ;
+-----------------------+------------------------+


+----------------------------------------------------------------------------+
; LAB Logic Elements                                                         ;
+---------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 12.27) ; Number of LABs  (Total = 79) ;
+---------------------------------------------+------------------------------+
; 1                                           ; 8                            ;
; 2                                           ; 2                            ;
; 3                                           ; 2                            ;
; 4                                           ; 0                            ;
; 5                                           ; 1                            ;
; 6                                           ; 1                            ;
; 7                                           ; 2                            ;
; 8                                           ; 6                            ;
; 9                                           ; 0                            ;
; 10                                          ; 0                            ;
; 11                                          ; 2                            ;
; 12                                          ; 1                            ;
; 13                                          ; 1                            ;
; 14                                          ; 2                            ;
; 15                                          ; 13                           ;
; 16                                          ; 38                           ;
+---------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 1.96) ; Number of LABs  (Total = 79) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 34                           ;
; 1 Clock                            ; 68                           ;
; 1 Clock enable                     ; 29                           ;
; 1 Sync. clear                      ; 2                            ;
; 1 Sync. load                       ; 5                            ;
; 2 Clock enables                    ; 8                            ;
; 2 Clocks                           ; 9                            ;
+------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Signals Sourced                                                         ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 19.44) ; Number of LABs  (Total = 79) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 2                            ;
; 2                                            ; 6                            ;
; 3                                            ; 0                            ;
; 4                                            ; 2                            ;
; 5                                            ; 1                            ;
; 6                                            ; 1                            ;
; 7                                            ; 1                            ;
; 8                                            ; 0                            ;
; 9                                            ; 0                            ;
; 10                                           ; 1                            ;
; 11                                           ; 0                            ;
; 12                                           ; 2                            ;
; 13                                           ; 1                            ;
; 14                                           ; 3                            ;
; 15                                           ; 2                            ;
; 16                                           ; 2                            ;
; 17                                           ; 4                            ;
; 18                                           ; 0                            ;
; 19                                           ; 1                            ;
; 20                                           ; 4                            ;
; 21                                           ; 3                            ;
; 22                                           ; 7                            ;
; 23                                           ; 2                            ;
; 24                                           ; 8                            ;
; 25                                           ; 5                            ;
; 26                                           ; 3                            ;
; 27                                           ; 6                            ;
; 28                                           ; 4                            ;
; 29                                           ; 1                            ;
; 30                                           ; 3                            ;
; 31                                           ; 1                            ;
; 32                                           ; 3                            ;
+----------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 6.96) ; Number of LABs  (Total = 79) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 11                           ;
; 2                                               ; 4                            ;
; 3                                               ; 2                            ;
; 4                                               ; 3                            ;
; 5                                               ; 9                            ;
; 6                                               ; 7                            ;
; 7                                               ; 9                            ;
; 8                                               ; 7                            ;
; 9                                               ; 3                            ;
; 10                                              ; 8                            ;
; 11                                              ; 7                            ;
; 12                                              ; 4                            ;
; 13                                              ; 1                            ;
; 14                                              ; 0                            ;
; 15                                              ; 2                            ;
; 16                                              ; 2                            ;
+-------------------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                         ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 12.22) ; Number of LABs  (Total = 79) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 1                            ;
; 2                                            ; 8                            ;
; 3                                            ; 3                            ;
; 4                                            ; 3                            ;
; 5                                            ; 1                            ;
; 6                                            ; 0                            ;
; 7                                            ; 4                            ;
; 8                                            ; 5                            ;
; 9                                            ; 5                            ;
; 10                                           ; 6                            ;
; 11                                           ; 2                            ;
; 12                                           ; 7                            ;
; 13                                           ; 2                            ;
; 14                                           ; 6                            ;
; 15                                           ; 2                            ;
; 16                                           ; 5                            ;
; 17                                           ; 2                            ;
; 18                                           ; 4                            ;
; 19                                           ; 0                            ;
; 20                                           ; 1                            ;
; 21                                           ; 1                            ;
; 22                                           ; 1                            ;
; 23                                           ; 1                            ;
; 24                                           ; 0                            ;
; 25                                           ; 1                            ;
; 26                                           ; 1                            ;
; 27                                           ; 0                            ;
; 28                                           ; 0                            ;
; 29                                           ; 2                            ;
; 30                                           ; 3                            ;
; 31                                           ; 0                            ;
; 32                                           ; 1                            ;
+----------------------------------------------+------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 12    ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 18    ;
+----------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass         ; 56        ; 0            ; 56        ; 0            ; 0            ; 56        ; 56        ; 0            ; 56        ; 56        ; 0            ; 2            ; 0            ; 0            ; 18           ; 0            ; 2            ; 18           ; 0            ; 0            ; 0            ; 2            ; 0            ; 0            ; 0            ; 0            ; 0            ; 56        ; 0            ; 0            ;
; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable ; 0         ; 56           ; 0         ; 56           ; 56           ; 0         ; 0         ; 56           ; 0         ; 0         ; 56           ; 54           ; 56           ; 56           ; 38           ; 56           ; 54           ; 38           ; 56           ; 56           ; 56           ; 54           ; 56           ; 56           ; 56           ; 56           ; 56           ; 0         ; 56           ; 56           ;
; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Prbs               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; AdcClk             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacLoad            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; PotClk             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; PotStart           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Led                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacWr              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; AdcConvert         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacAddr[3]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacAddr[2]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacAddr[1]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacAddr[0]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[15]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[14]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[13]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[12]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[11]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[10]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[9]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[8]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DacDat[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigOut[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ExtendOut[1]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ExtendOut[0]       ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Clk100             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ExtendIn[0]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; ExtendIn[1]        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Master             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Adc1               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Adc4               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Adc3               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; Adc2               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[7]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[6]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[5]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[4]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[3]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[2]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[1]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; DigIn[0]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; AC60Hz             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; PotDat             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+---------------------------------------------------------------------------------------------+
; Fitter Device Options                                                                       ;
+------------------------------------------------------------------+--------------------------+
; Option                                                           ; Setting                  ;
+------------------------------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
; Enable INIT_DONE output                                          ; Off                      ;
; Configuration scheme                                             ; Active Serial            ;
; Error detection CRC                                              ; Off                      ;
; Enable open drain on CRC_ERROR pin                               ; Off                      ;
; Enable input tri-state on active configuration pins in user mode ; Off                      ;
; Configuration Voltage Level                                      ; Auto                     ;
; Force Configuration Voltage Level                                ; Off                      ;
; nCEO                                                             ; Unreserved               ;
; Data[0]                                                          ; As input tri-stated      ;
; Data[1]/ASDO                                                     ; As input tri-stated      ;
; Data[7..2]                                                       ; Unreserved               ;
; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
; Other Active Parallel pins                                       ; Unreserved               ;
; DCLK                                                             ; As output driving ground ;
; Base pin-out file on sameframe device                            ; Off                      ;
+------------------------------------------------------------------+--------------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 °C   ;
; High Junction Temperature ; 85 °C  ;
+---------------------------+--------+


+-----------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Summary                                                       ;
+---------------------------------------------------+-----------------------------+-------------------+
; Source Clock(s)                                   ; Destination Clock(s)        ; Delay Added in ns ;
+---------------------------------------------------+-----------------------------+-------------------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 78.2              ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 24.1              ;
+---------------------------------------------------+-----------------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                         ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------+
; Source Register                                                                 ; Destination Register                                                                                                            ; Delay Added in ns ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------+
; uberACync:Sink|DigInBuf[6]                                                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_datain_reg0   ; 1.529             ;
; uberACync:Sink|DigInBuf[0]                                                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_datain_reg0   ; 1.247             ;
; uberACync:Sink|DigInBuf[2]                                                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_datain_reg0  ; 1.200             ;
; uberACync:Sink|DigInBuf[4]                                                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_datain_reg0   ; 1.180             ;
; uberACync:Sink|DigInBuf[7]                                                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_datain_reg0  ; 0.986             ;
; uberACync:Sink|DigInBuf[3]                                                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_datain_reg0   ; 0.812             ;
; uberACync:Sink|DigInBuf[1]                                                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_datain_reg0   ; 0.808             ;
; uberACync:Sink|DigInBuf[5]                                                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_datain_reg0   ; 0.787             ;
; uberACync:Sink|FifosClear                                                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                  ; 0.626             ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_address_reg0 ; 0.096             ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------+
Note: This table only shows the top 10 path(s) that have the largest delay added for hold.


+-----------------+
; Fitter Messages ;
+-----------------+
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (119006): Selected device EP4CE22E22C8 for design "ACync"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (15535): Implemented PLL "altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|pll1" as Cyclone IV E PLL type
    Info (15099): Implementing clock multiplication of 3, clock division of 5, and phase shift of 0 degrees (0 ps) for altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] port
Info (171001): Fitter is performing a Fast Fit compilation, which decreases Fitter effort to reduce compilation time
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info (176445): Device EP4CE10E22C8 is compatible
    Info (176445): Device EP4CE6E22C8 is compatible
    Info (176445): Device EP4CE15E22C8 is compatible
Info (169124): Fitter converted 4 user pins into dedicated programming pins
    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12
    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity dcfifo_h0l1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a* 
    Info (332165): Entity dcfifo_o1l1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_te9:dffpipe15|dffe16a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_se9:dffpipe12|dffe13a* 
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ACync.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained generated clocks found in the design
Info (332144): No user constrained base clocks found in the design
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info (332127): Assuming a default timing requirement
Info (332111): Found 6 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   16.666 60MHz|altpll_component|auto_generated|pll1|clk[0]
    Info (332111):   10.000       Clk100
    Info (332111):    1.000 uberACync:Sink|FifoAnaRdClk
    Info (332111):    1.000 uberACync:Sink|FifoAnaWrClk
    Info (332111):    1.000 uberACync:Sink|FifoDigRdClk
    Info (332111):    1.000 uberACync:Sink|FifoDigWrClk
Info (176353): Automatically promoted node altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1)
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info (176353): Automatically promoted node uberACync:Sink|FifoAnaRdClk 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node uberACync:Sink|Selector136~8
Info (176353): Automatically promoted node uberACync:Sink|FifoAnaWrClk 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node uberACync:Sink|Selector135~4
Info (176353): Automatically promoted node uberACync:Sink|FifoDigRdClk 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node uberACync:Sink|Selector70~4
Info (176353): Automatically promoted node uberACync:Sink|FifoDigWrClk 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node uberACync:Sink|Selector69~0
        Info (176357): Destination node uberACync:Sink|Selector69~1
Info (176353): Automatically promoted node uberACync:Sink|FifosClear 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]
        Info (176357): Destination node FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]
        Info (176357): Destination node uberACync:Sink|FifosClear~0
Warning (128008): Can't perform fitting netlist optimizations during fast fit compilation
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 3% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22
Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
Info (11888): Total time spent on timing analysis during the Fitter is 1.98 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169177): 14 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin Clk100 uses I/O standard 3.3-V LVCMOS at 23
    Info (169178): Pin ExtendIn[0] uses I/O standard 3.3-V LVCMOS at 55
    Info (169178): Pin ExtendIn[1] uses I/O standard 3.3-V LVCMOS at 54
    Info (169178): Pin Master uses I/O standard 3.3-V LVCMOS at 24
    Info (169178): Pin DigIn[7] uses I/O standard 3.3-V LVCMOS at 44
    Info (169178): Pin DigIn[6] uses I/O standard 3.3-V LVCMOS at 43
    Info (169178): Pin DigIn[5] uses I/O standard 3.3-V LVCMOS at 42
    Info (169178): Pin DigIn[4] uses I/O standard 3.3-V LVCMOS at 39
    Info (169178): Pin DigIn[3] uses I/O standard 3.3-V LVCMOS at 33
    Info (169178): Pin DigIn[2] uses I/O standard 3.3-V LVCMOS at 32
    Info (169178): Pin DigIn[1] uses I/O standard 3.3-V LVCMOS at 31
    Info (169178): Pin DigIn[0] uses I/O standard 3.3-V LVCMOS at 30
    Info (169178): Pin AC60Hz uses I/O standard 3.3-V LVCMOS at 53
    Info (169178): Pin PotDat uses I/O standard 3.3-V LVCMOS at 126
Info (144001): Generated suppressed messages file C:/Projects/2015 ACync/Altera/output_files/ACync.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 1009 megabytes
    Info: Processing ended: Tue Mar 31 14:48:29 2015
    Info: Elapsed time: 00:00:18
    Info: Total CPU time (on all processors): 00:00:19


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Projects/2015 ACync/Altera/output_files/ACync.fit.smsg.


