Analysis & Elaboration report for ACync
Wed Apr 01 12:24:26 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Elaboration Summary
  3. Parallel Compilation
  4. Analysis & Elaboration IP Cores Summary
  5. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component
  6. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated
  7. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p
  8. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p
  9. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram
 10. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp
 11. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12
 12. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp
 13. Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15
 14. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component
 15. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated
 16. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p
 17. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p
 18. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram
 19. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp
 20. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14
 21. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp
 22. Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17
 23. Parameter Settings for User Entity Instance: altpll0:60MHz|altpll:altpll_component
 24. Parameter Settings for User Entity Instance: FifoA:FifoAnalog|dcfifo:dcfifo_component
 25. Parameter Settings for User Entity Instance: FifoD:FifoDigital|dcfifo:dcfifo_component
 26. altpll Parameter Settings by Entity Instance
 27. dcfifo Parameter Settings by Entity Instance
 28. Analysis & Elaboration Settings
 29. Analysis & Elaboration Messages
 30. Analysis & Elaboration Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Elaboration Summary                                                   ;
+------------------------------------+---------------------------------------------+
; Analysis & Elaboration Status      ; Successful - Wed Apr 01 12:24:26 2015       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; ACync                                       ;
; Top-level Entity Name              ; ACync_block                                 ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; N/A until Partition Merge                   ;
;     Total combinational functions  ; N/A until Partition Merge                   ;
;     Dedicated logic registers      ; N/A until Partition Merge                   ;
; Total registers                    ; N/A until Partition Merge                   ;
; Total pins                         ; N/A until Partition Merge                   ;
; Total virtual pins                 ; N/A until Partition Merge                   ;
; Total memory bits                  ; N/A until Partition Merge                   ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                   ;
; Total PLLs                         ; N/A until Partition Merge                   ;
+------------------------------------+---------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Elaboration IP Cores Summary                                                                                                  ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                ; IP Include File                         ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------------------------------+
; Altera ; ALTPLL       ; 13.1    ; N/A          ; N/A          ; |ACync_block|altpll0:60MHz     ; C:/Projects/2015 ACync/Altera/altpll0.v ;
; Altera ; FIFO         ; 13.1    ; N/A          ; N/A          ; |ACync_block|FifoA:FifoAnalog  ; C:/Projects/2015 ACync/Altera/FifoA.v   ;
; Altera ; FIFO         ; 13.1    ; N/A          ; N/A          ; |ACync_block|FifoD:FifoDigital ; C:/Projects/2015 ACync/Altera/FifoD.v   ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------------------------------+


+-----------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+----------------+
; Assignment                      ; Value ; From ; To             ;
+---------------------------------+-------+------+----------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -              ;
+---------------------------------+-------+------+----------------+


+----------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated         ;
+---------------------------------------+------------------------+------+----------------------------+
; Assignment                            ; Value                  ; From ; To                         ;
+---------------------------------------+------------------------+------+----------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                    ; -    ; -                          ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF                    ; -    ; -                          ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF                    ; -    ; -                          ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3                      ; -    ; -                          ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rdemp_eq_comp_lsb_aeb      ;
; POWER_UP_LEVEL                        ; HIGH                   ; -    ; rdemp_eq_comp_lsb_aeb      ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rdemp_eq_comp_msb_aeb      ;
; POWER_UP_LEVEL                        ; HIGH                   ; -    ; rdemp_eq_comp_msb_aeb      ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rs_dgwp_reg                ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; wrfull_eq_comp_lsb_mux_reg ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; wrfull_eq_comp_msb_mux_reg ;
; POWER_UP_LEVEL                        ; LOW                    ; -    ; wrptr_g                    ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; ws_dgrp_reg                ;
+---------------------------------------+------------------------+------+----------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                     ;
+----------------+-------+------+----------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                             ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                ;
+----------------+-------+------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                     ;
+----------------+-------+------+----------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                             ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                ;
+----------------+-------+------+----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram ;
+---------------------------------+--------------------+------+-------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                    ;
+---------------------------------+--------------------+------+-------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                     ;
+---------------------------------+--------------------+------+-------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp ;
+-----------------------------+------------------------+------+---------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                      ;
+-----------------------------+------------------------+------+---------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                       ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                       ;
+-----------------------------+------------------------+------+---------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                         ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                          ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp ;
+-----------------------------+------------------------+------+---------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                      ;
+-----------------------------+------------------------+------+---------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                       ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                       ;
+-----------------------------+------------------------+------+---------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                         ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                          ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------+
; Assignment                      ; Value ; From ; To              ;
+---------------------------------+-------+------+-----------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -               ;
+---------------------------------+-------+------+-----------------+


+----------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated        ;
+---------------------------------------+------------------------+------+----------------------------+
; Assignment                            ; Value                  ; From ; To                         ;
+---------------------------------------+------------------------+------+----------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                    ; -    ; -                          ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF                    ; -    ; -                          ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF                    ; -    ; -                          ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3                      ; -    ; -                          ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rdemp_eq_comp_lsb_aeb      ;
; POWER_UP_LEVEL                        ; HIGH                   ; -    ; rdemp_eq_comp_lsb_aeb      ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rdemp_eq_comp_msb_aeb      ;
; POWER_UP_LEVEL                        ; HIGH                   ; -    ; rdemp_eq_comp_msb_aeb      ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; rs_dgwp_reg                ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; wrfull_eq_comp_lsb_mux_reg ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; wrfull_eq_comp_msb_mux_reg ;
; POWER_UP_LEVEL                        ; LOW                    ; -    ; wrptr_g                    ;
; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS ; -    ; ws_dgrp_reg                ;
+---------------------------------------+------------------------+------+----------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                      ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                 ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                      ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                 ;
+----------------+-------+------+-----------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                     ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                      ;
+---------------------------------+--------------------+------+--------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                       ;
+-----------------------------+------------------------+------+----------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                        ;
+-----------------------------+------------------------+------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                       ;
+-----------------------------+------------------------+------+----------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                        ;
+-----------------------------+------------------------+------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altpll0:60MHz|altpll:altpll_component ;
+-------------------------------+---------------------------+------------------------+
; Parameter Name                ; Value                     ; Type                   ;
+-------------------------------+---------------------------+------------------------+
; OPERATION_MODE                ; NORMAL                    ; Untyped                ;
; PLL_TYPE                      ; AUTO                      ; Untyped                ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=altpll0 ; Untyped                ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                ;
; INCLK0_INPUT_FREQUENCY        ; 10000                     ; Signed Integer         ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                ;
; LOCK_HIGH                     ; 1                         ; Untyped                ;
; LOCK_LOW                      ; 1                         ; Untyped                ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                ;
; SKIP_VCO                      ; OFF                       ; Untyped                ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                ;
; BANDWIDTH                     ; 0                         ; Untyped                ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                ;
; DOWN_SPREAD                   ; 0                         ; Untyped                ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK1_MULTIPLY_BY              ; 1                         ; Untyped                ;
; CLK0_MULTIPLY_BY              ; 3                         ; Signed Integer         ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK1_DIVIDE_BY                ; 1                         ; Untyped                ;
; CLK0_DIVIDE_BY                ; 5                         ; Signed Integer         ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK1_DUTY_CYCLE               ; 50                        ; Untyped                ;
; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer         ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                ;
; DPA_DIVIDER                   ; 0                         ; Untyped                ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                ;
; VCO_MIN                       ; 0                         ; Untyped                ;
; VCO_MAX                       ; 0                         ; Untyped                ;
; VCO_CENTER                    ; 0                         ; Untyped                ;
; PFD_MIN                       ; 0                         ; Untyped                ;
; PFD_MAX                       ; 0                         ; Untyped                ;
; M_INITIAL                     ; 0                         ; Untyped                ;
; M                             ; 0                         ; Untyped                ;
; N                             ; 1                         ; Untyped                ;
; M2                            ; 1                         ; Untyped                ;
; N2                            ; 1                         ; Untyped                ;
; SS                            ; 1                         ; Untyped                ;
; C0_HIGH                       ; 0                         ; Untyped                ;
; C1_HIGH                       ; 0                         ; Untyped                ;
; C2_HIGH                       ; 0                         ; Untyped                ;
; C3_HIGH                       ; 0                         ; Untyped                ;
; C4_HIGH                       ; 0                         ; Untyped                ;
; C5_HIGH                       ; 0                         ; Untyped                ;
; C6_HIGH                       ; 0                         ; Untyped                ;
; C7_HIGH                       ; 0                         ; Untyped                ;
; C8_HIGH                       ; 0                         ; Untyped                ;
; C9_HIGH                       ; 0                         ; Untyped                ;
; C0_LOW                        ; 0                         ; Untyped                ;
; C1_LOW                        ; 0                         ; Untyped                ;
; C2_LOW                        ; 0                         ; Untyped                ;
; C3_LOW                        ; 0                         ; Untyped                ;
; C4_LOW                        ; 0                         ; Untyped                ;
; C5_LOW                        ; 0                         ; Untyped                ;
; C6_LOW                        ; 0                         ; Untyped                ;
; C7_LOW                        ; 0                         ; Untyped                ;
; C8_LOW                        ; 0                         ; Untyped                ;
; C9_LOW                        ; 0                         ; Untyped                ;
; C0_INITIAL                    ; 0                         ; Untyped                ;
; C1_INITIAL                    ; 0                         ; Untyped                ;
; C2_INITIAL                    ; 0                         ; Untyped                ;
; C3_INITIAL                    ; 0                         ; Untyped                ;
; C4_INITIAL                    ; 0                         ; Untyped                ;
; C5_INITIAL                    ; 0                         ; Untyped                ;
; C6_INITIAL                    ; 0                         ; Untyped                ;
; C7_INITIAL                    ; 0                         ; Untyped                ;
; C8_INITIAL                    ; 0                         ; Untyped                ;
; C9_INITIAL                    ; 0                         ; Untyped                ;
; C0_MODE                       ; BYPASS                    ; Untyped                ;
; C1_MODE                       ; BYPASS                    ; Untyped                ;
; C2_MODE                       ; BYPASS                    ; Untyped                ;
; C3_MODE                       ; BYPASS                    ; Untyped                ;
; C4_MODE                       ; BYPASS                    ; Untyped                ;
; C5_MODE                       ; BYPASS                    ; Untyped                ;
; C6_MODE                       ; BYPASS                    ; Untyped                ;
; C7_MODE                       ; BYPASS                    ; Untyped                ;
; C8_MODE                       ; BYPASS                    ; Untyped                ;
; C9_MODE                       ; BYPASS                    ; Untyped                ;
; C0_PH                         ; 0                         ; Untyped                ;
; C1_PH                         ; 0                         ; Untyped                ;
; C2_PH                         ; 0                         ; Untyped                ;
; C3_PH                         ; 0                         ; Untyped                ;
; C4_PH                         ; 0                         ; Untyped                ;
; C5_PH                         ; 0                         ; Untyped                ;
; C6_PH                         ; 0                         ; Untyped                ;
; C7_PH                         ; 0                         ; Untyped                ;
; C8_PH                         ; 0                         ; Untyped                ;
; C9_PH                         ; 0                         ; Untyped                ;
; L0_HIGH                       ; 1                         ; Untyped                ;
; L1_HIGH                       ; 1                         ; Untyped                ;
; G0_HIGH                       ; 1                         ; Untyped                ;
; G1_HIGH                       ; 1                         ; Untyped                ;
; G2_HIGH                       ; 1                         ; Untyped                ;
; G3_HIGH                       ; 1                         ; Untyped                ;
; E0_HIGH                       ; 1                         ; Untyped                ;
; E1_HIGH                       ; 1                         ; Untyped                ;
; E2_HIGH                       ; 1                         ; Untyped                ;
; E3_HIGH                       ; 1                         ; Untyped                ;
; L0_LOW                        ; 1                         ; Untyped                ;
; L1_LOW                        ; 1                         ; Untyped                ;
; G0_LOW                        ; 1                         ; Untyped                ;
; G1_LOW                        ; 1                         ; Untyped                ;
; G2_LOW                        ; 1                         ; Untyped                ;
; G3_LOW                        ; 1                         ; Untyped                ;
; E0_LOW                        ; 1                         ; Untyped                ;
; E1_LOW                        ; 1                         ; Untyped                ;
; E2_LOW                        ; 1                         ; Untyped                ;
; E3_LOW                        ; 1                         ; Untyped                ;
; L0_INITIAL                    ; 1                         ; Untyped                ;
; L1_INITIAL                    ; 1                         ; Untyped                ;
; G0_INITIAL                    ; 1                         ; Untyped                ;
; G1_INITIAL                    ; 1                         ; Untyped                ;
; G2_INITIAL                    ; 1                         ; Untyped                ;
; G3_INITIAL                    ; 1                         ; Untyped                ;
; E0_INITIAL                    ; 1                         ; Untyped                ;
; E1_INITIAL                    ; 1                         ; Untyped                ;
; E2_INITIAL                    ; 1                         ; Untyped                ;
; E3_INITIAL                    ; 1                         ; Untyped                ;
; L0_MODE                       ; BYPASS                    ; Untyped                ;
; L1_MODE                       ; BYPASS                    ; Untyped                ;
; G0_MODE                       ; BYPASS                    ; Untyped                ;
; G1_MODE                       ; BYPASS                    ; Untyped                ;
; G2_MODE                       ; BYPASS                    ; Untyped                ;
; G3_MODE                       ; BYPASS                    ; Untyped                ;
; E0_MODE                       ; BYPASS                    ; Untyped                ;
; E1_MODE                       ; BYPASS                    ; Untyped                ;
; E2_MODE                       ; BYPASS                    ; Untyped                ;
; E3_MODE                       ; BYPASS                    ; Untyped                ;
; L0_PH                         ; 0                         ; Untyped                ;
; L1_PH                         ; 0                         ; Untyped                ;
; G0_PH                         ; 0                         ; Untyped                ;
; G1_PH                         ; 0                         ; Untyped                ;
; G2_PH                         ; 0                         ; Untyped                ;
; G3_PH                         ; 0                         ; Untyped                ;
; E0_PH                         ; 0                         ; Untyped                ;
; E1_PH                         ; 0                         ; Untyped                ;
; E2_PH                         ; 0                         ; Untyped                ;
; E3_PH                         ; 0                         ; Untyped                ;
; M_PH                          ; 0                         ; Untyped                ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                ;
; CLK0_COUNTER                  ; G0                        ; Untyped                ;
; CLK1_COUNTER                  ; G0                        ; Untyped                ;
; CLK2_COUNTER                  ; G0                        ; Untyped                ;
; CLK3_COUNTER                  ; G0                        ; Untyped                ;
; CLK4_COUNTER                  ; G0                        ; Untyped                ;
; CLK5_COUNTER                  ; G0                        ; Untyped                ;
; CLK6_COUNTER                  ; E0                        ; Untyped                ;
; CLK7_COUNTER                  ; E1                        ; Untyped                ;
; CLK8_COUNTER                  ; E2                        ; Untyped                ;
; CLK9_COUNTER                  ; E3                        ; Untyped                ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                ;
; M_TIME_DELAY                  ; 0                         ; Untyped                ;
; N_TIME_DELAY                  ; 0                         ; Untyped                ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                ;
; VCO_POST_SCALE                ; 0                         ; Untyped                ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E              ; Untyped                ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                ;
; PORT_CLK1                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                ;
; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                ;
; CBXI_PARAMETER                ; altpll0_altpll            ; Untyped                ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                ;
; WIDTH_CLOCK                   ; 5                         ; Signed Integer         ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                ;
; DEVICE_FAMILY                 ; Cyclone IV E              ; Untyped                ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE         ;
+-------------------------------+---------------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FifoA:FifoAnalog|dcfifo:dcfifo_component ;
+-------------------------+--------------+----------------------------------------------+
; Parameter Name          ; Value        ; Type                                         ;
+-------------------------+--------------+----------------------------------------------+
; WIDTH_BYTEENA           ; 1            ; Untyped                                      ;
; AUTO_CARRY_CHAINS       ; ON           ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF          ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS     ; ON           ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF          ; IGNORE_CASCADE                               ;
; LPM_WIDTH               ; 64           ; Signed Integer                               ;
; LPM_NUMWORDS            ; 4096         ; Signed Integer                               ;
; LPM_WIDTHU              ; 12           ; Signed Integer                               ;
; LPM_SHOWAHEAD           ; OFF          ; Untyped                                      ;
; UNDERFLOW_CHECKING      ; ON           ; Untyped                                      ;
; OVERFLOW_CHECKING       ; ON           ; Untyped                                      ;
; USE_EAB                 ; ON           ; Untyped                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF          ; Untyped                                      ;
; DELAY_RDUSEDW           ; 1            ; Untyped                                      ;
; DELAY_WRUSEDW           ; 1            ; Untyped                                      ;
; RDSYNC_DELAYPIPE        ; 5            ; Signed Integer                               ;
; WRSYNC_DELAYPIPE        ; 5            ; Signed Integer                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE        ; Untyped                                      ;
; MAXIMIZE_SPEED          ; 5            ; Untyped                                      ;
; DEVICE_FAMILY           ; Cyclone IV E ; Untyped                                      ;
; ADD_USEDW_MSB_BIT       ; OFF          ; Untyped                                      ;
; WRITE_ACLR_SYNCH        ; OFF          ; Untyped                                      ;
; READ_ACLR_SYNCH         ; OFF          ; Untyped                                      ;
; CBXI_PARAMETER          ; dcfifo_o1l1  ; Untyped                                      ;
+-------------------------+--------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FifoD:FifoDigital|dcfifo:dcfifo_component ;
+-------------------------+--------------+-----------------------------------------------+
; Parameter Name          ; Value        ; Type                                          ;
+-------------------------+--------------+-----------------------------------------------+
; WIDTH_BYTEENA           ; 1            ; Untyped                                       ;
; AUTO_CARRY_CHAINS       ; ON           ; AUTO_CARRY                                    ;
; IGNORE_CARRY_BUFFERS    ; OFF          ; IGNORE_CARRY                                  ;
; AUTO_CASCADE_CHAINS     ; ON           ; AUTO_CASCADE                                  ;
; IGNORE_CASCADE_BUFFERS  ; OFF          ; IGNORE_CASCADE                                ;
; LPM_WIDTH               ; 8            ; Signed Integer                                ;
; LPM_NUMWORDS            ; 32768        ; Signed Integer                                ;
; LPM_WIDTHU              ; 15           ; Signed Integer                                ;
; LPM_SHOWAHEAD           ; OFF          ; Untyped                                       ;
; UNDERFLOW_CHECKING      ; ON           ; Untyped                                       ;
; OVERFLOW_CHECKING       ; ON           ; Untyped                                       ;
; USE_EAB                 ; ON           ; Untyped                                       ;
; ADD_RAM_OUTPUT_REGISTER ; OFF          ; Untyped                                       ;
; DELAY_RDUSEDW           ; 1            ; Untyped                                       ;
; DELAY_WRUSEDW           ; 1            ; Untyped                                       ;
; RDSYNC_DELAYPIPE        ; 5            ; Signed Integer                                ;
; WRSYNC_DELAYPIPE        ; 5            ; Signed Integer                                ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE        ; Untyped                                       ;
; MAXIMIZE_SPEED          ; 5            ; Untyped                                       ;
; DEVICE_FAMILY           ; Cyclone IV E ; Untyped                                       ;
; ADD_USEDW_MSB_BIT       ; OFF          ; Untyped                                       ;
; WRITE_ACLR_SYNCH        ; OFF          ; Untyped                                       ;
; READ_ACLR_SYNCH         ; OFF          ; Untyped                                       ;
; CBXI_PARAMETER          ; dcfifo_h0l1  ; Untyped                                       ;
+-------------------------+--------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                          ;
+-------------------------------+---------------------------------------+
; Name                          ; Value                                 ;
+-------------------------------+---------------------------------------+
; Number of entity instances    ; 1                                     ;
; Entity Instance               ; altpll0:60MHz|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                ;
;     -- PLL_TYPE               ; AUTO                                  ;
;     -- PRIMARY_CLOCK          ; INCLK0                                ;
;     -- INCLK0_INPUT_FREQUENCY ; 10000                                 ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                     ;
;     -- VCO_MULTIPLY_BY        ; 0                                     ;
;     -- VCO_DIVIDE_BY          ; 0                                     ;
+-------------------------------+---------------------------------------+


+------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                           ;
+----------------------------+-------------------------------------------+
; Name                       ; Value                                     ;
+----------------------------+-------------------------------------------+
; Number of entity instances ; 2                                         ;
; Entity Instance            ; FifoA:FifoAnalog|dcfifo:dcfifo_component  ;
;     -- FIFO Type           ; Dual Clock                                ;
;     -- LPM_WIDTH           ; 64                                        ;
;     -- LPM_NUMWORDS        ; 4096                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                       ;
;     -- USE_EAB             ; ON                                        ;
; Entity Instance            ; FifoD:FifoDigital|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                ;
;     -- LPM_WIDTH           ; 8                                         ;
;     -- LPM_NUMWORDS        ; 32768                                     ;
;     -- LPM_SHOWAHEAD       ; OFF                                       ;
;     -- USE_EAB             ; ON                                        ;
+----------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Elaboration Settings                                                                                      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE22E22C8       ;                    ;
; Top-level entity name                                                      ; ACync_block        ; ACync              ;
; Family name                                                                ; Cyclone IV E       ; Cyclone IV GX      ;
; Verilog Show LMF Mapping Messages                                          ; Off                ;                    ;
; Verilog Version                                                            ; SystemVerilog_2005 ; Verilog_2001       ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------+
; Analysis & Elaboration Messages ;
+---------------------------------+
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file acync_block.bdf
    Info (12023): Found entity 1: ACync_block
Info (12021): Found 1 design units, including 1 entities, in source file uberacync.sv
    Info (12023): Found entity 1: uberACync
Info (12021): Found 1 design units, including 1 entities, in source file altpll0.v
    Info (12023): Found entity 1: altpll0
Info (12021): Found 1 design units, including 1 entities, in source file fifod.v
    Info (12023): Found entity 1: FifoD
Info (12021): Found 1 design units, including 1 entities, in source file fifoa.v
    Info (12023): Found entity 1: FifoA
Info (12127): Elaborating entity "ACync_block" for the top level hierarchy
Info (12128): Elaborating entity "uberACync" for hierarchy "uberACync:Sink"
Info (12128): Elaborating entity "altpll0" for hierarchy "altpll0:60MHz"
Info (12128): Elaborating entity "altpll" for hierarchy "altpll0:60MHz|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "altpll0:60MHz|altpll:altpll_component"
Info (12133): Instantiated megafunction "altpll0:60MHz|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "5"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "3"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "10000"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll0"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/altpll0_altpll.v
    Info (12023): Found entity 1: altpll0_altpll
Info (12128): Elaborating entity "altpll0_altpll" for hierarchy "altpll0:60MHz|altpll:altpll_component|altpll0_altpll:auto_generated"
Info (12128): Elaborating entity "FifoA" for hierarchy "FifoA:FifoAnalog"
Info (12128): Elaborating entity "dcfifo" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component"
Info (12130): Elaborated megafunction instantiation "FifoA:FifoAnalog|dcfifo:dcfifo_component"
Info (12133): Instantiated megafunction "FifoA:FifoAnalog|dcfifo:dcfifo_component" with the following parameter:
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_numwords" = "4096"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "64"
    Info (12134): Parameter "lpm_widthu" = "12"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "5"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_o1l1.tdf
    Info (12023): Found entity 1: dcfifo_o1l1
Info (12128): Elaborating entity "dcfifo_o1l1" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_877.tdf
    Info (12023): Found entity 1: a_graycounter_877
Info (12128): Elaborating entity "a_graycounter_877" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_4lc.tdf
    Info (12023): Found entity 1: a_graycounter_4lc
Info (12128): Elaborating entity "a_graycounter_4lc" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_om31.tdf
    Info (12023): Found entity 1: altsyncram_om31
Info (12128): Elaborating entity "altsyncram_om31" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tld.tdf
    Info (12023): Found entity 1: alt_synch_pipe_tld
Info (12128): Elaborating entity "alt_synch_pipe_tld" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_se9.tdf
    Info (12023): Found entity 1: dffpipe_se9
Info (12128): Elaborating entity "dffpipe_se9" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_uld.tdf
    Info (12023): Found entity 1: alt_synch_pipe_uld
Info (12128): Elaborating entity "alt_synch_pipe_uld" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_te9.tdf
    Info (12023): Found entity 1: dffpipe_te9
Info (12128): Elaborating entity "dffpipe_te9" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_d66.tdf
    Info (12023): Found entity 1: cmpr_d66
Info (12128): Elaborating entity "cmpr_d66" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|cmpr_d66:rdempty_eq_comp1_lsb"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_c66.tdf
    Info (12023): Found entity 1: cmpr_c66
Info (12128): Elaborating entity "cmpr_c66" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|cmpr_c66:rdempty_eq_comp1_msb"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_q76.tdf
    Info (12023): Found entity 1: cmpr_q76
Info (12128): Elaborating entity "cmpr_q76" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|cmpr_q76:rdfull_eq_comp"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_j28.tdf
    Info (12023): Found entity 1: mux_j28
Info (12128): Elaborating entity "mux_j28" for hierarchy "FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|mux_j28:rdemp_eq_comp_lsb_mux"
Info (12128): Elaborating entity "FifoD" for hierarchy "FifoD:FifoDigital"
Info (12128): Elaborating entity "dcfifo" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component"
Info (12130): Elaborated megafunction instantiation "FifoD:FifoDigital|dcfifo:dcfifo_component"
Info (12133): Instantiated megafunction "FifoD:FifoDigital|dcfifo:dcfifo_component" with the following parameter:
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_numwords" = "32768"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "8"
    Info (12134): Parameter "lpm_widthu" = "15"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "5"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_h0l1.tdf
    Info (12023): Found entity 1: dcfifo_h0l1
Info (12128): Elaborating entity "dcfifo_h0l1" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_b77.tdf
    Info (12023): Found entity 1: a_graycounter_b77
Info (12128): Elaborating entity "a_graycounter_b77" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_7lc.tdf
    Info (12023): Found entity 1: a_graycounter_7lc
Info (12128): Elaborating entity "a_graycounter_7lc" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qj31.tdf
    Info (12023): Found entity 1: altsyncram_qj31
Info (12128): Elaborating entity "altsyncram_qj31" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_d87.tdf
    Info (12023): Found entity 1: decode_d87
Info (12128): Elaborating entity "decode_d87" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|decode_d87:decode12"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_t28.tdf
    Info (12023): Found entity 1: mux_t28
Info (12128): Elaborating entity "mux_t28" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|mux_t28:mux13"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_0md.tdf
    Info (12023): Found entity 1: alt_synch_pipe_0md
Info (12128): Elaborating entity "alt_synch_pipe_0md" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ve9.tdf
    Info (12023): Found entity 1: dffpipe_ve9
Info (12128): Elaborating entity "dffpipe_ve9" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_1md.tdf
    Info (12023): Found entity 1: alt_synch_pipe_1md
Info (12128): Elaborating entity "alt_synch_pipe_1md" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_0f9.tdf
    Info (12023): Found entity 1: dffpipe_0f9
Info (12128): Elaborating entity "dffpipe_0f9" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf
    Info (12023): Found entity 1: cmpr_e66
Info (12128): Elaborating entity "cmpr_e66" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_e66:rdempty_eq_comp1_lsb"
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_t76.tdf
    Info (12023): Found entity 1: cmpr_t76
Info (12128): Elaborating entity "cmpr_t76" for hierarchy "FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|cmpr_t76:rdfull_eq_comp"
Info (144001): Generated suppressed messages file C:/Projects/2015 ACync/Altera/output_files/ACync.map.smsg


+--------------------------------------------+
; Analysis & Elaboration Suppressed Messages ;
+--------------------------------------------+
The suppressed messages can be found in C:/Projects/2015 ACync/Altera/output_files/ACync.map.smsg.


