TimeQuest Timing Analyzer report for ACync
Tue Mar 31 14:48:43 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Timing Closure Recommendations
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
 13. Slow 1200mV 85C Model Setup: 'uberACync:Sink|FifoDigWrClk'
 14. Slow 1200mV 85C Model Setup: 'uberACync:Sink|FifoAnaWrClk'
 15. Slow 1200mV 85C Model Setup: 'uberACync:Sink|FifoDigRdClk'
 16. Slow 1200mV 85C Model Setup: 'uberACync:Sink|FifoAnaRdClk'
 17. Slow 1200mV 85C Model Hold: 'uberACync:Sink|FifoAnaWrClk'
 18. Slow 1200mV 85C Model Hold: 'uberACync:Sink|FifoDigWrClk'
 19. Slow 1200mV 85C Model Hold: 'uberACync:Sink|FifoDigRdClk'
 20. Slow 1200mV 85C Model Hold: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
 21. Slow 1200mV 85C Model Hold: 'uberACync:Sink|FifoAnaRdClk'
 22. Slow 1200mV 85C Model Recovery: 'uberACync:Sink|FifoDigWrClk'
 23. Slow 1200mV 85C Model Recovery: 'uberACync:Sink|FifoAnaRdClk'
 24. Slow 1200mV 85C Model Recovery: 'uberACync:Sink|FifoAnaWrClk'
 25. Slow 1200mV 85C Model Recovery: 'uberACync:Sink|FifoDigRdClk'
 26. Slow 1200mV 85C Model Removal: 'uberACync:Sink|FifoDigRdClk'
 27. Slow 1200mV 85C Model Removal: 'uberACync:Sink|FifoAnaRdClk'
 28. Slow 1200mV 85C Model Removal: 'uberACync:Sink|FifoAnaWrClk'
 29. Slow 1200mV 85C Model Removal: 'uberACync:Sink|FifoDigWrClk'
 30. Slow 1200mV 85C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigWrClk'
 31. Slow 1200mV 85C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaRdClk'
 32. Slow 1200mV 85C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaWrClk'
 33. Slow 1200mV 85C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigRdClk'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'Clk100'
 35. Slow 1200mV 85C Model Minimum Pulse Width: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
 36. Setup Times
 37. Hold Times
 38. Clock to Output Times
 39. Minimum Clock to Output Times
 40. MTBF Summary
 41. Synchronizer Summary
 42. Synchronizer Chain #1: Worst-Case MTBF is Not Calculated
 43. Synchronizer Chain #2: Worst-Case MTBF is Not Calculated
 44. Synchronizer Chain #3: Worst-Case MTBF is Not Calculated
 45. Synchronizer Chain #4: Worst-Case MTBF is Not Calculated
 46. Synchronizer Chain #5: Worst-Case MTBF is Not Calculated
 47. Synchronizer Chain #6: Worst-Case MTBF is Not Calculated
 48. Synchronizer Chain #7: Worst-Case MTBF is Not Calculated
 49. Synchronizer Chain #8: Worst-Case MTBF is Not Calculated
 50. Synchronizer Chain #9: Worst-Case MTBF is Not Calculated
 51. Synchronizer Chain #10: Worst-Case MTBF is Not Calculated
 52. Synchronizer Chain #11: Worst-Case MTBF is Not Calculated
 53. Synchronizer Chain #12: Worst-Case MTBF is Not Calculated
 54. Synchronizer Chain #13: Worst-Case MTBF is Not Calculated
 55. Synchronizer Chain #14: Worst-Case MTBF is Not Calculated
 56. Synchronizer Chain #15: Worst-Case MTBF is Not Calculated
 57. Synchronizer Chain #16: Worst-Case MTBF is Not Calculated
 58. Synchronizer Chain #17: Worst-Case MTBF is Not Calculated
 59. Synchronizer Chain #18: Worst-Case MTBF is Not Calculated
 60. Synchronizer Chain #19: Worst-Case MTBF is Not Calculated
 61. Synchronizer Chain #20: Worst-Case MTBF is Not Calculated
 62. Synchronizer Chain #21: Worst-Case MTBF is Not Calculated
 63. Synchronizer Chain #22: Worst-Case MTBF is Not Calculated
 64. Synchronizer Chain #23: Worst-Case MTBF is Not Calculated
 65. Synchronizer Chain #24: Worst-Case MTBF is Not Calculated
 66. Synchronizer Chain #25: Worst-Case MTBF is Not Calculated
 67. Synchronizer Chain #26: Worst-Case MTBF is Not Calculated
 68. Synchronizer Chain #27: Worst-Case MTBF is Not Calculated
 69. Synchronizer Chain #28: Worst-Case MTBF is Not Calculated
 70. Synchronizer Chain #29: Worst-Case MTBF is Not Calculated
 71. Synchronizer Chain #30: Worst-Case MTBF is Not Calculated
 72. Synchronizer Chain #31: Worst-Case MTBF is Not Calculated
 73. Synchronizer Chain #32: Worst-Case MTBF is Not Calculated
 74. Synchronizer Chain #33: Worst-Case MTBF is Not Calculated
 75. Synchronizer Chain #34: Worst-Case MTBF is Not Calculated
 76. Synchronizer Chain #35: Worst-Case MTBF is Not Calculated
 77. Synchronizer Chain #36: Worst-Case MTBF is Not Calculated
 78. Synchronizer Chain #37: Worst-Case MTBF is Not Calculated
 79. Synchronizer Chain #38: Worst-Case MTBF is Not Calculated
 80. Synchronizer Chain #39: Worst-Case MTBF is Not Calculated
 81. Synchronizer Chain #40: Worst-Case MTBF is Not Calculated
 82. Synchronizer Chain #41: Worst-Case MTBF is Not Calculated
 83. Synchronizer Chain #42: Worst-Case MTBF is Not Calculated
 84. Synchronizer Chain #43: Worst-Case MTBF is Not Calculated
 85. Synchronizer Chain #44: Worst-Case MTBF is Not Calculated
 86. Synchronizer Chain #45: Worst-Case MTBF is Not Calculated
 87. Synchronizer Chain #46: Worst-Case MTBF is Not Calculated
 88. Synchronizer Chain #47: Worst-Case MTBF is Not Calculated
 89. Synchronizer Chain #48: Worst-Case MTBF is Not Calculated
 90. Synchronizer Chain #49: Worst-Case MTBF is Not Calculated
 91. Synchronizer Chain #50: Worst-Case MTBF is Not Calculated
 92. Synchronizer Chain #51: Worst-Case MTBF is Not Calculated
 93. Synchronizer Chain #52: Worst-Case MTBF is Not Calculated
 94. Synchronizer Chain #53: Worst-Case MTBF is Not Calculated
 95. Synchronizer Chain #54: Worst-Case MTBF is Not Calculated
 96. Synchronizer Chain #55: Worst-Case MTBF is Not Calculated
 97. Synchronizer Chain #56: Worst-Case MTBF is Not Calculated
 98. Synchronizer Chain #57: Worst-Case MTBF is Not Calculated
 99. Synchronizer Chain #58: Worst-Case MTBF is Not Calculated
100. Synchronizer Chain #59: Worst-Case MTBF is Not Calculated
101. Synchronizer Chain #60: Worst-Case MTBF is Not Calculated
102. Synchronizer Chain #61: Worst-Case MTBF is Not Calculated
103. Synchronizer Chain #62: Worst-Case MTBF is Not Calculated
104. Slow 1200mV 0C Model Fmax Summary
105. Slow 1200mV 0C Model Setup Summary
106. Slow 1200mV 0C Model Hold Summary
107. Slow 1200mV 0C Model Recovery Summary
108. Slow 1200mV 0C Model Removal Summary
109. Slow 1200mV 0C Model Minimum Pulse Width Summary
110. Slow 1200mV 0C Model Setup: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
111. Slow 1200mV 0C Model Setup: 'uberACync:Sink|FifoDigWrClk'
112. Slow 1200mV 0C Model Setup: 'uberACync:Sink|FifoAnaWrClk'
113. Slow 1200mV 0C Model Setup: 'uberACync:Sink|FifoDigRdClk'
114. Slow 1200mV 0C Model Setup: 'uberACync:Sink|FifoAnaRdClk'
115. Slow 1200mV 0C Model Hold: 'uberACync:Sink|FifoAnaWrClk'
116. Slow 1200mV 0C Model Hold: 'uberACync:Sink|FifoDigRdClk'
117. Slow 1200mV 0C Model Hold: 'uberACync:Sink|FifoDigWrClk'
118. Slow 1200mV 0C Model Hold: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
119. Slow 1200mV 0C Model Hold: 'uberACync:Sink|FifoAnaRdClk'
120. Slow 1200mV 0C Model Recovery: 'uberACync:Sink|FifoDigWrClk'
121. Slow 1200mV 0C Model Recovery: 'uberACync:Sink|FifoAnaRdClk'
122. Slow 1200mV 0C Model Recovery: 'uberACync:Sink|FifoAnaWrClk'
123. Slow 1200mV 0C Model Recovery: 'uberACync:Sink|FifoDigRdClk'
124. Slow 1200mV 0C Model Removal: 'uberACync:Sink|FifoDigRdClk'
125. Slow 1200mV 0C Model Removal: 'uberACync:Sink|FifoAnaRdClk'
126. Slow 1200mV 0C Model Removal: 'uberACync:Sink|FifoAnaWrClk'
127. Slow 1200mV 0C Model Removal: 'uberACync:Sink|FifoDigWrClk'
128. Slow 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigWrClk'
129. Slow 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaRdClk'
130. Slow 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaWrClk'
131. Slow 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigRdClk'
132. Slow 1200mV 0C Model Minimum Pulse Width: 'Clk100'
133. Slow 1200mV 0C Model Minimum Pulse Width: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
134. Setup Times
135. Hold Times
136. Clock to Output Times
137. Minimum Clock to Output Times
138. MTBF Summary
139. Synchronizer Summary
140. Synchronizer Chain #1: Worst-Case MTBF is Not Calculated
141. Synchronizer Chain #2: Worst-Case MTBF is Not Calculated
142. Synchronizer Chain #3: Worst-Case MTBF is Not Calculated
143. Synchronizer Chain #4: Worst-Case MTBF is Not Calculated
144. Synchronizer Chain #5: Worst-Case MTBF is Not Calculated
145. Synchronizer Chain #6: Worst-Case MTBF is Not Calculated
146. Synchronizer Chain #7: Worst-Case MTBF is Not Calculated
147. Synchronizer Chain #8: Worst-Case MTBF is Not Calculated
148. Synchronizer Chain #9: Worst-Case MTBF is Not Calculated
149. Synchronizer Chain #10: Worst-Case MTBF is Not Calculated
150. Synchronizer Chain #11: Worst-Case MTBF is Not Calculated
151. Synchronizer Chain #12: Worst-Case MTBF is Not Calculated
152. Synchronizer Chain #13: Worst-Case MTBF is Not Calculated
153. Synchronizer Chain #14: Worst-Case MTBF is Not Calculated
154. Synchronizer Chain #15: Worst-Case MTBF is Not Calculated
155. Synchronizer Chain #16: Worst-Case MTBF is Not Calculated
156. Synchronizer Chain #17: Worst-Case MTBF is Not Calculated
157. Synchronizer Chain #18: Worst-Case MTBF is Not Calculated
158. Synchronizer Chain #19: Worst-Case MTBF is Not Calculated
159. Synchronizer Chain #20: Worst-Case MTBF is Not Calculated
160. Synchronizer Chain #21: Worst-Case MTBF is Not Calculated
161. Synchronizer Chain #22: Worst-Case MTBF is Not Calculated
162. Synchronizer Chain #23: Worst-Case MTBF is Not Calculated
163. Synchronizer Chain #24: Worst-Case MTBF is Not Calculated
164. Synchronizer Chain #25: Worst-Case MTBF is Not Calculated
165. Synchronizer Chain #26: Worst-Case MTBF is Not Calculated
166. Synchronizer Chain #27: Worst-Case MTBF is Not Calculated
167. Synchronizer Chain #28: Worst-Case MTBF is Not Calculated
168. Synchronizer Chain #29: Worst-Case MTBF is Not Calculated
169. Synchronizer Chain #30: Worst-Case MTBF is Not Calculated
170. Synchronizer Chain #31: Worst-Case MTBF is Not Calculated
171. Synchronizer Chain #32: Worst-Case MTBF is Not Calculated
172. Synchronizer Chain #33: Worst-Case MTBF is Not Calculated
173. Synchronizer Chain #34: Worst-Case MTBF is Not Calculated
174. Synchronizer Chain #35: Worst-Case MTBF is Not Calculated
175. Synchronizer Chain #36: Worst-Case MTBF is Not Calculated
176. Synchronizer Chain #37: Worst-Case MTBF is Not Calculated
177. Synchronizer Chain #38: Worst-Case MTBF is Not Calculated
178. Synchronizer Chain #39: Worst-Case MTBF is Not Calculated
179. Synchronizer Chain #40: Worst-Case MTBF is Not Calculated
180. Synchronizer Chain #41: Worst-Case MTBF is Not Calculated
181. Synchronizer Chain #42: Worst-Case MTBF is Not Calculated
182. Synchronizer Chain #43: Worst-Case MTBF is Not Calculated
183. Synchronizer Chain #44: Worst-Case MTBF is Not Calculated
184. Synchronizer Chain #45: Worst-Case MTBF is Not Calculated
185. Synchronizer Chain #46: Worst-Case MTBF is Not Calculated
186. Synchronizer Chain #47: Worst-Case MTBF is Not Calculated
187. Synchronizer Chain #48: Worst-Case MTBF is Not Calculated
188. Synchronizer Chain #49: Worst-Case MTBF is Not Calculated
189. Synchronizer Chain #50: Worst-Case MTBF is Not Calculated
190. Synchronizer Chain #51: Worst-Case MTBF is Not Calculated
191. Synchronizer Chain #52: Worst-Case MTBF is Not Calculated
192. Synchronizer Chain #53: Worst-Case MTBF is Not Calculated
193. Synchronizer Chain #54: Worst-Case MTBF is Not Calculated
194. Synchronizer Chain #55: Worst-Case MTBF is Not Calculated
195. Synchronizer Chain #56: Worst-Case MTBF is Not Calculated
196. Synchronizer Chain #57: Worst-Case MTBF is Not Calculated
197. Synchronizer Chain #58: Worst-Case MTBF is Not Calculated
198. Synchronizer Chain #59: Worst-Case MTBF is Not Calculated
199. Synchronizer Chain #60: Worst-Case MTBF is Not Calculated
200. Synchronizer Chain #61: Worst-Case MTBF is Not Calculated
201. Synchronizer Chain #62: Worst-Case MTBF is Not Calculated
202. Fast 1200mV 0C Model Setup Summary
203. Fast 1200mV 0C Model Hold Summary
204. Fast 1200mV 0C Model Recovery Summary
205. Fast 1200mV 0C Model Removal Summary
206. Fast 1200mV 0C Model Minimum Pulse Width Summary
207. Fast 1200mV 0C Model Setup: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
208. Fast 1200mV 0C Model Setup: 'uberACync:Sink|FifoDigWrClk'
209. Fast 1200mV 0C Model Setup: 'uberACync:Sink|FifoAnaWrClk'
210. Fast 1200mV 0C Model Setup: 'uberACync:Sink|FifoDigRdClk'
211. Fast 1200mV 0C Model Setup: 'uberACync:Sink|FifoAnaRdClk'
212. Fast 1200mV 0C Model Hold: 'uberACync:Sink|FifoDigRdClk'
213. Fast 1200mV 0C Model Hold: 'uberACync:Sink|FifoAnaWrClk'
214. Fast 1200mV 0C Model Hold: 'uberACync:Sink|FifoDigWrClk'
215. Fast 1200mV 0C Model Hold: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
216. Fast 1200mV 0C Model Hold: 'uberACync:Sink|FifoAnaRdClk'
217. Fast 1200mV 0C Model Recovery: 'uberACync:Sink|FifoDigWrClk'
218. Fast 1200mV 0C Model Recovery: 'uberACync:Sink|FifoAnaRdClk'
219. Fast 1200mV 0C Model Recovery: 'uberACync:Sink|FifoAnaWrClk'
220. Fast 1200mV 0C Model Recovery: 'uberACync:Sink|FifoDigRdClk'
221. Fast 1200mV 0C Model Removal: 'uberACync:Sink|FifoDigRdClk'
222. Fast 1200mV 0C Model Removal: 'uberACync:Sink|FifoAnaRdClk'
223. Fast 1200mV 0C Model Removal: 'uberACync:Sink|FifoAnaWrClk'
224. Fast 1200mV 0C Model Removal: 'uberACync:Sink|FifoDigWrClk'
225. Fast 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigWrClk'
226. Fast 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaRdClk'
227. Fast 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaWrClk'
228. Fast 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigRdClk'
229. Fast 1200mV 0C Model Minimum Pulse Width: 'Clk100'
230. Fast 1200mV 0C Model Minimum Pulse Width: '60MHz|altpll_component|auto_generated|pll1|clk[0]'
231. Setup Times
232. Hold Times
233. Clock to Output Times
234. Minimum Clock to Output Times
235. MTBF Summary
236. Synchronizer Summary
237. Synchronizer Chain #1: Worst-Case MTBF is Not Calculated
238. Synchronizer Chain #2: Worst-Case MTBF is Not Calculated
239. Synchronizer Chain #3: Worst-Case MTBF is Not Calculated
240. Synchronizer Chain #4: Worst-Case MTBF is Not Calculated
241. Synchronizer Chain #5: Worst-Case MTBF is Not Calculated
242. Synchronizer Chain #6: Worst-Case MTBF is Not Calculated
243. Synchronizer Chain #7: Worst-Case MTBF is Not Calculated
244. Synchronizer Chain #8: Worst-Case MTBF is Not Calculated
245. Synchronizer Chain #9: Worst-Case MTBF is Not Calculated
246. Synchronizer Chain #10: Worst-Case MTBF is Not Calculated
247. Synchronizer Chain #11: Worst-Case MTBF is Not Calculated
248. Synchronizer Chain #12: Worst-Case MTBF is Not Calculated
249. Synchronizer Chain #13: Worst-Case MTBF is Not Calculated
250. Synchronizer Chain #14: Worst-Case MTBF is Not Calculated
251. Synchronizer Chain #15: Worst-Case MTBF is Not Calculated
252. Synchronizer Chain #16: Worst-Case MTBF is Not Calculated
253. Synchronizer Chain #17: Worst-Case MTBF is Not Calculated
254. Synchronizer Chain #18: Worst-Case MTBF is Not Calculated
255. Synchronizer Chain #19: Worst-Case MTBF is Not Calculated
256. Synchronizer Chain #20: Worst-Case MTBF is Not Calculated
257. Synchronizer Chain #21: Worst-Case MTBF is Not Calculated
258. Synchronizer Chain #22: Worst-Case MTBF is Not Calculated
259. Synchronizer Chain #23: Worst-Case MTBF is Not Calculated
260. Synchronizer Chain #24: Worst-Case MTBF is Not Calculated
261. Synchronizer Chain #25: Worst-Case MTBF is Not Calculated
262. Synchronizer Chain #26: Worst-Case MTBF is Not Calculated
263. Synchronizer Chain #27: Worst-Case MTBF is Not Calculated
264. Synchronizer Chain #28: Worst-Case MTBF is Not Calculated
265. Synchronizer Chain #29: Worst-Case MTBF is Not Calculated
266. Synchronizer Chain #30: Worst-Case MTBF is Not Calculated
267. Synchronizer Chain #31: Worst-Case MTBF is Not Calculated
268. Synchronizer Chain #32: Worst-Case MTBF is Not Calculated
269. Synchronizer Chain #33: Worst-Case MTBF is Not Calculated
270. Synchronizer Chain #34: Worst-Case MTBF is Not Calculated
271. Synchronizer Chain #35: Worst-Case MTBF is Not Calculated
272. Synchronizer Chain #36: Worst-Case MTBF is Not Calculated
273. Synchronizer Chain #37: Worst-Case MTBF is Not Calculated
274. Synchronizer Chain #38: Worst-Case MTBF is Not Calculated
275. Synchronizer Chain #39: Worst-Case MTBF is Not Calculated
276. Synchronizer Chain #40: Worst-Case MTBF is Not Calculated
277. Synchronizer Chain #41: Worst-Case MTBF is Not Calculated
278. Synchronizer Chain #42: Worst-Case MTBF is Not Calculated
279. Synchronizer Chain #43: Worst-Case MTBF is Not Calculated
280. Synchronizer Chain #44: Worst-Case MTBF is Not Calculated
281. Synchronizer Chain #45: Worst-Case MTBF is Not Calculated
282. Synchronizer Chain #46: Worst-Case MTBF is Not Calculated
283. Synchronizer Chain #47: Worst-Case MTBF is Not Calculated
284. Synchronizer Chain #48: Worst-Case MTBF is Not Calculated
285. Synchronizer Chain #49: Worst-Case MTBF is Not Calculated
286. Synchronizer Chain #50: Worst-Case MTBF is Not Calculated
287. Synchronizer Chain #51: Worst-Case MTBF is Not Calculated
288. Synchronizer Chain #52: Worst-Case MTBF is Not Calculated
289. Synchronizer Chain #53: Worst-Case MTBF is Not Calculated
290. Synchronizer Chain #54: Worst-Case MTBF is Not Calculated
291. Synchronizer Chain #55: Worst-Case MTBF is Not Calculated
292. Synchronizer Chain #56: Worst-Case MTBF is Not Calculated
293. Synchronizer Chain #57: Worst-Case MTBF is Not Calculated
294. Synchronizer Chain #58: Worst-Case MTBF is Not Calculated
295. Synchronizer Chain #59: Worst-Case MTBF is Not Calculated
296. Synchronizer Chain #60: Worst-Case MTBF is Not Calculated
297. Synchronizer Chain #61: Worst-Case MTBF is Not Calculated
298. Synchronizer Chain #62: Worst-Case MTBF is Not Calculated
299. Multicorner Timing Analysis Summary
300. Setup Times
301. Hold Times
302. Clock to Output Times
303. Minimum Clock to Output Times
304. Board Trace Model Assignments
305. Input Transition Times
306. Signal Integrity Metrics (Slow 1200mv 0c Model)
307. Signal Integrity Metrics (Slow 1200mv 85c Model)
308. Signal Integrity Metrics (Fast 1200mv 0c Model)
309. Setup Transfers
310. Hold Transfers
311. Recovery Transfers
312. Removal Transfers
313. Report TCCS
314. Report RSKM
315. Unconstrained Paths
316. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                        ;
+--------------------+-----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name      ; ACync                                               ;
; Device Family      ; Cyclone IV E                                        ;
; Device Name        ; EP4CE22E22C8                                        ;
; Timing Models      ; Final                                               ;
; Delay Model        ; Combined                                            ;
; Rise/Fall Delays   ; Enabled                                             ;
+--------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ; < 0.1%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                 ;
+---------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+
; Clock Name                                        ; Type      ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source                                              ; Targets                                               ;
+---------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 16.666 ; 60.0 MHz   ; 0.000 ; 8.333 ; 50.00      ; 5         ; 3           ;       ;        ;           ;            ; false    ; Clk100 ; 60MHz|altpll_component|auto_generated|pll1|inclk[0] ; { 60MHz|altpll_component|auto_generated|pll1|clk[0] } ;
; Clk100                                            ; Base      ; 10.000 ; 100.0 MHz  ; 0.000 ; 5.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                     ; { Clk100 }                                            ;
; uberACync:Sink|FifoAnaRdClk                       ; Base      ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                     ; { uberACync:Sink|FifoAnaRdClk }                       ;
; uberACync:Sink|FifoAnaWrClk                       ; Base      ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                     ; { uberACync:Sink|FifoAnaWrClk }                       ;
; uberACync:Sink|FifoDigRdClk                       ; Base      ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                     ; { uberACync:Sink|FifoDigRdClk }                       ;
; uberACync:Sink|FifoDigWrClk                       ; Base      ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                     ; { uberACync:Sink|FifoDigWrClk }                       ;
+---------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                ;
+------------+-----------------+---------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                        ; Note                                           ;
+------------+-----------------+---------------------------------------------------+------------------------------------------------+
; 108.03 MHz ; 108.03 MHz      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 199.0 MHz  ; 199.0 MHz       ; uberACync:Sink|FifoDigRdClk                       ;                                                ;
; 213.08 MHz ; 213.08 MHz      ; uberACync:Sink|FifoDigWrClk                       ;                                                ;
; 231.27 MHz ; 231.27 MHz      ; uberACync:Sink|FifoAnaWrClk                       ;                                                ;
; 244.98 MHz ; 238.04 MHz      ; uberACync:Sink|FifoAnaRdClk                       ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+---------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
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+----------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                        ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; -8.006 ; -176.267      ;
; uberACync:Sink|FifoDigWrClk                       ; -6.764 ; -826.762      ;
; uberACync:Sink|FifoAnaWrClk                       ; -4.992 ; -594.061      ;
; uberACync:Sink|FifoDigRdClk                       ; -4.025 ; -276.811      ;
; uberACync:Sink|FifoAnaRdClk                       ; -3.082 ; -320.853      ;
+---------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                         ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; uberACync:Sink|FifoAnaWrClk                       ; -1.718 ; -50.989       ;
; uberACync:Sink|FifoDigWrClk                       ; -1.660 ; -47.267       ;
; uberACync:Sink|FifoDigRdClk                       ; -1.615 ; -3.230        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; -0.317 ; -0.942        ;
; uberACync:Sink|FifoAnaRdClk                       ; 0.455  ; 0.000         ;
+---------------------------------------------------+--------+---------------+


+------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary               ;
+-----------------------------+--------+---------------+
; Clock                       ; Slack  ; End Point TNS ;
+-----------------------------+--------+---------------+
; uberACync:Sink|FifoDigWrClk ; -1.066 ; -92.692       ;
; uberACync:Sink|FifoAnaRdClk ; -0.942 ; -133.263      ;
; uberACync:Sink|FifoAnaWrClk ; -0.628 ; -45.200       ;
; uberACync:Sink|FifoDigRdClk ; -0.197 ; -9.346        ;
+-----------------------------+--------+---------------+


+------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                ;
+-----------------------------+--------+---------------+
; Clock                       ; Slack  ; End Point TNS ;
+-----------------------------+--------+---------------+
; uberACync:Sink|FifoDigRdClk ; -1.336 ; -200.249      ;
; uberACync:Sink|FifoAnaRdClk ; -0.552 ; -82.954       ;
; uberACync:Sink|FifoAnaWrClk ; -0.540 ; -38.795       ;
; uberACync:Sink|FifoDigWrClk ; -0.086 ; -7.331        ;
+-----------------------------+--------+---------------+


+----------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                          ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; uberACync:Sink|FifoDigWrClk                       ; -3.201 ; -436.665      ;
; uberACync:Sink|FifoAnaRdClk                       ; -3.201 ; -418.821      ;
; uberACync:Sink|FifoAnaWrClk                       ; -3.201 ; -414.360      ;
; uberACync:Sink|FifoDigRdClk                       ; -3.201 ; -347.616      ;
; Clk100                                            ; 4.851  ; 0.000         ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 8.025  ; 0.000         ;
+---------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                   ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                          ; To Node                   ; Launch Clock                ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+
; -8.006 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5        ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.566     ; 3.393      ;
; -7.905 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.563     ; 3.295      ;
; -7.857 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 3.547      ;
; -7.811 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.585     ; 3.179      ;
; -7.790 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7        ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.584     ; 3.159      ;
; -7.748 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17       ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.569     ; 3.132      ;
; -7.743 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0        ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.565     ; 3.131      ;
; -7.734 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 3.424      ;
; -7.734 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 3.424      ;
; -7.694 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.566     ; 3.081      ;
; -7.649 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 3.339      ;
; -7.637 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 3.327      ;
; -7.620 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.579     ; 2.994      ;
; -7.612 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.568     ; 2.997      ;
; -7.585 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1        ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.568     ; 2.970      ;
; -7.584 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 3.274      ;
; -7.576 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6        ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.571     ; 2.958      ;
; -7.562 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.587     ; 2.928      ;
; -7.559 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.583     ; 2.929      ;
; -7.557 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.577     ; 2.933      ;
; -7.530 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.586     ; 2.897      ;
; -7.527 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 3.217      ;
; -7.520 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4        ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.573     ; 2.900      ;
; -7.513 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.575     ; 2.891      ;
; -7.472 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25       ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.569     ; 2.856      ;
; -7.416 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.787     ; 3.582      ;
; -7.413 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.570     ; 2.796      ;
; -7.400 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.545      ;
; -7.397 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3        ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.574     ; 2.776      ;
; -7.382 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.787     ; 3.548      ;
; -7.375 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.566     ; 2.762      ;
; -7.341 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.576     ; 2.718      ;
; -7.335 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.576     ; 2.712      ;
; -7.330 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.581     ; 2.702      ;
; -7.305 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 2.995      ;
; -7.304 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 2.994      ;
; -7.302 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.263     ; 2.992      ;
; -7.297 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 3.451      ;
; -7.269 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16       ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.568     ; 2.654      ;
; -7.260 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.794     ; 3.419      ;
; -7.259 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.271     ; 2.941      ;
; -7.245 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.271     ; 2.927      ;
; -7.240 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9        ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.562     ; 2.631      ;
; -7.188 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8        ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.564     ; 2.577      ;
; -7.183 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                ; uberACync:Sink|DacDat[3]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.798     ; 3.338      ;
; -7.181 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.803     ; 3.331      ;
; -7.171 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.788     ; 3.336      ;
; -7.169 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.563     ; 2.559      ;
; -7.160 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.576     ; 2.537      ;
; -7.121 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.809     ; 3.265      ;
; -7.104 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24       ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.567     ; 2.490      ;
; -7.090 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.788     ; 3.255      ;
; -7.024 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.169      ;
; -6.966 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.568     ; 2.351      ;
; -6.966 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.791     ; 3.128      ;
; -6.963 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]               ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.108      ;
; -6.953 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]               ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.800     ; 3.106      ;
; -6.934 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2        ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.566     ; 2.321      ;
; -6.923 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.803     ; 3.073      ;
; -6.922 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.809     ; 3.066      ;
; -6.884 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.791     ; 3.046      ;
; -6.849 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]               ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.789     ; 3.013      ;
; -6.846 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.794     ; 3.005      ;
; -6.823 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.255     ; 2.521      ;
; -6.814 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.255     ; 2.512      ;
; -6.804 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.790     ; 2.967      ;
; -6.801 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.801     ; 2.953      ;
; -6.795 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.796     ; 2.952      ;
; -6.724 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.802     ; 2.875      ;
; -6.697 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 2.851      ;
; -6.677 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 2.831      ;
; -6.668 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.790     ; 2.831      ;
; -6.659 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.255     ; 2.357      ;
; -6.658 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]               ; uberACync:Sink|DacDat[13] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.793     ; 2.818      ;
; -6.655 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.255     ; 2.353      ;
; -6.645 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]               ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.792     ; 2.806      ;
; -6.635 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.791     ; 2.797      ;
; -6.631 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.790     ; 2.794      ;
; -6.631 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.796     ; 2.788      ;
; -6.612 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.788     ; 2.777      ;
; -6.542 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.801     ; 2.694      ;
; -6.534 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.790     ; 2.697      ;
; -6.520 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 2.674      ;
; -6.502 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.792     ; 2.663      ;
; -6.478 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]               ; uberACync:Sink|DacDat[6]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.807     ; 2.624      ;
; -6.476 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.788     ; 2.641      ;
; -6.474 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.793     ; 2.634      ;
; -6.471 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.802     ; 2.622      ;
; -6.460 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.791     ; 2.622      ;
; -6.458 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]               ; uberACync:Sink|DacDat[13] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.794     ; 2.617      ;
; -6.456 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.796     ; 2.613      ;
; -6.453 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 2.598      ;
; -6.410 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.786     ; 2.577      ;
; -6.324 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.786     ; 2.491      ;
; -6.308 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 2.462      ;
; -6.283 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.796     ; 2.440      ;
; -6.248 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]               ; uberACync:Sink|DacDat[6]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.807     ; 2.394      ;
; -6.245 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]               ; uberACync:Sink|DacDat[6]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.797     ; 2.401      ;
; -6.178 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]               ; uberACync:Sink|DacDat[11] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.789     ; 2.342      ;
; -6.167 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]               ; uberACync:Sink|DacDat[3]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.800     ; 2.320      ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                                                                         ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -6.764 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.821      ;
; -6.764 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.821      ;
; -6.764 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.821      ;
; -6.764 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.821      ;
; -6.763 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.827      ;
; -6.763 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.827      ;
; -6.756 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.813      ;
; -6.756 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.813      ;
; -6.755 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.819      ;
; -6.749 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.806      ;
; -6.749 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.806      ;
; -6.748 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.812      ;
; -6.746 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.801      ;
; -6.746 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.801      ;
; -6.746 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.801      ;
; -6.746 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.801      ;
; -6.745 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.986     ; 6.807      ;
; -6.745 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.986     ; 6.807      ;
; -6.738 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.793      ;
; -6.738 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.793      ;
; -6.737 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.986     ; 6.799      ;
; -6.731 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.786      ;
; -6.731 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.786      ;
; -6.730 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.986     ; 6.792      ;
; -6.728 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.788      ;
; -6.728 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.788      ;
; -6.728 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.788      ;
; -6.728 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.788      ;
; -6.727 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.981     ; 6.794      ;
; -6.727 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.981     ; 6.794      ;
; -6.720 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.780      ;
; -6.720 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.780      ;
; -6.719 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.981     ; 6.786      ;
; -6.713 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.773      ;
; -6.713 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.773      ;
; -6.712 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.981     ; 6.779      ;
; -6.708 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.765      ;
; -6.708 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.765      ;
; -6.707 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.771      ;
; -6.690 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.745      ;
; -6.690 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.745      ;
; -6.689 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.986     ; 6.751      ;
; -6.688 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.752      ;
; -6.688 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.752      ;
; -6.688 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.752      ;
; -6.688 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.752      ;
; -6.687 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.977     ; 6.758      ;
; -6.687 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.977     ; 6.758      ;
; -6.682 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.739      ;
; -6.682 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.739      ;
; -6.681 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.745      ;
; -6.680 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.744      ;
; -6.680 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.744      ;
; -6.679 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.977     ; 6.750      ;
; -6.674 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.731      ;
; -6.674 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.731      ;
; -6.673 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.737      ;
; -6.673 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.737      ;
; -6.672 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.729      ;
; -6.672 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.729      ;
; -6.672 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.736      ;
; -6.672 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.732      ;
; -6.672 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.732      ;
; -6.672 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.977     ; 6.743      ;
; -6.672 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.729      ;
; -6.672 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.729      ;
; -6.671 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.735      ;
; -6.671 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.981     ; 6.738      ;
; -6.671 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.735      ;
; -6.664 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.719      ;
; -6.664 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.719      ;
; -6.664 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.721      ;
; -6.664 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.721      ;
; -6.663 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.986     ; 6.725      ;
; -6.663 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.727      ;
; -6.660 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.715      ;
; -6.660 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.993     ; 6.715      ;
; -6.658 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.986     ; 6.720      ;
; -6.657 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.714      ;
; -6.657 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.714      ;
; -6.656 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.716      ;
; -6.656 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.716      ;
; -6.656 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.720      ;
; -6.654 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.981     ; 6.721      ;
; -6.649 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.706      ;
; -6.649 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.991     ; 6.706      ;
; -6.648 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.712      ;
; -6.648 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.712      ;
; -6.648 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.712      ;
; -6.648 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.712      ;
; -6.647 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.977     ; 6.718      ;
; -6.647 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.711      ;
; -6.647 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.977     ; 6.718      ;
; -6.646 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.706      ;
; -6.646 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.988     ; 6.706      ;
; -6.645 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.981     ; 6.712      ;
; -6.640 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.704      ;
; -6.640 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.984     ; 6.704      ;
; -6.639 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.977     ; 6.710      ;
; -6.637 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.981     ; 6.704      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                                                         ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                           ; To Node                                                                                                                        ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -4.992 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.225      ; 6.265      ;
; -4.992 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.225      ; 6.265      ;
; -4.990 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.232      ; 6.270      ;
; -4.989 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.225      ; 6.262      ;
; -4.989 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.225      ; 6.262      ;
; -4.987 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.232      ; 6.267      ;
; -4.954 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.225      ; 6.227      ;
; -4.954 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.225      ; 6.227      ;
; -4.952 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.232      ; 6.232      ;
; -4.933 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.225      ; 6.206      ;
; -4.933 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.225      ; 6.206      ;
; -4.931 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.232      ; 6.211      ;
; -4.918 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.222      ; 6.188      ;
; -4.918 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.222      ; 6.188      ;
; -4.916 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.193      ;
; -4.915 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.222      ; 6.185      ;
; -4.915 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.222      ; 6.185      ;
; -4.913 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.196      ;
; -4.913 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.196      ;
; -4.913 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.190      ;
; -4.912 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.231      ; 6.191      ;
; -4.912 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.231      ; 6.191      ;
; -4.911 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.242      ; 6.201      ;
; -4.910 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.238      ; 6.196      ;
; -4.910 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.193      ;
; -4.910 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.193      ;
; -4.909 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.231      ; 6.188      ;
; -4.909 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.231      ; 6.188      ;
; -4.908 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.242      ; 6.198      ;
; -4.907 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.238      ; 6.193      ;
; -4.898 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.175      ;
; -4.898 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.175      ;
; -4.896 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.236      ; 6.180      ;
; -4.895 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.172      ;
; -4.895 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.172      ;
; -4.893 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.236      ; 6.177      ;
; -4.892 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.227      ; 6.167      ;
; -4.892 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.227      ; 6.167      ;
; -4.890 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.234      ; 6.172      ;
; -4.889 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.227      ; 6.164      ;
; -4.889 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.227      ; 6.164      ;
; -4.887 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.234      ; 6.169      ;
; -4.887 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.234      ; 6.169      ;
; -4.887 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.234      ; 6.169      ;
; -4.885 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.241      ; 6.174      ;
; -4.884 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.234      ; 6.166      ;
; -4.884 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.234      ; 6.166      ;
; -4.882 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.241      ; 6.171      ;
; -4.880 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.222      ; 6.150      ;
; -4.880 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.222      ; 6.150      ;
; -4.878 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.230      ; 6.156      ;
; -4.878 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.230      ; 6.156      ;
; -4.878 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.155      ;
; -4.876 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.228      ; 6.152      ;
; -4.876 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.228      ; 6.152      ;
; -4.876 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.237      ; 6.161      ;
; -4.875 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.158      ;
; -4.875 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.158      ;
; -4.875 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.230      ; 6.153      ;
; -4.875 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.230      ; 6.153      ;
; -4.874 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.157      ;
; -4.874 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.231      ; 6.153      ;
; -4.874 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.231      ; 6.153      ;
; -4.873 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.242      ; 6.163      ;
; -4.873 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.228      ; 6.149      ;
; -4.873 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.228      ; 6.149      ;
; -4.873 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.237      ; 6.158      ;
; -4.872 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.238      ; 6.158      ;
; -4.871 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.232      ; 6.151      ;
; -4.871 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.232      ; 6.151      ;
; -4.871 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.154      ;
; -4.869 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.239      ; 6.156      ;
; -4.868 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.232      ; 6.148      ;
; -4.868 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.232      ; 6.148      ;
; -4.867 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.226      ; 6.141      ;
; -4.867 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.226      ; 6.141      ;
; -4.866 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.239      ; 6.153      ;
; -4.865 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.233      ; 6.146      ;
; -4.864 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.226      ; 6.138      ;
; -4.864 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.226      ; 6.138      ;
; -4.862 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.233      ; 6.143      ;
; -4.860 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.137      ;
; -4.860 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.137      ;
; -4.859 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.222      ; 6.129      ;
; -4.859 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.222      ; 6.129      ;
; -4.858 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.236      ; 6.142      ;
; -4.857 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.230      ; 6.135      ;
; -4.857 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.230      ; 6.135      ;
; -4.857 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.229      ; 6.134      ;
; -4.855 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.237      ; 6.140      ;
; -4.854 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.137      ;
; -4.854 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.235      ; 6.137      ;
; -4.854 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.227      ; 6.129      ;
; -4.854 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.227      ; 6.129      ;
; -4.853 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.231      ; 6.132      ;
; -4.853 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.231      ; 6.132      ;
; -4.852 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.226      ; 6.126      ;
; -4.852 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.226      ; 6.126      ;
; -4.852 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.242      ; 6.142      ;
; -4.852 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.234      ; 6.134      ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                                                                                                        ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                         ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -4.025 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.954      ;
; -3.875 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.804      ;
; -3.874 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.803      ;
; -3.726 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.656      ;
; -3.632 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.561      ;
; -3.582 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.507      ;
; -3.570 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.490      ;
; -3.534 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.459      ;
; -3.529 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.459      ;
; -3.506 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.436      ;
; -3.496 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.421      ;
; -3.493 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.413      ;
; -3.484 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.404      ;
; -3.453 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.373      ;
; -3.448 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.373      ;
; -3.443 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.368      ;
; -3.434 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.363      ;
; -3.411 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.331      ;
; -3.407 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.327      ;
; -3.393 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.313      ;
; -3.391 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.320      ;
; -3.381 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.301      ;
; -3.376 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.296      ;
; -3.357 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.277      ;
; -3.301 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.221      ;
; -3.295 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.215      ;
; -3.295 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.215      ;
; -3.290 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.210      ;
; -3.271 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.191      ;
; -3.264 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.193      ;
; -3.260 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.185      ;
; -3.241 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.166      ;
; -3.239 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.168      ;
; -3.209 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.129      ;
; -3.209 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.139      ;
; -3.190 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.115      ;
; -3.180 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.105      ;
; -3.156 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.212      ; 4.284      ;
; -3.155 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.080      ;
; -3.154 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.213      ; 4.283      ;
; -3.148 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.212      ; 4.276      ;
; -3.147 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.203      ; 4.266      ;
; -3.144 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.200      ; 4.260      ;
; -3.140 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.060      ;
; -3.135 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 4.055      ;
; -3.127 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.203      ; 4.246      ;
; -3.114 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.043      ;
; -3.104 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.029      ;
; -3.104 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.034      ;
; -3.076 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 4.001      ;
; -3.061 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.981      ;
; -3.058 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.987      ;
; -3.003 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.932      ;
; -2.987 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 3.912      ;
; -2.971 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.900      ;
; -2.923 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 3.848      ;
; -2.894 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.814      ;
; -2.869 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.789      ;
; -2.865 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 3.790      ;
; -2.861 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.781      ;
; -2.839 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.759      ;
; -2.833 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 3.758      ;
; -2.821 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.083     ; 3.739      ;
; -2.821 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.741      ;
; -2.787 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.210      ; 4.045      ;
; -2.787 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.707      ;
; -2.784 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.704      ;
; -2.775 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.231      ; 3.922      ;
; -2.769 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.197      ; 3.882      ;
; -2.757 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 3.687      ;
; -2.755 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.209      ; 3.880      ;
; -2.744 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.664      ;
; -2.743 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.200      ; 3.859      ;
; -2.742 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.210      ; 4.000      ;
; -2.739 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.668      ;
; -2.734 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.199      ; 3.849      ;
; -2.730 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.195      ; 3.841      ;
; -2.726 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 3.651      ;
; -2.720 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.211      ; 3.847      ;
; -2.717 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~portb_address_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.216      ; 3.981      ;
; -2.714 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.208      ; 3.838      ;
; -2.709 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.210      ; 3.967      ;
; -2.703 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.205      ; 3.824      ;
; -2.692 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.236      ; 3.976      ;
; -2.685 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.219      ; 3.952      ;
; -2.677 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.606      ;
; -2.671 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 3.596      ;
; -2.660 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.580      ;
; -2.630 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.076     ; 3.555      ;
; -2.627 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.220      ; 3.895      ;
; -2.612 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.081     ; 3.532      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~portb_address_reg0    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~portb_address_reg0   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~portb_address_reg0   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.051     ; 3.476      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                       ; To Node                                                                                                                        ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -3.082 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.075     ; 4.008      ;
; -3.069 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.075     ; 3.995      ;
; -2.869 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.075     ; 3.795      ;
; -2.863 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.229      ; 4.008      ;
; -2.863 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.229      ; 4.008      ;
; -2.851 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.222      ; 3.989      ;
; -2.851 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.222      ; 3.989      ;
; -2.838 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.230      ; 3.984      ;
; -2.838 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.230      ; 3.984      ;
; -2.825 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.222      ; 3.963      ;
; -2.825 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.222      ; 3.963      ;
; -2.820 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.219      ; 3.955      ;
; -2.820 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.219      ; 3.955      ;
; -2.819 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.224      ; 3.959      ;
; -2.819 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.224      ; 3.959      ;
; -2.808 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.224      ; 3.948      ;
; -2.808 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.224      ; 3.948      ;
; -2.793 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.226      ; 3.935      ;
; -2.793 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.226      ; 3.935      ;
; -2.779 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.079     ; 3.701      ;
; -2.769 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.226      ; 3.911      ;
; -2.769 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.226      ; 3.911      ;
; -2.760 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.229      ; 3.905      ;
; -2.760 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.229      ; 3.905      ;
; -2.755 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.229      ; 3.900      ;
; -2.755 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.229      ; 3.900      ;
; -2.751 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_msb_aeb                                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.079     ; 3.673      ;
; -2.734 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.075     ; 3.660      ;
; -2.728 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.228      ; 3.872      ;
; -2.728 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.228      ; 3.872      ;
; -2.694 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.219      ; 3.829      ;
; -2.694 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.219      ; 3.829      ;
; -2.687 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.075     ; 3.613      ;
; -2.674 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.075     ; 3.600      ;
; -2.671 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.081     ; 3.591      ;
; -2.668 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.219      ; 3.803      ;
; -2.668 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.219      ; 3.803      ;
; -2.663 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.235      ; 3.946      ;
; -2.659 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.228      ; 3.803      ;
; -2.659 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.228      ; 3.803      ;
; -2.641 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.080     ; 3.562      ;
; -2.636 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.214      ; 3.766      ;
; -2.636 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.214      ; 3.766      ;
; -2.632 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.080     ; 3.553      ;
; -2.626 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.220      ; 3.762      ;
; -2.626 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.220      ; 3.762      ;
; -2.623 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.080     ; 3.544      ;
; -2.614 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.220      ; 3.750      ;
; -2.614 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.220      ; 3.750      ;
; -2.613 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.230      ; 3.891      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[11]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[43]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[27]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[23]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[6]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[4]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[51]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
; -2.611 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.051     ; 3.476      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                                                                                                                               ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.718 ; uberACync:Sink|FifoOutAna[19]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.871      ; 2.477      ;
; -1.686 ; uberACync:Sink|FifoOutAna[35]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.871      ; 2.509      ;
; -1.680 ; uberACync:Sink|FifoOutAna[21]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.874      ; 2.518      ;
; -1.673 ; uberACync:Sink|FifoOutAna[6]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.867      ; 2.518      ;
; -1.663 ; uberACync:Sink|FifoOutAna[22]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.879      ; 2.540      ;
; -1.661 ; uberACync:Sink|FifoOutAna[34]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.866      ; 2.529      ;
; -1.658 ; uberACync:Sink|FifoOutAna[37]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.874      ; 2.540      ;
; -1.653 ; uberACync:Sink|FifoOutAna[49]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.879      ; 2.550      ;
; -1.652 ; uberACync:Sink|FifoOutAna[17]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.871      ; 2.543      ;
; -1.652 ; uberACync:Sink|FifoOutAna[33]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.871      ; 2.543      ;
; -1.647 ; uberACync:Sink|FifoOutAna[40]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.878      ; 2.555      ;
; -1.645 ; uberACync:Sink|FifoOutAna[39]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.547      ;
; -1.639 ; uberACync:Sink|FifoOutAna[7]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.870      ; 2.555      ;
; -1.634 ; uberACync:Sink|FifoOutAna[11]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.867      ; 2.557      ;
; -1.631 ; uberACync:Sink|FifoOutAna[8]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.876      ; 2.569      ;
; -1.625 ; uberACync:Sink|FifoOutAna[23]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.567      ;
; -1.624 ; uberACync:Sink|FifoOutAna[4]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.871      ; 2.571      ;
; -1.623 ; uberACync:Sink|FifoOutAna[46]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.855      ; 2.556      ;
; -1.619 ; uberACync:Sink|FifoOutAna[56]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.876      ; 2.581      ;
; -1.618 ; uberACync:Sink|FifoOutAna[55]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.870      ; 2.576      ;
; -1.616 ; uberACync:Sink|FifoOutAna[25]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.881      ; 2.589      ;
; -1.607 ; uberACync:Sink|FifoOutAna[1]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.879      ; 2.596      ;
; -1.606 ; uberACync:Sink|FifoOutAna[43]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.586      ;
; -1.603 ; uberACync:Sink|FifoOutAna[32]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.885      ; 2.606      ;
; -1.602 ; uberACync:Sink|FifoOutAna[12]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.884      ; 2.606      ;
; -1.601 ; uberACync:Sink|FifoOutAna[26]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.871      ; 2.594      ;
; -1.600 ; uberACync:Sink|FifoOutAna[42]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.871      ; 2.595      ;
; -1.597 ; uberACync:Sink|FifoOutAna[38]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.879      ; 2.606      ;
; -1.593 ; uberACync:Sink|FifoOutAna[14]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.872      ; 2.603      ;
; -1.591 ; uberACync:Sink|FifoOutAna[15]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.601      ;
; -1.589 ; uberACync:Sink|FifoOutAna[52]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.866      ; 2.601      ;
; -1.585 ; uberACync:Sink|FifoOutAna[63]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.607      ;
; -1.583 ; uberACync:Sink|FifoOutAna[54]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.867      ; 2.608      ;
; -1.580 ; uberACync:Sink|FifoOutAna[62]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.872      ; 2.616      ;
; -1.574 ; uberACync:Sink|FifoOutAna[58]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.865      ; 2.615      ;
; -1.572 ; uberACync:Sink|FifoOutAna[16]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.885      ; 2.637      ;
; -1.570 ; uberACync:Sink|FifoOutAna[59]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.867      ; 2.621      ;
; -1.568 ; uberACync:Sink|FifoOutAna[27]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.624      ;
; -1.564 ; uberACync:Sink|FifoOutAna[2]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.870      ; 2.630      ;
; -1.564 ; uberACync:Sink|FifoOutAna[45]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.628      ;
; -1.562 ; uberACync:Sink|FifoOutAna[10]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.865      ; 2.627      ;
; -1.561 ; uberACync:Sink|FifoOutAna[51]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.867      ; 2.630      ;
; -1.558 ; uberACync:Sink|FifoOutAna[24]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.878      ; 2.644      ;
; -1.557 ; uberACync:Sink|FifoOutAna[3]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.867      ; 2.634      ;
; -1.530 ; uberACync:Sink|FifoOutAna[20]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.662      ;
; -1.524 ; uberACync:Sink|FifoOutAna[30]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.855      ; 2.655      ;
; -1.521 ; uberACync:Sink|FifoOutAna[31]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.858      ; 2.661      ;
; -1.516 ; uberACync:Sink|FifoOutAna[61]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.867      ; 2.675      ;
; -1.510 ; uberACync:Sink|FifoOutAna[18]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.866      ; 2.680      ;
; -1.508 ; uberACync:Sink|FifoOutAna[53]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.873      ; 2.689      ;
; -1.506 ; uberACync:Sink|FifoOutAna[5]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.873      ; 2.691      ;
; -1.499 ; uberACync:Sink|FifoOutAna[29]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.693      ;
; -1.497 ; uberACync:Sink|FifoOutAna[60]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.884      ; 2.711      ;
; -1.491 ; uberACync:Sink|FifoOutAna[41]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.881      ; 2.714      ;
; -1.485 ; uberACync:Sink|FifoOutAna[36]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.868      ; 2.707      ;
; -1.480 ; uberACync:Sink|FifoOutAna[57]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.870      ; 2.714      ;
; -1.479 ; uberACync:Sink|FifoOutAna[50]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.870      ; 2.715      ;
; -1.473 ; uberACync:Sink|FifoOutAna[13]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.867      ; 2.718      ;
; -1.428 ; uberACync:Sink|FifoOutAna[48]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.872      ; 2.768      ;
; -1.396 ; uberACync:Sink|FifoOutAna[47]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.858      ; 2.786      ;
; -1.388 ; uberACync:Sink|FifoOutAna[28]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.861      ; 2.797      ;
; -1.375 ; uberACync:Sink|FifoOutAna[0]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.872      ; 2.821      ;
; -1.341 ; uberACync:Sink|FifoOutAna[44]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.861      ; 2.844      ;
; -1.222 ; uberACync:Sink|FifoOutAna[9]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.870      ; 2.972      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.486  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.777      ;
; 0.502  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.793      ;
; 0.504  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.795      ;
; 0.504  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.795      ;
; 0.504  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.795      ;
; 0.505  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.796      ;
; 0.529  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.820      ;
; 0.627  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.918      ;
; 0.644  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.935      ;
; 0.679  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.970      ;
; 0.700  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.991      ;
; 0.701  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.992      ;
; 0.702  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.993      ;
; 0.703  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 0.994      ;
; 0.709  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 1.000      ;
; 0.723  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 1.014      ;
; 0.749  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 1.040      ;
; 0.755  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 1.046      ;
; 0.770  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.079      ; 1.061      ;
; 0.787  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.476      ; 1.517      ;
; 0.792  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.477      ; 1.523      ;
; 0.801  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.478      ; 1.533      ;
; 0.801  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.479      ; 1.534      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.660 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.404      ; 2.068      ;
; -1.658 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.414      ; 2.080      ;
; -1.642 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.412      ; 2.094      ;
; -1.633 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.413      ; 2.104      ;
; -1.621 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.413      ; 2.116      ;
; -1.570 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.429      ; 2.183      ;
; -1.568 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.418      ; 2.174      ;
; -1.565 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.415      ; 2.174      ;
; -1.556 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.415      ; 2.183      ;
; -1.546 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.411      ; 2.189      ;
; -1.533 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.415      ; 2.206      ;
; -1.521 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.421      ; 2.224      ;
; -1.519 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.424      ; 2.229      ;
; -1.518 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.415      ; 2.221      ;
; -1.517 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.431      ; 2.238      ;
; -1.505 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.406      ; 2.225      ;
; -1.472 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.410      ; 2.262      ;
; -1.468 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.423      ; 2.279      ;
; -1.463 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.422      ; 2.283      ;
; -1.457 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.419      ; 2.286      ;
; -1.438 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.419      ; 2.305      ;
; -1.433 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.421      ; 2.312      ;
; -1.427 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.423      ; 2.320      ;
; -1.413 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.413      ; 2.324      ;
; -1.382 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.428      ; 2.370      ;
; -1.367 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.402      ; 2.359      ;
; -1.361 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.426      ; 2.389      ;
; -1.351 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.410      ; 2.383      ;
; -1.318 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.408      ; 2.414      ;
; -1.315 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.413      ; 2.422      ;
; -1.249 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.414      ; 2.489      ;
; -1.221 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.413      ; 2.516      ;
; 0.405  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.130      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.455  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.490  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.215      ;
; 0.501  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.793      ;
; 0.502  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.227      ;
; 0.502  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.794      ;
; 0.502  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.794      ;
; 0.502  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.794      ;
; 0.503  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.228      ;
; 0.503  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.795      ;
; 0.505  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.796      ;
; 0.529  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.821      ;
; 0.537  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.262      ;
; 0.544  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.835      ;
; 0.628  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.920      ;
; 0.650  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.942      ;
; 0.676  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.967      ;
; 0.687  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.979      ;
; 0.691  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.982      ;
; 0.696  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.988      ;
; 0.699  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 0.991      ;
; 0.700  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.991      ;
; 0.701  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.992      ;
; 0.703  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 0.994      ;
; 0.704  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.479      ; 1.437      ;
; 0.714  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.439      ;
; 0.731  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 1.022      ;
; 0.741  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.033      ;
; 0.742  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.477      ; 1.473      ;
; 0.746  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.471      ;
; 0.750  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.480      ; 1.484      ;
; 0.753  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.480      ; 1.487      ;
; 0.760  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.479      ; 1.493      ;
; 0.763  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.055      ;
; 0.768  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.480      ; 1.502      ;
; 0.768  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.060      ;
; 0.772  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.476      ; 1.502      ;
; 0.773  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.479      ; 1.506      ;
; 0.777  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 1.068      ;
; 0.783  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.075      ;
; 0.783  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.075      ;
; 0.784  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.509      ;
; 0.786  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.078      ;
; 0.789  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.081      ;
; 0.791  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.083      ;
; 0.793  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.464      ; 1.511      ;
; 0.794  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.471      ; 1.519      ;
; 0.796  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.474      ; 1.524      ;
; 0.798  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.090      ;
; 0.798  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.079      ; 1.089      ;
; 0.799  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.091      ;
; 0.806  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.080      ; 1.098      ;
; 0.808  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.477      ; 1.539      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.615 ; uberACync:Sink|FifosClear                                                                                                         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 2.931      ;
; -1.615 ; uberACync:Sink|FifosClear                                                                                                         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 2.931      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.746      ;
; 0.488  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.781      ;
; 0.490  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.783      ;
; 0.501  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.793      ;
; 0.502  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.795      ;
; 0.572  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.395      ; 1.221      ;
; 0.579  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.395      ; 1.228      ;
; 0.580  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.395      ; 1.229      ;
; 0.586  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.395      ; 1.235      ;
; 0.614  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.395      ; 1.263      ;
; 0.625  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.397      ; 1.276      ;
; 0.652  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.395      ; 1.301      ;
; 0.700  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 0.992      ;
; 0.700  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.993      ;
; 0.701  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.994      ;
; 0.706  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 0.999      ;
; 0.731  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.024      ;
; 0.734  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.026      ;
; 0.740  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.032      ;
; 0.743  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.036      ;
; 0.744  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.037      ;
; 0.746  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.039      ;
; 0.751  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.044      ;
; 0.764  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.057      ;
; 0.769  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.061      ;
; 0.783  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.076      ;
; 0.786  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.079      ;
; 0.792  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.084      ;
; 0.794  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.402      ; 1.450      ;
; 0.800  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.093      ;
; 0.806  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.099      ;
; 0.808  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.101      ;
; 0.808  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.101      ;
; 0.810  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.103      ;
; 0.810  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.103      ;
; 0.818  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.110      ;
; 0.828  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.120      ;
; 0.855  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.148      ;
; 0.891  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.390      ; 1.535      ;
; 0.905  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.197      ;
; 0.906  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.198      ;
; 0.908  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.201      ;
; 0.910  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.399      ; 1.563      ;
; 0.916  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.390      ; 1.560      ;
; 0.917  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.392      ; 1.563      ;
; 0.918  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.394      ; 1.566      ;
; 0.920  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.403      ; 1.577      ;
; 0.920  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.213      ;
; 0.926  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.401      ; 1.581      ;
; 0.929  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.405      ; 1.588      ;
; 0.930  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.397      ; 1.581      ;
; 0.932  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.392      ; 1.578      ;
; 0.933  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.402      ; 1.589      ;
; 0.936  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.076      ; 1.224      ;
; 0.938  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.400      ; 1.592      ;
; 0.939  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.394      ; 1.587      ;
; 0.939  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.232      ;
; 0.947  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.397      ; 1.598      ;
; 0.948  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.401      ; 1.603      ;
; 0.949  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.403      ; 1.606      ;
; 0.950  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.399      ; 1.603      ;
; 0.950  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.391      ; 1.595      ;
; 0.950  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.243      ;
; 0.953  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.408      ; 1.615      ;
; 0.953  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.402      ; 1.609      ;
; 0.954  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.391      ; 1.599      ;
; 0.954  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.080      ; 1.246      ;
; 0.957  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.399      ; 1.610      ;
; 0.959  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.403      ; 1.616      ;
; 0.960  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]                                               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.253      ;
; 0.965  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.408      ; 1.627      ;
; 0.970  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.397      ; 1.621      ;
; 0.973  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.392      ; 1.619      ;
; 0.974  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.397      ; 1.625      ;
; 0.979  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.394      ; 1.627      ;
; 0.979  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.081      ; 1.272      ;
; 0.981  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.390      ; 1.625      ;
; 0.982  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.390      ; 1.626      ;
; 0.985  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.386      ; 1.625      ;
; 0.987  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.400      ; 1.641      ;
; 0.988  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.399      ; 1.641      ;
; 0.990  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.401      ; 1.645      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                     ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                           ; To Node                             ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; -0.317 ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.490      ; 0.746      ;
; -0.313 ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.486      ; 0.746      ;
; -0.312 ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.485      ; 0.746      ;
; -0.299 ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.490      ; 0.764      ;
; -0.295 ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.486      ; 0.764      ;
; -0.294 ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.485      ; 0.764      ;
; 0.316  ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.474      ; 1.363      ;
; 0.369  ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.474      ; 1.416      ;
; 0.454  ; uberACync:Sink|ExtendOut[0]         ; uberACync:Sink|ExtendOut[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|ExtendOut[1]         ; uberACync:Sink|ExtendOut[1]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PreloadAna[1]        ; uberACync:Sink|PreloadAna[1]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PreloadAna[2]        ; uberACync:Sink|PreloadAna[2]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PreloadAna[0]        ; uberACync:Sink|PreloadAna[0]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PreloadDig[0]        ; uberACync:Sink|PreloadDig[0]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|AtZeroCrossing       ; uberACync:Sink|AtZeroCrossing       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|StateZero.11         ; uberACync:Sink|StateZero.11         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|StateZero.01         ; uberACync:Sink|StateZero.01         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|StateZero.00         ; uberACync:Sink|StateZero.00         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|AdcClk               ; uberACync:Sink|AdcClk               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotStart             ; uberACync:Sink|PotStart             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[6]            ; uberACync:Sink|PotBuf[6]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[5]            ; uberACync:Sink|PotBuf[5]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[4]            ; uberACync:Sink|PotBuf[4]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[3]            ; uberACync:Sink|PotBuf[3]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[2]            ; uberACync:Sink|PotBuf[2]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[1]            ; uberACync:Sink|PotBuf[1]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[0]            ; uberACync:Sink|PotBuf[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[7]            ; uberACync:Sink|PotBuf[7]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[8]            ; uberACync:Sink|PotBuf[8]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; uberACync:Sink|PotBuf[11]           ; uberACync:Sink|PotBuf[11]           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455  ; uberACync:Sink|PreloadDig[2]        ; uberACync:Sink|PreloadDig[2]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; uberACync:Sink|FifosClear           ; uberACync:Sink|FifosClear           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; uberACync:Sink|StateMode.011        ; uberACync:Sink|StateMode.011        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; uberACync:Sink|StateMode.101        ; uberACync:Sink|StateMode.101        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; uberACync:Sink|AdcConvert           ; uberACync:Sink|AdcConvert           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; uberACync:Sink|DacWr                ; uberACync:Sink|DacWr                ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; uberACync:Sink|DacLoad              ; uberACync:Sink|DacLoad              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; uberACync:Sink|PotBuf[10]           ; uberACync:Sink|PotBuf[10]           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; uberACync:Sink|PotBuf[9]            ; uberACync:Sink|PotBuf[9]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467  ; uberACync:Sink|CtrPot[0]            ; uberACync:Sink|CtrPot[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.467  ; uberACync:Sink|Clk3662Hz[0]         ; uberACync:Sink|Clk3662Hz[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.484  ; uberACync:Sink|PrbsShift[15]        ; uberACync:Sink|PrbsShift[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.776      ;
; 0.501  ; uberACync:Sink|PotBuf[2]            ; uberACync:Sink|PhaseDelayTime[10]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.793      ;
; 0.502  ; uberACync:Sink|PotBuf[4]            ; uberACync:Sink|PhaseDelayTime[12]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.794      ;
; 0.503  ; uberACync:Sink|PotBuf[6]            ; uberACync:Sink|PhaseDelayTime[14]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503  ; uberACync:Sink|PotBuf[3]            ; uberACync:Sink|PhaseDelayTime[11]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503  ; uberACync:Sink|PotBuf[1]            ; uberACync:Sink|PhaseDelayTime[9]    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.795      ;
; 0.509  ; uberACync:Sink|PotBuf[7]            ; uberACync:Sink|PhaseDelayTime[15]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.801      ;
; 0.511  ; uberACync:Sink|PotBuf[8]            ; uberACync:Sink|PhaseDelayTime[16]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.803      ;
; 0.527  ; uberACync:Sink|StateMode.010        ; uberACync:Sink|FifosClear           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.818      ;
; 0.642  ; uberACync:Sink|PrbsShift[13]        ; uberACync:Sink|PrbsShift[14]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.934      ;
; 0.642  ; uberACync:Sink|PrbsShift[12]        ; uberACync:Sink|PrbsShift[13]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.934      ;
; 0.643  ; uberACync:Sink|PrbsShift[5]         ; uberACync:Sink|PrbsShift[6]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.935      ;
; 0.645  ; uberACync:Sink|PrbsShift[14]        ; uberACync:Sink|PrbsShift[15]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.937      ;
; 0.645  ; uberACync:Sink|PrbsShift[6]         ; uberACync:Sink|PrbsShift[7]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.937      ;
; 0.654  ; uberACync:Sink|PreloadDig[0]        ; uberACync:Sink|PreloadDig[1]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.946      ;
; 0.668  ; uberACync:Sink|PrbsShift[0]         ; uberACync:Sink|PrbsShift[1]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.960      ;
; 0.679  ; uberACync:Sink|StateMode.011        ; uberACync:Sink|StateMode.100        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.970      ;
; 0.694  ; uberACync:Sink|PrbsShift[8]         ; uberACync:Sink|PrbsShift[9]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.986      ;
; 0.700  ; uberACync:Sink|PotBuf[5]            ; uberACync:Sink|PhaseDelayTime[13]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.992      ;
; 0.700  ; uberACync:Sink|PotBuf[0]            ; uberACync:Sink|PhaseDelayTime[8]    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.992      ;
; 0.707  ; uberACync:Sink|PotBuf[11]           ; uberACync:Sink|PhaseDelayTime[19]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.999      ;
; 0.727  ; uberACync:Sink|DigInBuf[4]          ; uberACync:Sink|DigOut[4]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.019      ;
; 0.728  ; uberACync:Sink|DigInBuf[0]          ; uberACync:Sink|DigOut[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.019      ;
; 0.742  ; uberACync:Sink|PrbsShift[9]         ; uberACync:Sink|PrbsShift[10]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.742  ; uberACync:Sink|PrbsShift[7]         ; uberACync:Sink|PrbsShift[8]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.742  ; uberACync:Sink|PrbsShift[2]         ; uberACync:Sink|PrbsShift[3]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.742  ; uberACync:Sink|PrbsShift[1]         ; uberACync:Sink|PrbsShift[2]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.743  ; uberACync:Sink|PrbsShift[11]        ; uberACync:Sink|PrbsShift[12]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.035      ;
; 0.743  ; uberACync:Sink|PrbsShift[4]         ; uberACync:Sink|PrbsShift[5]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.035      ;
; 0.743  ; uberACync:Sink|PrbsShift[3]         ; uberACync:Sink|PrbsShift[4]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.035      ;
; 0.745  ; uberACync:Sink|DelayTimer[8]        ; uberACync:Sink|DelayTimer[8]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.745  ; uberACync:Sink|DelayTimer[12]       ; uberACync:Sink|DelayTimer[12]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.745  ; uberACync:Sink|DelayTimer[10]       ; uberACync:Sink|DelayTimer[10]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.745  ; uberACync:Sink|DelayTimer[6]        ; uberACync:Sink|DelayTimer[6]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.745  ; uberACync:Sink|RetriggerInhibit[12] ; uberACync:Sink|RetriggerInhibit[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.745  ; uberACync:Sink|RetriggerInhibit[9]  ; uberACync:Sink|RetriggerInhibit[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.745  ; uberACync:Sink|RetriggerInhibit[8]  ; uberACync:Sink|RetriggerInhibit[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.746  ; uberACync:Sink|DelayTimer[14]       ; uberACync:Sink|DelayTimer[14]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|DelayTimer[7]        ; uberACync:Sink|DelayTimer[7]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|DelayTimer[5]        ; uberACync:Sink|DelayTimer[5]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|Clk3662Hz[10]        ; uberACync:Sink|Clk3662Hz[10]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|Clk3662Hz[4]         ; uberACync:Sink|Clk3662Hz[4]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|Clk3662Hz[2]         ; uberACync:Sink|Clk3662Hz[2]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|RetriggerInhibit[16] ; uberACync:Sink|RetriggerInhibit[16] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|RetriggerInhibit[14] ; uberACync:Sink|RetriggerInhibit[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|RetriggerInhibit[7]  ; uberACync:Sink|RetriggerInhibit[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|RetriggerInhibit[6]  ; uberACync:Sink|RetriggerInhibit[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|RetriggerInhibit[5]  ; uberACync:Sink|RetriggerInhibit[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; uberACync:Sink|RetriggerInhibit[4]  ; uberACync:Sink|RetriggerInhibit[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.747  ; uberACync:Sink|DelayTimer[15]       ; uberACync:Sink|DelayTimer[15]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747  ; uberACync:Sink|DelayTimer[13]       ; uberACync:Sink|DelayTimer[13]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747  ; uberACync:Sink|DelayTimer[11]       ; uberACync:Sink|DelayTimer[11]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747  ; uberACync:Sink|DelayTimer[4]        ; uberACync:Sink|DelayTimer[4]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747  ; uberACync:Sink|RetriggerInhibit[15] ; uberACync:Sink|RetriggerInhibit[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747  ; uberACync:Sink|RetriggerInhibit[13] ; uberACync:Sink|RetriggerInhibit[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747  ; uberACync:Sink|RetriggerInhibit[2]  ; uberACync:Sink|RetriggerInhibit[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.748  ; uberACync:Sink|DelayTimer[18]       ; uberACync:Sink|DelayTimer[18]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748  ; uberACync:Sink|DelayTimer[3]        ; uberACync:Sink|DelayTimer[3]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748  ; uberACync:Sink|Clk3662Hz[6]         ; uberACync:Sink|Clk3662Hz[6]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                                                                                                        ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; 0.455 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.746      ;
; 0.456 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 0.746      ;
; 0.502 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.793      ;
; 0.503 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.794      ;
; 0.504 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.795      ;
; 0.536 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.827      ;
; 0.545 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.397      ; 1.196      ;
; 0.545 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.836      ;
; 0.545 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.836      ;
; 0.548 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.397      ; 1.199      ;
; 0.568 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.397      ; 1.219      ;
; 0.599 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.397      ; 1.250      ;
; 0.602 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.397      ; 1.253      ;
; 0.613 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.397      ; 1.264      ;
; 0.621 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.397      ; 1.272      ;
; 0.646 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.937      ;
; 0.658 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.949      ;
; 0.697 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 0.988      ;
; 0.726 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.017      ;
; 0.735 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.026      ;
; 0.735 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.025      ;
; 0.767 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.058      ;
; 0.769 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.059      ;
; 0.769 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.059      ;
; 0.809 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.099      ;
; 0.816 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.399      ; 1.469      ;
; 0.821 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.111      ;
; 0.827 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.117      ;
; 0.829 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.119      ;
; 0.873 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.164      ;
; 0.900 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.191      ;
; 0.903 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.399      ; 1.556      ;
; 0.919 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.080      ; 1.211      ;
; 0.924 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.399      ; 1.577      ;
; 0.924 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.214      ;
; 0.938 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.228      ;
; 0.949 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.399      ; 1.602      ;
; 0.949 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.240      ;
; 0.950 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.416      ; 1.620      ;
; 0.957 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.416      ; 1.627      ;
; 0.966 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.257      ;
; 0.968 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.259      ;
; 0.970 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.397      ; 1.621      ;
; 0.971 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.416      ; 1.641      ;
; 0.979 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.269      ;
; 0.984 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.275      ;
; 0.986 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.277      ;
; 0.986 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.077      ; 1.275      ;
; 0.990 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.280      ;
; 0.993 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.284      ;
; 1.001 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.291      ;
; 1.004 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.294      ;
; 1.004 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.294      ;
; 1.004 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.294      ;
; 1.011 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.301      ;
; 1.021 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.311      ;
; 1.022 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.077      ; 1.311      ;
; 1.025 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.316      ;
; 1.048 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.077      ; 1.337      ;
; 1.048 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.338      ;
; 1.059 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.349      ;
; 1.068 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.399      ; 1.721      ;
; 1.083 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.374      ;
; 1.124 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.399      ; 1.777      ;
; 1.136 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.080      ; 1.428      ;
; 1.141 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.432      ;
; 1.141 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.432      ;
; 1.163 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.398      ; 1.815      ;
; 1.163 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.077      ; 1.452      ;
; 1.164 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.077      ; 1.453      ;
; 1.169 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.077      ; 1.458      ;
; 1.171 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.080      ; 1.463      ;
; 1.180 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.470      ;
; 1.183 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.400      ; 1.837      ;
; 1.183 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.077      ; 1.472      ;
; 1.193 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.401      ; 1.848      ;
; 1.197 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.488      ;
; 1.203 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.418      ; 1.875      ;
; 1.205 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.495      ;
; 1.210 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.500      ;
; 1.212 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.076      ; 1.500      ;
; 1.213 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.416      ; 1.883      ;
; 1.213 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.504      ;
; 1.214 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.416      ; 1.884      ;
; 1.227 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.079      ; 1.518      ;
; 1.239 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.399      ; 1.892      ;
; 1.242 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.078      ; 1.532      ;
; 1.243 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.077      ; 1.532      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                     ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.353      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.353      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.353      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.353      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.353      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.353      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.353      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.353      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.365      ; 3.354      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.365      ; 3.354      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.358      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.365      ; 3.354      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.368      ; 3.357      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.368      ; 3.357      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.368      ; 3.357      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.368      ; 3.357      ;
; -1.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.368      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.352      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.365      ; 3.353      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.352      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.365      ; 3.353      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.352      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.364      ; 3.352      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.362      ; 3.350      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.365      ; 3.353      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.365      ; 3.353      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.365      ; 3.353      ;
; -1.065 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.369      ; 3.357      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                  ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                        ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.942 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.908      ;
; -0.942 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.908      ;
; -0.942 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.124      ; 3.904      ;
; -0.942 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.124      ; 3.904      ;
; -0.942 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.126      ; 3.906      ;
; -0.942 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.126      ; 3.906      ;
; -0.941 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[11]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.122      ; 3.901      ;
; -0.941 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.122      ; 3.901      ;
; -0.941 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.114      ; 3.893      ;
; -0.941 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.114      ; 3.893      ;
; -0.941 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.116      ; 3.895      ;
; -0.941 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.116      ; 3.895      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.899      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.899      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.122      ; 3.900      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.122      ; 3.900      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.909      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.909      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[27]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.124      ; 3.902      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[43]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.124      ; 3.902      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.120      ; 3.898      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.120      ; 3.898      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.899      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.899      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[4]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.899      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.899      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.118      ; 3.896      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.118      ; 3.896      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.130      ; 3.908      ;
; -0.940 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.130      ; 3.908      ;
; -0.939 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[23]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.111      ; 3.888      ;
; -0.939 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.111      ; 3.888      ;
; -0.936 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.905      ;
; -0.936 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.905      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.904      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.904      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.114      ; 3.887      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.114      ; 3.887      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.124      ; 3.897      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.124      ; 3.897      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.132      ; 3.905      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.132      ; 3.905      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.132      ; 3.905      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.132      ; 3.905      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.130      ; 3.903      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.130      ; 3.903      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.893      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.893      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.893      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.893      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.120      ; 3.892      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[51]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.120      ; 3.892      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[6]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.116      ; 3.887      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.116      ; 3.887      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.126      ; 3.897      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.126      ; 3.897      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.122      ; 3.893      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.122      ; 3.893      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.899      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.899      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[17]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.122      ; 3.893      ;
; -0.933 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.122      ; 3.893      ;
; -0.932 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.118      ; 3.888      ;
; -0.932 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.118      ; 3.888      ;
; -0.850 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.135      ; 3.955      ;
; -0.850 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.129      ; 3.949      ;
; -0.850 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.948      ;
; -0.850 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.118      ; 3.938      ;
; -0.850 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.133      ; 3.953      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.947      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.129      ; 3.948      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.138      ; 3.957      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.950      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.950      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.127      ; 3.946      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.940      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.947      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.125      ; 3.944      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.123      ; 3.942      ;
; -0.849 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.137      ; 3.956      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.138      ; 3.951      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.125      ; 3.938      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.121      ; 3.934      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.131      ; 3.944      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.941      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.139      ; 3.952      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.133      ; 3.946      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.138      ; 3.951      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.139      ; 3.952      ;
; -0.843 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.135      ; 3.948      ;
; -0.842 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.128      ; 3.940      ;
; -0.842 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.123      ; 3.935      ;
; -0.842 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.129      ; 3.941      ;
; -0.842 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.137      ; 3.949      ;
; -0.842 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.129      ; 3.941      ;
; -0.841 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 3.127      ; 3.938      ;
; -0.617 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.800      ; 3.340      ;
; -0.617 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.800      ; 3.340      ;
; -0.617 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.800      ; 3.340      ;
; -0.617 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.800      ; 3.340      ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                    ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.790      ; 3.341      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.790      ; 3.341      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.789      ; 3.340      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.789      ; 3.340      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.789      ; 3.340      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.789      ; 3.340      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.790      ; 3.341      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.788      ; 3.339      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.788      ; 3.339      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.789      ; 3.340      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.789      ; 3.340      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.789      ; 3.340      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.343      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.788      ; 3.339      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.343      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.789      ; 3.340      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.791      ; 3.342      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.343      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.343      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.794      ; 3.345      ;
; -0.628 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.346      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.792      ; 3.342      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.345      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.345      ;
; -0.627 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.795      ; 3.345      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                     ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.197 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.879      ; 3.914      ;
; -0.197 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.879      ; 3.914      ;
; -0.197 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.877      ; 3.912      ;
; -0.197 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.878      ; 3.913      ;
; -0.196 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.866      ; 3.900      ;
; -0.196 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.879      ; 3.913      ;
; -0.195 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.869      ; 3.902      ;
; -0.195 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.869      ; 3.902      ;
; -0.194 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.861      ; 3.893      ;
; -0.194 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.865      ; 3.897      ;
; -0.194 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.863      ; 3.895      ;
; -0.194 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.871      ; 3.903      ;
; -0.194 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.873      ; 3.905      ;
; -0.194 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.875      ; 3.907      ;
; -0.191 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.885      ; 3.914      ;
; -0.191 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.883      ; 3.912      ;
; -0.190 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.887      ; 3.915      ;
; -0.190 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.888      ; 3.916      ;
; -0.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.879      ; 3.906      ;
; -0.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.878      ; 3.905      ;
; -0.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.888      ; 3.915      ;
; -0.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.889      ; 3.916      ;
; -0.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.875      ; 3.902      ;
; -0.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.878      ; 3.905      ;
; -0.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.875      ; 3.902      ;
; -0.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.874      ; 3.900      ;
; -0.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.868      ; 3.894      ;
; -0.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.866      ; 3.892      ;
; -0.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.877      ; 3.903      ;
; -0.187 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.882      ; 3.907      ;
; -0.187 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.871      ; 3.896      ;
; -0.187 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.879      ; 3.904      ;
; -0.105 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.873      ; 3.948      ;
; -0.105 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.872      ; 3.947      ;
; -0.105 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.880      ; 3.955      ;
; -0.105 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.882      ; 3.957      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.876      ; 3.950      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.876      ; 3.950      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.868      ; 3.942      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.870      ; 3.944      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.878      ; 3.952      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.886      ; 3.960      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.886      ; 3.960      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.886      ; 3.960      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.884      ; 3.958      ;
; -0.104 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.885      ; 3.959      ;
; -0.099 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.890      ; 3.959      ;
; -0.098 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.892      ; 3.960      ;
; -0.098 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.889      ; 3.957      ;
; -0.098 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.885      ; 3.953      ;
; -0.098 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.895      ; 3.963      ;
; -0.098 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.895      ; 3.963      ;
; -0.098 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.875      ; 3.943      ;
; -0.098 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.896      ; 3.964      ;
; -0.098 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.882      ; 3.950      ;
; -0.097 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.894      ; 3.961      ;
; -0.097 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.886      ; 3.953      ;
; -0.097 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.878      ; 3.945      ;
; -0.097 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.884      ; 3.951      ;
; -0.097 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.885      ; 3.952      ;
; -0.097 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.886      ; 3.953      ;
; -0.097 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.882      ; 3.949      ;
; -0.096 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.881      ; 3.947      ;
; -0.096 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.873      ; 3.939      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.559      ; 3.353      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
; 0.129  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.558      ; 3.352      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.266      ; 3.212      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.266      ; 3.212      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.266      ; 3.212      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.266      ; 3.212      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.266      ; 3.212      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.266      ; 3.212      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[2]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.336 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.264      ; 3.210      ;
; -1.335 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.263      ; 3.210      ;
; -1.335 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.263      ; 3.210      ;
; -1.335 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.263      ; 3.210      ;
; -1.335 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.263      ; 3.210      ;
; -1.335 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.263      ; 3.210      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.333 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.259      ; 3.208      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.328 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.255      ; 3.210      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.327 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.254      ; 3.209      ;
; -1.232 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.580      ; 3.672      ;
; -1.232 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.578      ; 3.670      ;
; -1.231 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.569      ; 3.662      ;
; -1.231 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.567      ; 3.660      ;
; -1.231 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.588      ; 3.681      ;
; -1.231 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.574      ; 3.667      ;
; -1.230 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.577      ; 3.671      ;
; -1.230 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.572      ; 3.666      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                     ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.467      ; 3.197      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.467      ; 3.197      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.467      ; 3.197      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.467      ; 3.197      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.466      ; 3.196      ;
; -0.552 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.467      ; 3.197      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.469      ; 3.200      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.469      ; 3.200      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.551 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.201      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.472      ; 3.204      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.472      ; 3.204      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.472      ; 3.204      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.472      ; 3.204      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.472      ; 3.204      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.472      ; 3.204      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.472      ; 3.204      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.470      ; 3.202      ;
; -0.550 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.203      ;
; -0.549 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.204      ;
; -0.549 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.204      ;
; -0.549 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.204      ;
; -0.549 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.204      ;
; -0.549 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.204      ;
; -0.549 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.204      ;
; -0.549 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.204      ;
; -0.549 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.471      ; 3.204      ;
; -0.456 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.797      ; 3.665      ;
; -0.455 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.786      ; 3.655      ;
; -0.455 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.784      ; 3.653      ;
; -0.455 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.794      ; 3.663      ;
; -0.455 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.790      ; 3.659      ;
; -0.454 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.789      ; 3.659      ;
; -0.454 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.789      ; 3.659      ;
; -0.454 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.800      ; 3.670      ;
; -0.454 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.788      ; 3.658      ;
; -0.454 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.790      ; 3.660      ;
; -0.453 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.799      ; 3.670      ;
; -0.453 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.792      ; 3.663      ;
; -0.453 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.800      ; 3.671      ;
; -0.453 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.800      ; 3.671      ;
; -0.453 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.798      ; 3.669      ;
; -0.452 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.782      ; 3.654      ;
; -0.449 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.790      ; 3.665      ;
; -0.448 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.797      ; 3.673      ;
; -0.448 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.789      ; 3.665      ;
; -0.448 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.799      ; 3.675      ;
; -0.448 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.792      ; 3.668      ;
; -0.448 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.788      ; 3.664      ;
; -0.448 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.789      ; 3.665      ;
; -0.448 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.779      ; 3.655      ;
; -0.448 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.789      ; 3.665      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                     ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.455      ; 3.197      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.455      ; 3.197      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.455      ; 3.197      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.453      ; 3.195      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.453      ; 3.195      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.453      ; 3.195      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.199      ;
; -0.540 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.456      ; 3.198      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.454      ; 3.197      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.454      ; 3.197      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.454      ; 3.197      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.454      ; 3.197      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.454      ; 3.197      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.454      ; 3.197      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.454      ; 3.197      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.200      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.200      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.454      ; 3.197      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.200      ;
; -0.539 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.457      ; 3.200      ;
; -0.538 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.204      ;
; -0.538 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.204      ;
; -0.538 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.204      ;
; -0.538 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.204      ;
; -0.538 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.205      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.205      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.205      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.205      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.205      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.205      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.459      ; 3.204      ;
; -0.537 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.460      ; 3.205      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.017      ; 3.213      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.212      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.212      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.212      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.212      ;
; -0.086 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.212      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.085 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.016      ; 3.213      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.011      ; 3.209      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.011      ; 3.209      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.011      ; 3.209      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.011      ; 3.209      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.013      ; 3.211      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.013      ; 3.211      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.013      ; 3.211      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.084 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.012      ; 3.210      ;
; -0.083 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.208      ;
; -0.083 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.208      ;
; -0.083 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.208      ;
; -0.083 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.208      ;
; -0.083 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.208      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
; -0.082 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 3.009      ; 3.209      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                         ;
+--------+--------------+----------------+------------+-----------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                          ;
+--------+--------------+----------------+------------+-----------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_we_reg        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                    ;
+--------+--------------+----------------+------------+-----------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                        ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                         ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[11]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[17]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[23]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[27]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[43]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[4]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[51]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[6]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11            ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                        ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                         ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_we_reg        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                    ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                           ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                            ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[2]                  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'Clk100'                                                                                          ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                      ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+
; 4.851 ; 4.851        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0]           ;
; 4.851 ; 4.851        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|observablevcoout ;
; 4.891 ; 4.891        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; Clk100~input|o                                              ;
; 4.923 ; 4.923        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.000 ; 5.000        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; Clk100~input|i                                              ;
; 5.000 ; 5.000        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; Clk100~input|i                                              ;
; 5.076 ; 5.076        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.109 ; 5.109        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; Clk100~input|o                                              ;
; 5.146 ; 5.146        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0]           ;
; 5.146 ; 5.146        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|observablevcoout ;
; 6.000 ; 10.000       ; 4.000          ; Port Rate        ; Clk100 ; Rise       ; Clk100                                                      ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                            ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                             ; Clock Edge ; Target                        ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------+
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacLoad        ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacWr          ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[0]    ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[1]    ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[2]    ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[0]      ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[1]      ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoAnaWrClk   ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[10] ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[13] ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[26] ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[29] ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[42] ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[45] ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[58] ;
; 8.025 ; 8.245        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[61] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[12]     ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[13]     ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[14]     ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[4]      ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[5]      ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[6]      ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[3]    ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[20] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[21] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[22] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[23] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[24] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[36] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[37] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[38] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[39] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[40] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[4]  ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[53] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[54] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[55] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[56] ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[5]  ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[6]  ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[7]  ;
; 8.026 ; 8.246        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[8]  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|AcLineBuf      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|AtZeroCrossing ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[0]   ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[0]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[1]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[2]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[3]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[4]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[5]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[6]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[7]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[8]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[0]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[1]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[2]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[3]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[4]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[5]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[6]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[7]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[8]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[4]    ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[5]    ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[2]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[3]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[4]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[5]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[6]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[7]      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|ExtendInBuf[0] ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|ExtendInBuf[1] ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|ExtendOut[0]   ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|ExtendOut[1]   ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoDigRdClk   ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoDigWrClk   ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[12] ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[28] ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[44] ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[52] ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[60] ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifosClear     ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|MasterBuf      ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PotStart       ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PreloadAna[0]  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PreloadAna[1]  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PreloadAna[2]  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PreloadDig[0]  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PreloadDig[1]  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PreloadDig[2]  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateMode.000  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateMode.001  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateMode.010  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateMode.011  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateMode.100  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateMode.101  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateMode.110  ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateZero.00   ;
; 8.027 ; 8.247        ; 0.220          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|StateZero.01   ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+
; AC60Hz       ; Clk100     ; 2.901 ; 3.032 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc1         ; Clk100     ; 6.716 ; 6.979 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc2         ; Clk100     ; 6.397 ; 6.653 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc3         ; Clk100     ; 4.305 ; 4.492 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc4         ; Clk100     ; 4.453 ; 4.697 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigIn[*]     ; Clk100     ; 5.841 ; 6.243 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[0]    ; Clk100     ; 5.779 ; 6.120 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[1]    ; Clk100     ; 5.841 ; 6.163 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[2]    ; Clk100     ; 5.583 ; 5.842 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[3]    ; Clk100     ; 5.300 ; 5.621 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[4]    ; Clk100     ; 5.831 ; 6.243 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[5]    ; Clk100     ; 5.520 ; 5.856 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[6]    ; Clk100     ; 5.804 ; 6.188 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[7]    ; Clk100     ; 5.525 ; 5.900 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendIn[*]  ; Clk100     ; 3.122 ; 3.276 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[0] ; Clk100     ; 3.047 ; 3.207 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[1] ; Clk100     ; 3.122 ; 3.276 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Master       ; Clk100     ; 3.179 ; 3.329 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotDat       ; Clk100     ; 3.238 ; 3.466 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                   ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+
; AC60Hz       ; Clk100     ; -2.119 ; -2.248 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc1         ; Clk100     ; -4.015 ; -4.224 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc2         ; Clk100     ; -4.416 ; -4.660 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc3         ; Clk100     ; -2.456 ; -2.554 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc4         ; Clk100     ; -1.778 ; -1.875 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigIn[*]     ; Clk100     ; -4.401 ; -4.697 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[0]    ; Clk100     ; -4.858 ; -5.174 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[1]    ; Clk100     ; -4.936 ; -5.245 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[2]    ; Clk100     ; -4.672 ; -4.909 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[3]    ; Clk100     ; -4.401 ; -4.697 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[4]    ; Clk100     ; -4.901 ; -5.290 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[5]    ; Clk100     ; -4.607 ; -4.920 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[6]    ; Clk100     ; -4.897 ; -5.268 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[7]    ; Clk100     ; -4.612 ; -4.963 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendIn[*]  ; Clk100     ; -2.260 ; -2.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[0] ; Clk100     ; -2.260 ; -2.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[1] ; Clk100     ; -2.332 ; -2.483 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Master       ; Clk100     ; -2.386 ; -2.534 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotDat       ; Clk100     ; -1.668 ; -1.869 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                         ;
+---------------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+---------------+------------+--------+--------+------------+---------------------------------------------------+
; AdcClk        ; Clk100     ; 5.486  ; 5.394  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; AdcConvert    ; Clk100     ; 5.554  ; 5.477  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacAddr[*]    ; Clk100     ; 8.981  ; 8.957  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[0]   ; Clk100     ; 6.264  ; 6.062  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[1]   ; Clk100     ; 6.459  ; 6.269  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[2]   ; Clk100     ; 8.981  ; 8.957  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[3]   ; Clk100     ; 5.803  ; 5.721  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacDat[*]     ; Clk100     ; 9.826  ; 10.014 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[0]    ; Clk100     ; 6.440  ; 6.265  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[1]    ; Clk100     ; 5.795  ; 5.703  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[2]    ; Clk100     ; 6.745  ; 6.484  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[3]    ; Clk100     ; 5.926  ; 5.895  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[4]    ; Clk100     ; 6.602  ; 6.537  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[5]    ; Clk100     ; 6.912  ; 6.678  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[6]    ; Clk100     ; 7.159  ; 6.891  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[7]    ; Clk100     ; 7.484  ; 7.112  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[8]    ; Clk100     ; 9.826  ; 10.014 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[9]    ; Clk100     ; 7.884  ; 7.541  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[10]   ; Clk100     ; 7.489  ; 7.177  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[11]   ; Clk100     ; 6.370  ; 6.209  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[12]   ; Clk100     ; 8.721  ; 8.329  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[13]   ; Clk100     ; 7.266  ; 7.128  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[14]   ; Clk100     ; 9.014  ; 8.495  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[15]   ; Clk100     ; 7.790  ; 7.558  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacLoad       ; Clk100     ; 7.133  ; 7.028  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacWr         ; Clk100     ; 6.589  ; 6.446  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigOut[*]     ; Clk100     ; 8.326  ; 8.380  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[0]    ; Clk100     ; 5.473  ; 5.351  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[1]    ; Clk100     ; 5.895  ; 5.823  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[2]    ; Clk100     ; 5.792  ; 5.639  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[3]    ; Clk100     ; 5.635  ; 5.434  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[4]    ; Clk100     ; 8.326  ; 8.380  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[5]    ; Clk100     ; 5.985  ; 5.778  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[6]    ; Clk100     ; 6.349  ; 6.148  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[7]    ; Clk100     ; 6.658  ; 6.414  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendOut[*]  ; Clk100     ; 6.996  ; 6.672  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[0] ; Clk100     ; 6.681  ; 6.496  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[1] ; Clk100     ; 6.996  ; 6.672  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Led           ; Clk100     ; 10.645 ; 10.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotClk        ; Clk100     ; 5.417  ; 5.238  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotStart      ; Clk100     ; 5.286  ; 5.131  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Prbs          ; Clk100     ; 7.520  ; 7.122  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+---------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                               ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; AdcClk        ; Clk100     ; 4.810 ; 4.722 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; AdcConvert    ; Clk100     ; 4.877 ; 4.803 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacAddr[*]    ; Clk100     ; 5.117 ; 5.036 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[0]   ; Clk100     ; 5.559 ; 5.364 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[1]   ; Clk100     ; 5.747 ; 5.563 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[2]   ; Clk100     ; 8.279 ; 8.264 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[3]   ; Clk100     ; 5.117 ; 5.036 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacDat[*]     ; Clk100     ; 5.110 ; 5.020 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[0]    ; Clk100     ; 5.729 ; 5.559 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[1]    ; Clk100     ; 5.110 ; 5.020 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[2]    ; Clk100     ; 6.023 ; 5.771 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[3]    ; Clk100     ; 5.237 ; 5.207 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[4]    ; Clk100     ; 5.878 ; 5.815 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[5]    ; Clk100     ; 6.183 ; 5.958 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[6]    ; Clk100     ; 6.420 ; 6.162 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[7]    ; Clk100     ; 6.726 ; 6.368 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[8]    ; Clk100     ; 9.084 ; 9.273 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[9]    ; Clk100     ; 7.116 ; 6.787 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[10]   ; Clk100     ; 6.735 ; 6.434 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[11]   ; Clk100     ; 5.661 ; 5.505 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[12]   ; Clk100     ; 7.918 ; 7.540 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[13]   ; Clk100     ; 6.521 ; 6.387 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[14]   ; Clk100     ; 8.199 ; 7.699 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[15]   ; Clk100     ; 7.025 ; 6.800 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacLoad       ; Clk100     ; 6.394 ; 6.292 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacWr         ; Clk100     ; 5.872 ; 5.733 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigOut[*]     ; Clk100     ; 4.800 ; 4.681 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[0]    ; Clk100     ; 4.800 ; 4.681 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[1]    ; Clk100     ; 5.206 ; 5.135 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[2]    ; Clk100     ; 5.106 ; 4.957 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[3]    ; Clk100     ; 4.955 ; 4.760 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[4]    ; Clk100     ; 7.649 ; 7.708 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[5]    ; Clk100     ; 5.291 ; 5.090 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[6]    ; Clk100     ; 5.640 ; 5.446 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[7]    ; Clk100     ; 5.937 ; 5.701 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendOut[*]  ; Clk100     ; 5.959 ; 5.780 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[0] ; Clk100     ; 5.959 ; 5.780 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[1] ; Clk100     ; 6.262 ; 5.949 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Led           ; Clk100     ; 6.090 ; 5.865 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotClk        ; Clk100     ; 4.746 ; 4.572 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotStart      ; Clk100     ; 4.620 ; 4.470 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Prbs          ; Clk100     ; 6.766 ; 6.381 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+


----------------
; MTBF Summary ;
----------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Synchronizer Summary                                                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+
; Source Node                                                                              ; Synchronization Node                                                                                                              ; Typical MTBF (Years) ; Included in Design MTBF ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                    ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                    ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]   ; Not Calculated       ; Yes                     ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+


Synchronizer Chain #1: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -4.959         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9] ;                ;              ;                  ; -1.568       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9] ;                ;              ;                  ; -3.391       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #2: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -4.283         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0] ;                ;              ;                  ; -0.982       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0] ;                ;              ;                  ; -3.301       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #3: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -4.240         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;                ;              ;                  ; -0.976       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ;                ;              ;                  ; -3.264       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #4: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -4.204         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8] ;                ;              ;                  ; -1.233       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8] ;                ;              ;                  ; -2.971       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #5: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -4.178         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1] ;                ;              ;                  ; -1.339       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1] ;                ;              ;                  ; -2.839       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #6: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -4.048         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;                ;              ;                  ; -0.173       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ;                ;              ;                  ; -3.875       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #7: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.858         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1] ;                ;              ;                  ; -1.626       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1] ;                ;              ;                  ; -2.232       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #8: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -3.857         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;                ;              ;                  ; -0.131       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ;                ;              ;                  ; -3.726       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #9: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.847         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ;                ;              ;                  ; -1.373       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ;                ;              ;                  ; -2.474       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #10: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -3.836         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;                ;              ;                  ; -0.330       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ;                ;              ;                  ; -3.506       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #11: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.798         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2] ;                ;              ;                  ; -0.663       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2] ;                ;              ;                  ; -3.135       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #12: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.752         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4] ;                ;              ;                  ; -0.341       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4] ;                ;              ;                  ; -3.411       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #13: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.501         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5] ;                ;              ;                  ; -0.714       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5] ;                ;              ;                  ; -2.787       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #14: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.489         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7] ;                ;              ;                  ; -0.624       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7] ;                ;              ;                  ; -2.865       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #15: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -3.488         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;                ;              ;                  ; 0.041        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ;                ;              ;                  ; -3.529       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #16: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.403         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0] ;                ;              ;                  ; -1.036       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0] ;                ;              ;                  ; -2.367       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #17: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -3.345         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6] ;                ;              ;                  ; -0.950       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6] ;                ;              ;                  ; -2.395       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #18: Worst-Case MTBF is Not Calculated
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                          ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                 ;
; Included in Design MTBF ; Yes                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                        ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                           ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                            ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                    ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                    ; -3.324         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                       ; 125            ;              ;                  ;              ;
; Source Clock                                                                                    ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                           ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
; Synchronization Registers                                                                       ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;                ;              ;                  ; -3.324       ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #19: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -3.114         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2] ;                ;              ;                  ; -0.380       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2] ;                ;              ;                  ; -2.734       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #20: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -3.081         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7] ;                ;              ;                  ; -1.039       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7] ;                ;              ;                  ; -2.042       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #21: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.046         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7] ;                ;              ;                  ; 0.039        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7] ;                ;              ;                  ; -3.085       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #22: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -3.000         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9] ;                ;              ;                  ; -0.618       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9] ;                ;              ;                  ; -2.382       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #23: Worst-Case MTBF is Not Calculated
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                          ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                 ;
; Included in Design MTBF ; Yes                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                        ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                           ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                            ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                    ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                    ; -2.988         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                       ; 125            ;              ;                  ;              ;
; Source Clock                                                                                    ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                           ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
; Synchronization Registers                                                                       ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;                ;              ;                  ; -2.988       ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #24: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.903         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ;                ;              ;                  ; -0.718       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ;                ;              ;                  ; -2.185       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #25: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.900         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ;                ;              ;                  ; -0.172       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ;                ;              ;                  ; -2.728       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #26: Worst-Case MTBF is Not Calculated
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                           ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                  ;
; Included in Design MTBF ; Yes                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                     ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                     ; -2.879         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                              ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
; Synchronization Registers                                                                        ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;                ;              ;                  ; -2.879       ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #27: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.836         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5] ;                ;              ;                  ; -0.169       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5] ;                ;              ;                  ; -2.667       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #28: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.827         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3] ;                ;              ;                  ; 0.042        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3] ;                ;              ;                  ; -2.869       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #29: Worst-Case MTBF is Not Calculated
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                           ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                  ;
; Included in Design MTBF ; Yes                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                     ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                     ; -2.797         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                              ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
; Synchronization Registers                                                                        ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;                ;              ;                  ; -2.797       ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #30: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.791         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6] ;                ;              ;                  ; -0.336       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6] ;                ;              ;                  ; -2.455       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #31: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.782         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3] ;                ;              ;                  ; 0.039        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3] ;                ;              ;                  ; -2.821       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #32: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.751         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ;                ;              ;                  ; 0.039        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ;                ;              ;                  ; -2.790       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #33: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.712         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1] ;                ;              ;                  ; -0.170       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1] ;                ;              ;                  ; -2.542       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #34: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.631         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ;                ;              ;                  ; -0.475       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ;                ;              ;                  ; -2.156       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #35: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.617         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3] ;                ;              ;                  ; -0.169       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3] ;                ;              ;                  ; -2.448       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #36: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.583         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ;                ;              ;                  ; -0.144       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ;                ;              ;                  ; -2.439       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #37: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.529         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5] ;                ;              ;                  ; -0.125       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5] ;                ;              ;                  ; -2.404       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #38: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.520         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;                ;              ;                  ; -0.173       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ;                ;              ;                  ; -2.347       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #39: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.504         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ;                ;              ;                  ; -0.699       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ;                ;              ;                  ; -1.805       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #40: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.430         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0] ;                ;              ;                  ; -0.326       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0] ;                ;              ;                  ; -2.104       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #41: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.409         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6] ;                ;              ;                  ; -0.372       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6] ;                ;              ;                  ; -2.037       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #42: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.368         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4] ;                ;              ;                  ; 0.041        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4] ;                ;              ;                  ; -2.409       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #43: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.295         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4] ;                ;              ;                  ; 0.040        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4] ;                ;              ;                  ; -2.335       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #44: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.270         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7] ;                ;              ;                  ; 0.041        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7] ;                ;              ;                  ; -2.311       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #45: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.249         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8] ;                ;              ;                  ; -0.147       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8] ;                ;              ;                  ; -2.102       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #46: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.244         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2] ;                ;              ;                  ; -0.122       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2] ;                ;              ;                  ; -2.122       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #47: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.181         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0] ;                ;              ;                  ; 0.040        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0] ;                ;              ;                  ; -2.221       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #48: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.176         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ;                ;              ;                  ; -0.623       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ;                ;              ;                  ; -1.553       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #49: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.176         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ;                ;              ;                  ; 0.041        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ;                ;              ;                  ; -2.217       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #50: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.175         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5] ;                ;              ;                  ; -0.168       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5] ;                ;              ;                  ; -2.007       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #51: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.166         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ;                ;              ;                  ; 0.040        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ;                ;              ;                  ; -2.206       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #52: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.101         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8] ;                ;              ;                  ; 0.040        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8] ;                ;              ;                  ; -2.141       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #53: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.063         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ;                ;              ;                  ; 0.040        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ;                ;              ;                  ; -2.103       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #54: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.052         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ;                ;              ;                  ; 0.039        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ;                ;              ;                  ; -2.091       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #55: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.017         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9] ;                ;              ;                  ; 0.040        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9] ;                ;              ;                  ; -2.057       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #56: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.892         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4] ;                ;              ;                  ; -0.169       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4] ;                ;              ;                  ; -1.723       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #57: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.859         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6] ;                ;              ;                  ; -0.330       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6] ;                ;              ;                  ; -1.529       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #58: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -1.809         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9] ;                ;              ;                  ; -0.168       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9] ;                ;              ;                  ; -1.641       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #59: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.802         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2] ;                ;              ;                  ; -0.303       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2] ;                ;              ;                  ; -1.499       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #60: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.767         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1] ;                ;              ;                  ; 0.042        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1] ;                ;              ;                  ; -1.809       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #61: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -1.755         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8] ;                ;              ;                  ; -0.172       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8] ;                ;              ;                  ; -1.583       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #62: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.733         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3] ;                ;              ;                  ; 0.040        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3] ;                ;              ;                  ; -1.773       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



+-----------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                 ;
+------------+-----------------+---------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                        ; Note                                           ;
+------------+-----------------+---------------------------------------------------+------------------------------------------------+
; 112.82 MHz ; 112.82 MHz      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 213.4 MHz  ; 213.4 MHz       ; uberACync:Sink|FifoDigRdClk                       ;                                                ;
; 222.42 MHz ; 222.42 MHz      ; uberACync:Sink|FifoDigWrClk                       ;                                                ;
; 244.74 MHz ; 238.04 MHz      ; uberACync:Sink|FifoAnaWrClk                       ; limit due to minimum period restriction (tmin) ;
; 263.71 MHz ; 238.04 MHz      ; uberACync:Sink|FifoAnaRdClk                       ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+---------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+----------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                         ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; -7.337 ; -160.073      ;
; uberACync:Sink|FifoDigWrClk                       ; -6.211 ; -761.524      ;
; uberACync:Sink|FifoAnaWrClk                       ; -4.630 ; -547.631      ;
; uberACync:Sink|FifoDigRdClk                       ; -3.686 ; -251.120      ;
; uberACync:Sink|FifoAnaRdClk                       ; -2.792 ; -289.875      ;
+---------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                          ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; uberACync:Sink|FifoAnaWrClk                       ; -1.464 ; -43.265       ;
; uberACync:Sink|FifoDigRdClk                       ; -1.429 ; -2.858        ;
; uberACync:Sink|FifoDigWrClk                       ; -1.394 ; -39.280       ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; -0.429 ; -1.276        ;
; uberACync:Sink|FifoAnaRdClk                       ; 0.403  ; 0.000         ;
+---------------------------------------------------+--------+---------------+


+------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                ;
+-----------------------------+--------+---------------+
; Clock                       ; Slack  ; End Point TNS ;
+-----------------------------+--------+---------------+
; uberACync:Sink|FifoDigWrClk ; -1.077 ; -93.670       ;
; uberACync:Sink|FifoAnaRdClk ; -0.935 ; -136.110      ;
; uberACync:Sink|FifoAnaWrClk ; -0.658 ; -47.351       ;
; uberACync:Sink|FifoDigRdClk ; -0.228 ; -12.380       ;
+-----------------------------+--------+---------------+


+------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                 ;
+-----------------------------+--------+---------------+
; Clock                       ; Slack  ; End Point TNS ;
+-----------------------------+--------+---------------+
; uberACync:Sink|FifoDigRdClk ; -1.189 ; -176.471      ;
; uberACync:Sink|FifoAnaRdClk ; -0.443 ; -62.701       ;
; uberACync:Sink|FifoAnaWrClk ; -0.435 ; -31.235       ;
; uberACync:Sink|FifoDigWrClk ; 0.000  ; 0.000         ;
+-----------------------------+--------+---------------+


+----------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                           ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; uberACync:Sink|FifoDigWrClk                       ; -3.201 ; -436.665      ;
; uberACync:Sink|FifoAnaRdClk                       ; -3.201 ; -418.821      ;
; uberACync:Sink|FifoAnaWrClk                       ; -3.201 ; -414.360      ;
; uberACync:Sink|FifoDigRdClk                       ; -3.201 ; -347.616      ;
; Clk100                                            ; 4.849  ; 0.000         ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 8.025  ; 0.000         ;
+---------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                    ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                          ; To Node                   ; Launch Clock                ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+
; -7.337 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5        ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.067     ; 3.224      ;
; -7.238 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.384      ;
; -7.228 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.064     ; 3.118      ;
; -7.158 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.087     ; 3.025      ;
; -7.139 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7        ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.087     ; 3.006      ;
; -7.108 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17       ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.070     ; 2.992      ;
; -7.104 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.250      ;
; -7.104 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.250      ;
; -7.103 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0        ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.067     ; 2.990      ;
; -7.040 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.067     ; 2.927      ;
; -7.036 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.182      ;
; -7.027 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.173      ;
; -6.979 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.082     ; 2.851      ;
; -6.968 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.114      ;
; -6.967 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.070     ; 2.851      ;
; -6.954 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1        ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.070     ; 2.838      ;
; -6.931 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 3.077      ;
; -6.927 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.088     ; 2.793      ;
; -6.919 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6        ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.072     ; 2.801      ;
; -6.918 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.079     ; 2.793      ;
; -6.917 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.086     ; 2.785      ;
; -6.881 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.088     ; 2.747      ;
; -6.860 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.077     ; 2.737      ;
; -6.852 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4        ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.074     ; 2.732      ;
; -6.833 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25       ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.070     ; 2.717      ;
; -6.767 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.071     ; 2.650      ;
; -6.754 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3        ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.075     ; 2.633      ;
; -6.747 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.348     ; 3.353      ;
; -6.744 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.325     ; 3.373      ;
; -6.735 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.067     ; 2.622      ;
; -6.718 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 2.864      ;
; -6.718 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 2.864      ;
; -6.716 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.808     ; 2.862      ;
; -6.711 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.325     ; 3.340      ;
; -6.708 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.078     ; 2.584      ;
; -6.703 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.084     ; 2.573      ;
; -6.702 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.077     ; 2.579      ;
; -6.659 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.815     ; 2.798      ;
; -6.645 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.815     ; 2.784      ;
; -6.638 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.339     ; 3.253      ;
; -6.625 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16       ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.069     ; 2.510      ;
; -6.598 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9        ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.064     ; 2.488      ;
; -6.598 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.332     ; 3.220      ;
; -6.579 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8        ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.067     ; 2.466      ;
; -6.568 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.344     ; 3.178      ;
; -6.549 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                ; uberACync:Sink|DacDat[3]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.336     ; 3.167      ;
; -6.543 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.065     ; 2.432      ;
; -6.542 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.326     ; 3.170      ;
; -6.530 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.078     ; 2.406      ;
; -6.488 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.349     ; 3.093      ;
; -6.475 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24       ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.068     ; 2.361      ;
; -6.438 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.326     ; 3.066      ;
; -6.398 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.348     ; 3.004      ;
; -6.341 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.068     ; 2.227      ;
; -6.335 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]               ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.348     ; 2.941      ;
; -6.326 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.349     ; 2.931      ;
; -6.317 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.330     ; 2.941      ;
; -6.315 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2        ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -4.066     ; 2.203      ;
; -6.306 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.344     ; 2.916      ;
; -6.287 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]               ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.338     ; 2.903      ;
; -6.255 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.331     ; 2.878      ;
; -6.210 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]               ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.327     ; 2.837      ;
; -6.208 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 2.363      ;
; -6.199 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 2.354      ;
; -6.198 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.332     ; 2.820      ;
; -6.192 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.341     ; 2.805      ;
; -6.164 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.329     ; 2.789      ;
; -6.148 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.335     ; 2.767      ;
; -6.100 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.342     ; 2.712      ;
; -6.050 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.339     ; 2.665      ;
; -6.046 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.339     ; 2.661      ;
; -6.037 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 2.192      ;
; -6.034 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]               ; uberACync:Sink|DacDat[13] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.332     ; 2.656      ;
; -6.028 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.329     ; 2.653      ;
; -6.016 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]               ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.330     ; 2.640      ;
; -6.014 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.337     ; 2.631      ;
; -6.013 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.799     ; 2.168      ;
; -6.004 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.331     ; 2.627      ;
; -5.997 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.329     ; 2.622      ;
; -5.994 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.327     ; 2.621      ;
; -5.943 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.341     ; 2.556      ;
; -5.911 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.329     ; 2.536      ;
; -5.905 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.337     ; 2.522      ;
; -5.875 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]               ; uberACync:Sink|DacDat[6]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.347     ; 2.482      ;
; -5.869 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.348     ; 2.475      ;
; -5.868 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.330     ; 2.492      ;
; -5.851 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.327     ; 2.478      ;
; -5.844 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]               ; uberACync:Sink|DacDat[13] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.333     ; 2.465      ;
; -5.841 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.342     ; 2.453      ;
; -5.841 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.332     ; 2.463      ;
; -5.829 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.330     ; 2.453      ;
; -5.823 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.335     ; 2.442      ;
; -5.779 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.325     ; 2.408      ;
; -5.703 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.325     ; 2.332      ;
; -5.698 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.339     ; 2.313      ;
; -5.672 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.337     ; 2.289      ;
; -5.644 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]               ; uberACync:Sink|DacDat[6]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.347     ; 2.251      ;
; -5.635 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]               ; uberACync:Sink|DacDat[6]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.335     ; 2.254      ;
; -5.569 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]               ; uberACync:Sink|DacDat[11] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.329     ; 2.194      ;
; -5.559 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]               ; uberACync:Sink|DacDat[3]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -3.338     ; 2.175      ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                                                                         ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -6.211 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.292      ;
; -6.211 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.292      ;
; -6.210 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.286      ;
; -6.210 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.286      ;
; -6.210 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.286      ;
; -6.210 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.286      ;
; -6.205 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.286      ;
; -6.204 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.280      ;
; -6.204 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.280      ;
; -6.198 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.279      ;
; -6.197 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.273      ;
; -6.197 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.273      ;
; -6.189 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.961     ; 6.267      ;
; -6.189 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.961     ; 6.267      ;
; -6.188 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.261      ;
; -6.188 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.261      ;
; -6.188 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.261      ;
; -6.188 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.261      ;
; -6.184 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.265      ;
; -6.183 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.259      ;
; -6.183 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.259      ;
; -6.183 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.961     ; 6.261      ;
; -6.182 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.255      ;
; -6.182 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.255      ;
; -6.176 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.961     ; 6.254      ;
; -6.175 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.248      ;
; -6.175 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.248      ;
; -6.173 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.955     ; 6.257      ;
; -6.173 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.955     ; 6.257      ;
; -6.172 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.251      ;
; -6.172 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.251      ;
; -6.172 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.251      ;
; -6.172 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.251      ;
; -6.168 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.249      ;
; -6.168 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.249      ;
; -6.167 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.243      ;
; -6.167 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.243      ;
; -6.167 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.955     ; 6.251      ;
; -6.167 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.243      ;
; -6.167 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.243      ;
; -6.166 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.245      ;
; -6.166 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.245      ;
; -6.162 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.243      ;
; -6.161 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.237      ;
; -6.161 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.237      ;
; -6.160 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.955     ; 6.244      ;
; -6.159 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.238      ;
; -6.159 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.238      ;
; -6.155 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.236      ;
; -6.154 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.230      ;
; -6.154 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.230      ;
; -6.147 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.949     ; 6.237      ;
; -6.146 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.231      ;
; -6.146 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.231      ;
; -6.140 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.221      ;
; -6.139 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.215      ;
; -6.139 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.215      ;
; -6.132 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.946     ; 6.225      ;
; -6.132 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.208      ;
; -6.132 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.208      ;
; -6.131 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.951     ; 6.219      ;
; -6.131 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.951     ; 6.219      ;
; -6.131 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.212      ;
; -6.131 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.949     ; 6.221      ;
; -6.131 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.949     ; 6.221      ;
; -6.130 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.215      ;
; -6.130 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.215      ;
; -6.130 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.215      ;
; -6.130 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.215      ;
; -6.125 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.949     ; 6.215      ;
; -6.124 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.209      ;
; -6.124 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.209      ;
; -6.121 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.194      ;
; -6.121 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.194      ;
; -6.120 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.961     ; 6.198      ;
; -6.118 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.961     ; 6.196      ;
; -6.118 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.958     ; 6.199      ;
; -6.118 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.949     ; 6.208      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.949     ; 6.207      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.190      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.966     ; 6.190      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.196      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.960     ; 6.196      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.193      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.963     ; 6.193      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.202      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.202      ;
; -6.117 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.949     ; 6.207      ;
; -6.116 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.201      ;
; -6.116 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.201      ;
; -6.116 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.955     ; 6.200      ;
; -6.116 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.946     ; 6.209      ;
; -6.116 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.201      ;
; -6.116 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.954     ; 6.201      ;
; -6.116 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.946     ; 6.209      ;
; -6.115 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.962     ; 6.192      ;
; -6.115 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.951     ; 6.203      ;
; -6.115 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.951     ; 6.203      ;
; -6.115 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.951     ; 6.203      ;
; -6.115 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.951     ; 6.203      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                                                          ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                           ; To Node                                                                                                                        ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -4.630 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.196      ; 5.865      ;
; -4.630 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.196      ; 5.865      ;
; -4.629 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.869      ;
; -4.629 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.196      ; 5.864      ;
; -4.629 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.196      ; 5.864      ;
; -4.628 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.868      ;
; -4.600 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.196      ; 5.835      ;
; -4.600 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.196      ; 5.835      ;
; -4.599 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.839      ;
; -4.578 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.196      ; 5.813      ;
; -4.578 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.196      ; 5.813      ;
; -4.577 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.817      ;
; -4.556 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.195      ; 5.790      ;
; -4.556 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.195      ; 5.790      ;
; -4.555 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.200      ; 5.794      ;
; -4.555 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.195      ; 5.789      ;
; -4.555 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.195      ; 5.789      ;
; -4.554 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.200      ; 5.793      ;
; -4.551 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.798      ;
; -4.551 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.798      ;
; -4.550 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.213      ; 5.802      ;
; -4.550 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.797      ;
; -4.550 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.797      ;
; -4.549 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.213      ; 5.801      ;
; -4.548 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.791      ;
; -4.548 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.791      ;
; -4.547 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.209      ; 5.795      ;
; -4.547 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.790      ;
; -4.547 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.790      ;
; -4.546 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.209      ; 5.794      ;
; -4.533 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.775      ;
; -4.533 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.775      ;
; -4.532 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.779      ;
; -4.532 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.774      ;
; -4.532 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.774      ;
; -4.531 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.778      ;
; -4.529 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.769      ;
; -4.529 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.769      ;
; -4.528 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.206      ; 5.773      ;
; -4.528 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.768      ;
; -4.528 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.768      ;
; -4.527 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.206      ; 5.772      ;
; -4.526 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.207      ; 5.772      ;
; -4.526 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.207      ; 5.772      ;
; -4.526 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.195      ; 5.760      ;
; -4.526 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.195      ; 5.760      ;
; -4.525 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.212      ; 5.776      ;
; -4.525 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.200      ; 5.764      ;
; -4.525 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.207      ; 5.771      ;
; -4.525 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.207      ; 5.771      ;
; -4.524 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.212      ; 5.775      ;
; -4.521 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.768      ;
; -4.521 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.768      ;
; -4.520 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.213      ; 5.772      ;
; -4.518 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.761      ;
; -4.518 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.761      ;
; -4.517 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.209      ; 5.765      ;
; -4.515 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.199      ; 5.753      ;
; -4.515 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.199      ; 5.753      ;
; -4.514 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.202      ; 5.755      ;
; -4.514 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.202      ; 5.755      ;
; -4.514 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.757      ;
; -4.514 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.199      ; 5.752      ;
; -4.514 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.199      ; 5.752      ;
; -4.513 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.206      ; 5.758      ;
; -4.513 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.206      ; 5.758      ;
; -4.513 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.207      ; 5.759      ;
; -4.513 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.755      ;
; -4.513 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.755      ;
; -4.513 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.202      ; 5.754      ;
; -4.513 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.202      ; 5.754      ;
; -4.513 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.756      ;
; -4.512 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.211      ; 5.762      ;
; -4.512 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.759      ;
; -4.512 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.206      ; 5.757      ;
; -4.512 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.206      ; 5.757      ;
; -4.512 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.207      ; 5.758      ;
; -4.512 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.754      ;
; -4.512 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.754      ;
; -4.511 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.211      ; 5.761      ;
; -4.511 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.758      ;
; -4.504 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.195      ; 5.738      ;
; -4.504 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.195      ; 5.738      ;
; -4.503 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.200      ; 5.742      ;
; -4.503 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.745      ;
; -4.503 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.203      ; 5.745      ;
; -4.502 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.749      ;
; -4.499 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.746      ;
; -4.499 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.208      ; 5.746      ;
; -4.499 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.739      ;
; -4.499 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.201      ; 5.739      ;
; -4.498 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.213      ; 5.750      ;
; -4.498 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.206      ; 5.743      ;
; -4.496 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.739      ;
; -4.496 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.204      ; 5.739      ;
; -4.496 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.207      ; 5.742      ;
; -4.496 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.207      ; 5.742      ;
; -4.495 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.209      ; 5.743      ;
; -4.495 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.212      ; 5.746      ;
; -4.494 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.198      ; 5.731      ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                                                                                                         ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                         ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -3.686 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 4.624      ;
; -3.652 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 4.590      ;
; -3.485 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 4.423      ;
; -3.386 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.063     ; 4.325      ;
; -3.362 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.293      ;
; -3.358 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 4.296      ;
; -3.297 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.067     ; 4.232      ;
; -3.289 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.220      ;
; -3.270 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.063     ; 4.209      ;
; -3.253 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.067     ; 4.188      ;
; -3.251 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.063     ; 4.190      ;
; -3.224 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.067     ; 4.159      ;
; -3.222 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.153      ;
; -3.208 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.138      ;
; -3.204 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.134      ;
; -3.180 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.067     ; 4.115      ;
; -3.162 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 4.100      ;
; -3.157 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 4.087      ;
; -3.149 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.080      ;
; -3.143 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 4.077      ;
; -3.122 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.053      ;
; -3.102 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.033      ;
; -3.094 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 4.032      ;
; -3.094 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.025      ;
; -3.087 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 4.018      ;
; -3.067 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.997      ;
; -3.055 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 3.993      ;
; -3.049 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 3.980      ;
; -3.032 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.966      ;
; -3.029 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 3.960      ;
; -3.028 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 3.966      ;
; -3.021 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 3.952      ;
; -3.014 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.071     ; 3.945      ;
; -2.997 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.067     ; 3.932      ;
; -2.968 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.063     ; 3.907      ;
; -2.947 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.067     ; 3.882      ;
; -2.929 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.859      ;
; -2.924 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.067     ; 3.859      ;
; -2.895 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.187      ; 4.006      ;
; -2.895 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.187      ; 4.006      ;
; -2.893 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.177      ; 3.994      ;
; -2.888 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.175      ; 3.987      ;
; -2.888 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.186      ; 3.998      ;
; -2.878 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.812      ;
; -2.874 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.067     ; 3.809      ;
; -2.871 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.177      ; 3.972      ;
; -2.857 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.787      ;
; -2.854 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.784      ;
; -2.842 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.776      ;
; -2.832 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.063     ; 3.771      ;
; -2.821 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 3.759      ;
; -2.798 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 3.736      ;
; -2.765 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 3.703      ;
; -2.732 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 3.670      ;
; -2.726 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.660      ;
; -2.688 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.622      ;
; -2.658 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.588      ;
; -2.650 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.580      ;
; -2.635 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.565      ;
; -2.628 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.183      ; 3.850      ;
; -2.623 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.553      ;
; -2.615 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.074     ; 3.543      ;
; -2.602 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.532      ;
; -2.591 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.521      ;
; -2.588 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.522      ;
; -2.582 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.516      ;
; -2.578 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.183      ; 3.800      ;
; -2.539 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.208      ; 3.786      ;
; -2.530 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.171      ; 3.625      ;
; -2.523 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.453      ;
; -2.517 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.183      ; 3.624      ;
; -2.507 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~portb_address_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.189      ; 3.735      ;
; -2.505 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.174      ; 3.603      ;
; -2.504 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.183      ; 3.726      ;
; -2.498 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.063     ; 3.437      ;
; -2.497 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.205      ; 3.626      ;
; -2.494 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.174      ; 3.592      ;
; -2.491 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.169      ; 3.584      ;
; -2.488 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.418      ;
; -2.483 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.417      ;
; -2.481 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.185      ; 3.590      ;
; -2.480 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 3.418      ;
; -2.477 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.192      ; 3.708      ;
; -2.475 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.182      ; 3.581      ;
; -2.470 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.187      ; 3.696      ;
; -2.463 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.180      ; 3.567      ;
; -2.451 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.381      ;
; -2.450 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.380      ;
; -2.446 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.181      ; 3.666      ;
; -2.443 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.072     ; 3.373      ;
; -2.440 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.211      ; 3.690      ;
; -2.436 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.370      ;
; -2.432 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.183      ; 3.654      ;
; -2.430 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.193      ; 3.662      ;
; -2.424 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.193      ; 3.656      ;
; -2.422 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.064     ; 3.360      ;
; -2.419 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.193      ; 3.651      ;
; -2.413 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.192      ; 3.644      ;
; -2.403 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.080     ; 3.325      ;
; -2.398 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.068     ; 3.332      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                                                                                                      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                       ; To Node                                                                                                                        ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -2.792 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.067     ; 3.727      ;
; -2.777 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.067     ; 3.712      ;
; -2.607 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.204      ; 3.735      ;
; -2.607 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.204      ; 3.735      ;
; -2.607 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.067     ; 3.542      ;
; -2.588 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.198      ; 3.710      ;
; -2.588 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.198      ; 3.710      ;
; -2.586 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.205      ; 3.715      ;
; -2.586 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.205      ; 3.715      ;
; -2.565 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.196      ; 3.685      ;
; -2.565 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.196      ; 3.685      ;
; -2.558 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.194      ; 3.676      ;
; -2.558 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.194      ; 3.676      ;
; -2.556 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.200      ; 3.680      ;
; -2.556 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.200      ; 3.680      ;
; -2.545 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.200      ; 3.669      ;
; -2.545 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.200      ; 3.669      ;
; -2.538 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.070     ; 3.470      ;
; -2.530 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.209      ; 3.778      ;
; -2.529 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.202      ; 3.655      ;
; -2.529 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.202      ; 3.655      ;
; -2.506 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.202      ; 3.632      ;
; -2.506 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.202      ; 3.632      ;
; -2.503 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.204      ; 3.631      ;
; -2.503 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.204      ; 3.631      ;
; -2.496 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.205      ; 3.625      ;
; -2.496 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.205      ; 3.625      ;
; -2.482 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.067     ; 3.417      ;
; -2.481 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_msb_aeb                                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.071     ; 3.412      ;
; -2.480 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.073     ; 3.409      ;
; -2.470 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.203      ; 3.597      ;
; -2.470 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.203      ; 3.597      ;
; -2.446 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.199      ; 3.684      ;
; -2.444 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.193      ; 3.561      ;
; -2.444 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.193      ; 3.561      ;
; -2.437 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.067     ; 3.372      ;
; -2.434 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.072     ; 3.364      ;
; -2.427 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.072     ; 3.357      ;
; -2.426 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.205      ; 3.670      ;
; -2.422 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.067     ; 3.357      ;
; -2.417 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.193      ; 3.534      ;
; -2.417 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.193      ; 3.534      ;
; -2.413 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.199      ; 3.651      ;
; -2.412 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.203      ; 3.539      ;
; -2.412 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.203      ; 3.539      ;
; -2.407 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.198      ; 3.644      ;
; -2.395 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.198      ; 3.632      ;
; -2.394 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.203      ; 3.636      ;
; -2.394 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.208      ; 3.641      ;
; -2.391 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.188      ; 3.503      ;
; -2.391 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.188      ; 3.503      ;
; -2.388 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.201      ; 3.628      ;
; -2.384 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.194      ; 3.502      ;
; -2.384 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.194      ; 3.502      ;
; -2.376 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.205      ; 3.620      ;
; -2.374 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.208      ; 3.621      ;
; -2.370 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.073     ; 3.299      ;
; -2.368 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.210      ; 3.617      ;
; -2.366 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.072     ; 3.296      ;
; -2.364 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.194      ; 3.482      ;
; -2.364 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.194      ; 3.482      ;
; -2.363 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.201      ; 3.603      ;
; -2.359 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[11]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.211      ; 3.494      ;
; -2.359 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.211      ; 3.494      ;
; -2.358 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.207      ; 3.604      ;
; -2.358 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.190      ; 3.472      ;
; -2.358 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.190      ; 3.472      ;
; -2.358 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[23]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.183      ; 3.465      ;
; -2.358 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.183      ; 3.465      ;
; -2.356 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.209      ; 3.604      ;
; -2.352 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.199      ; 3.590      ;
; -2.352 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.205      ; 3.596      ;
; -2.346 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.198      ; 3.583      ;
; -2.345 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.210      ; 3.594      ;
; -2.344 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.200      ; 3.583      ;
; -2.344 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.211      ; 3.594      ;
; -2.344 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[4]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.193      ; 3.461      ;
; -2.344 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.193      ; 3.461      ;
; -2.341 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.207      ; 3.587      ;
; -2.339 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.193      ; 3.571      ;
; -2.339 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.199      ; 3.577      ;
; -2.337 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.207      ; 3.583      ;
; -2.334 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.198      ; 3.571      ;
; -2.330 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.210      ; 3.579      ;
; -2.329 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.210      ; 3.578      ;
; -2.326 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[6]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.188      ; 3.438      ;
; -2.326 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.188      ; 3.438      ;
; -2.326 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.190      ; 3.440      ;
; -2.326 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.190      ; 3.440      ;
; -2.320 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.208      ; 3.567      ;
; -2.320 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.203      ; 3.562      ;
; -2.320 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.208      ; 3.567      ;
; -2.318 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.209      ; 3.566      ;
; -2.317 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.195      ; 3.551      ;
; -2.314 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.209      ; 3.562      ;
; -2.314 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.201      ; 3.554      ;
; -2.310 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.208      ; 3.557      ;
; -2.304 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.210      ; 3.553      ;
; -2.302 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.200      ; 3.541      ;
; -2.302 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.205      ; 3.546      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                                                                                                                                ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.464 ; uberACync:Sink|FifoOutAna[19]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.406      ; 2.242      ;
; -1.436 ; uberACync:Sink|FifoOutAna[22]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.415      ; 2.279      ;
; -1.433 ; uberACync:Sink|FifoOutAna[21]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.413      ; 2.280      ;
; -1.432 ; uberACync:Sink|FifoOutAna[35]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.406      ; 2.274      ;
; -1.423 ; uberACync:Sink|FifoOutAna[6]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.281      ;
; -1.416 ; uberACync:Sink|FifoOutAna[34]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.288      ;
; -1.413 ; uberACync:Sink|FifoOutAna[37]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.413      ; 2.300      ;
; -1.411 ; uberACync:Sink|FifoOutAna[49]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.416      ; 2.305      ;
; -1.409 ; uberACync:Sink|FifoOutAna[40]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.417      ; 2.308      ;
; -1.401 ; uberACync:Sink|FifoOutAna[17]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.406      ; 2.305      ;
; -1.399 ; uberACync:Sink|FifoOutAna[33]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.406      ; 2.307      ;
; -1.394 ; uberACync:Sink|FifoOutAna[11]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.310      ;
; -1.393 ; uberACync:Sink|FifoOutAna[39]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.405      ; 2.312      ;
; -1.391 ; uberACync:Sink|FifoOutAna[46]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.390      ; 2.299      ;
; -1.386 ; uberACync:Sink|FifoOutAna[8]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.413      ; 2.327      ;
; -1.384 ; uberACync:Sink|FifoOutAna[7]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.407      ; 2.323      ;
; -1.375 ; uberACync:Sink|FifoOutAna[32]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.423      ; 2.348      ;
; -1.374 ; uberACync:Sink|FifoOutAna[23]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.405      ; 2.331      ;
; -1.373 ; uberACync:Sink|FifoOutAna[1]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.416      ; 2.343      ;
; -1.372 ; uberACync:Sink|FifoOutAna[4]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.407      ; 2.335      ;
; -1.368 ; uberACync:Sink|FifoOutAna[25]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.418      ; 2.350      ;
; -1.367 ; uberACync:Sink|FifoOutAna[56]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.413      ; 2.346      ;
; -1.365 ; uberACync:Sink|FifoOutAna[55]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.407      ; 2.342      ;
; -1.363 ; uberACync:Sink|FifoOutAna[38]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.415      ; 2.352      ;
; -1.359 ; uberACync:Sink|FifoOutAna[43]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.405      ; 2.346      ;
; -1.358 ; uberACync:Sink|FifoOutAna[12]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.423      ; 2.365      ;
; -1.355 ; uberACync:Sink|FifoOutAna[26]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.409      ; 2.354      ;
; -1.355 ; uberACync:Sink|FifoOutAna[42]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.409      ; 2.354      ;
; -1.352 ; uberACync:Sink|FifoOutAna[14]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.408      ; 2.356      ;
; -1.348 ; uberACync:Sink|FifoOutAna[16]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.423      ; 2.375      ;
; -1.348 ; uberACync:Sink|FifoOutAna[15]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.356      ;
; -1.342 ; uberACync:Sink|FifoOutAna[52]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.401      ; 2.359      ;
; -1.340 ; uberACync:Sink|FifoOutAna[63]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.364      ;
; -1.339 ; uberACync:Sink|FifoOutAna[54]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.365      ;
; -1.338 ; uberACync:Sink|FifoOutAna[62]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.408      ; 2.370      ;
; -1.335 ; uberACync:Sink|FifoOutAna[45]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.405      ; 2.370      ;
; -1.331 ; uberACync:Sink|FifoOutAna[24]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.417      ; 2.386      ;
; -1.330 ; uberACync:Sink|FifoOutAna[2]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.407      ; 2.377      ;
; -1.326 ; uberACync:Sink|FifoOutAna[58]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.402      ; 2.376      ;
; -1.321 ; uberACync:Sink|FifoOutAna[59]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.383      ;
; -1.320 ; uberACync:Sink|FifoOutAna[27]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.405      ; 2.385      ;
; -1.319 ; uberACync:Sink|FifoOutAna[10]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.402      ; 2.383      ;
; -1.317 ; uberACync:Sink|FifoOutAna[51]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.387      ;
; -1.314 ; uberACync:Sink|FifoOutAna[3]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.390      ;
; -1.290 ; uberACync:Sink|FifoOutAna[30]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.390      ; 2.400      ;
; -1.289 ; uberACync:Sink|FifoOutAna[20]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.415      ;
; -1.286 ; uberACync:Sink|FifoOutAna[18]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.418      ;
; -1.286 ; uberACync:Sink|FifoOutAna[31]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.392      ; 2.406      ;
; -1.283 ; uberACync:Sink|FifoOutAna[61]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.421      ;
; -1.279 ; uberACync:Sink|FifoOutAna[5]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.411      ; 2.432      ;
; -1.272 ; uberACync:Sink|FifoOutAna[29]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.405      ; 2.433      ;
; -1.271 ; uberACync:Sink|FifoOutAna[53]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.411      ; 2.440      ;
; -1.264 ; uberACync:Sink|FifoOutAna[60]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.423      ; 2.459      ;
; -1.258 ; uberACync:Sink|FifoOutAna[50]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.407      ; 2.449      ;
; -1.254 ; uberACync:Sink|FifoOutAna[36]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.450      ;
; -1.250 ; uberACync:Sink|FifoOutAna[13]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.404      ; 2.454      ;
; -1.249 ; uberACync:Sink|FifoOutAna[41]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.418      ; 2.469      ;
; -1.239 ; uberACync:Sink|FifoOutAna[57]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.406      ; 2.467      ;
; -1.199 ; uberACync:Sink|FifoOutAna[48]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.408      ; 2.509      ;
; -1.164 ; uberACync:Sink|FifoOutAna[47]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.392      ; 2.528      ;
; -1.154 ; uberACync:Sink|FifoOutAna[28]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.398      ; 2.544      ;
; -1.149 ; uberACync:Sink|FifoOutAna[0]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.408      ; 2.559      ;
; -1.108 ; uberACync:Sink|FifoOutAna[44]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.398      ; 2.590      ;
; -1.012 ; uberACync:Sink|FifoOutAna[9]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.406      ; 2.694      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.450  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.716      ;
; 0.471  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.737      ;
; 0.472  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.072      ; 0.739      ;
; 0.472  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.072      ; 0.739      ;
; 0.473  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.739      ;
; 0.474  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.740      ;
; 0.489  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.755      ;
; 0.580  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.846      ;
; 0.601  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.867      ;
; 0.632  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.898      ;
; 0.647  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.913      ;
; 0.648  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.914      ;
; 0.649  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.072      ; 0.916      ;
; 0.651  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.917      ;
; 0.655  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.921      ;
; 0.657  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.923      ;
; 0.665  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.072      ; 0.932      ;
; 0.668  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.070      ; 0.933      ;
; 0.714  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.071      ; 0.980      ;
; 0.724  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.421      ; 1.375      ;
; 0.735  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.422      ; 1.387      ;
; 0.737  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.424      ; 1.391      ;
; 0.740  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.423      ; 1.393      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.429 ; uberACync:Sink|FifosClear                                                                                                         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.644      ;
; -1.429 ; uberACync:Sink|FifosClear                                                                                                         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.644      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.453  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.719      ;
; 0.455  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.721      ;
; 0.471  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.737      ;
; 0.472  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.738      ;
; 0.537  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.346      ; 1.113      ;
; 0.542  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.346      ; 1.118      ;
; 0.543  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.346      ; 1.119      ;
; 0.550  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.346      ; 1.126      ;
; 0.577  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.345      ; 1.152      ;
; 0.588  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.348      ; 1.166      ;
; 0.608  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.346      ; 1.184      ;
; 0.624  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.890      ;
; 0.648  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.915      ;
; 0.648  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.915      ;
; 0.652  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.919      ;
; 0.653  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.919      ;
; 0.655  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.922      ;
; 0.665  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.932      ;
; 0.667  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.934      ;
; 0.674  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.940      ;
; 0.675  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.941      ;
; 0.695  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.961      ;
; 0.716  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.982      ;
; 0.716  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 0.982      ;
; 0.728  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 0.995      ;
; 0.733  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.349      ; 1.312      ;
; 0.734  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.001      ;
; 0.741  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.007      ;
; 0.745  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.012      ;
; 0.751  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.018      ;
; 0.752  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.019      ;
; 0.754  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.020      ;
; 0.756  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.023      ;
; 0.758  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.024      ;
; 0.764  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.030      ;
; 0.777  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.043      ;
; 0.800  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.066      ;
; 0.815  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.082      ;
; 0.823  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.341      ; 1.394      ;
; 0.831  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.098      ;
; 0.835  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.349      ; 1.414      ;
; 0.838  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.104      ;
; 0.845  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.343      ; 1.418      ;
; 0.848  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.343      ; 1.421      ;
; 0.848  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.346      ; 1.424      ;
; 0.848  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]                                               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.115      ;
; 0.848  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.114      ;
; 0.849  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.116      ;
; 0.853  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.354      ; 1.437      ;
; 0.856  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.349      ; 1.435      ;
; 0.857  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.352      ; 1.439      ;
; 0.857  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.068      ; 1.120      ;
; 0.858  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.356      ; 1.444      ;
; 0.862  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.354      ; 1.446      ;
; 0.862  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.351      ; 1.443      ;
; 0.863  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.343      ; 1.436      ;
; 0.869  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.346      ; 1.445      ;
; 0.870  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.137      ;
; 0.872  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.351      ; 1.453      ;
; 0.872  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.343      ; 1.445      ;
; 0.873  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.140      ;
; 0.874  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.353      ; 1.457      ;
; 0.875  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.348      ; 1.453      ;
; 0.875  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.353      ; 1.458      ;
; 0.877  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.359      ; 1.466      ;
; 0.878  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.343      ; 1.451      ;
; 0.881  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.351      ; 1.462      ;
; 0.882  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.352      ; 1.464      ;
; 0.884  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.071      ; 1.150      ;
; 0.885  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.354      ; 1.469      ;
; 0.888  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.359      ; 1.477      ;
; 0.895  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.347      ; 1.472      ;
; 0.896  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.163      ;
; 0.898  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.343      ; 1.471      ;
; 0.902  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.341      ; 1.473      ;
; 0.903  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.346      ; 1.479      ;
; 0.903  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.347      ; 1.480      ;
; 0.904  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.343      ; 1.477      ;
; 0.908  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.338      ; 1.476      ;
; 0.910  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.072      ; 1.177      ;
; 0.911  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.351      ; 1.492      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.394 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.961      ; 1.867      ;
; -1.389 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.971      ; 1.882      ;
; -1.376 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.968      ; 1.892      ;
; -1.364 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.970      ; 1.906      ;
; -1.355 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.969      ; 1.914      ;
; -1.320 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.986      ; 1.966      ;
; -1.317 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.976      ; 1.959      ;
; -1.299 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.972      ; 1.973      ;
; -1.291 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.972      ; 1.981      ;
; -1.282 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.967      ; 1.985      ;
; -1.281 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.982      ; 2.001      ;
; -1.271 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.971      ; 2.000      ;
; -1.267 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.971      ; 2.004      ;
; -1.266 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.988      ; 2.022      ;
; -1.263 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.976      ; 2.013      ;
; -1.241 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.962      ; 2.021      ;
; -1.232 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.966      ; 2.034      ;
; -1.221 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.981      ; 2.060      ;
; -1.201 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.978      ; 2.077      ;
; -1.201 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.975      ; 2.074      ;
; -1.199 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.977      ; 2.078      ;
; -1.196 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.981      ; 2.085      ;
; -1.174 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.977      ; 2.103      ;
; -1.162 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.969      ; 2.107      ;
; -1.150 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.984      ; 2.134      ;
; -1.133 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.983      ; 2.150      ;
; -1.117 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.967      ; 2.150      ;
; -1.117 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.958      ; 2.141      ;
; -1.089 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.964      ; 2.175      ;
; -1.087 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.968      ; 2.181      ;
; -1.022 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.968      ; 2.246      ;
; -1.003 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.969      ; 2.266      ;
; 0.381  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.417      ; 1.028      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.462  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.417      ; 1.109      ;
; 0.470  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.737      ;
; 0.471  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.738      ;
; 0.471  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.738      ;
; 0.471  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.738      ;
; 0.471  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.738      ;
; 0.472  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.417      ; 1.119      ;
; 0.474  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.417      ; 1.121      ;
; 0.474  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.740      ;
; 0.489  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.756      ;
; 0.503  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.417      ; 1.150      ;
; 0.511  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.777      ;
; 0.582  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.849      ;
; 0.599  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.866      ;
; 0.614  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.881      ;
; 0.615  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.882      ;
; 0.629  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.895      ;
; 0.645  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.912      ;
; 0.646  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.913      ;
; 0.646  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.913      ;
; 0.647  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.913      ;
; 0.648  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.421      ; 1.299      ;
; 0.650  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.916      ;
; 0.658  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.417      ; 1.305      ;
; 0.679  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 0.945      ;
; 0.680  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.947      ;
; 0.686  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.416      ; 1.332      ;
; 0.686  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.423      ; 1.339      ;
; 0.686  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.953      ;
; 0.693  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.420      ; 1.343      ;
; 0.696  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.963      ;
; 0.701  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.420      ; 1.351      ;
; 0.703  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.421      ; 1.354      ;
; 0.712  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.420      ; 1.362      ;
; 0.712  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.422      ; 1.364      ;
; 0.716  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.421      ; 1.367      ;
; 0.722  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.417      ; 1.369      ;
; 0.722  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.989      ;
; 0.729  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.996      ;
; 0.729  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.996      ;
; 0.732  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.410      ; 1.372      ;
; 0.732  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.999      ;
; 0.732  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 0.999      ;
; 0.733  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.416      ; 1.379      ;
; 0.734  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.419      ; 1.383      ;
; 0.735  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 1.002      ;
; 0.741  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 1.008      ;
; 0.741  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.072      ; 1.008      ;
; 0.744  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.071      ; 1.010      ;
; 0.745  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.414      ; 1.389      ;
; 0.747  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.423      ; 1.400      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                      ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                           ; To Node                             ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; -0.429 ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.563      ; 0.669      ;
; -0.424 ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.558      ; 0.669      ;
; -0.423 ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.557      ; 0.669      ;
; -0.405 ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.563      ; 0.693      ;
; -0.400 ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.558      ; 0.693      ;
; -0.399 ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.557      ; 0.693      ;
; 0.191  ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.546      ; 1.272      ;
; 0.200  ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.546      ; 1.281      ;
; 0.402  ; uberACync:Sink|AdcConvert           ; uberACync:Sink|AdcConvert           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|DacWr                ; uberACync:Sink|DacWr                ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotStart             ; uberACync:Sink|PotStart             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|DacLoad              ; uberACync:Sink|DacLoad              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[6]            ; uberACync:Sink|PotBuf[6]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[5]            ; uberACync:Sink|PotBuf[5]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[4]            ; uberACync:Sink|PotBuf[4]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[3]            ; uberACync:Sink|PotBuf[3]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[2]            ; uberACync:Sink|PotBuf[2]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[1]            ; uberACync:Sink|PotBuf[1]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[0]            ; uberACync:Sink|PotBuf[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[7]            ; uberACync:Sink|PotBuf[7]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[8]            ; uberACync:Sink|PotBuf[8]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; uberACync:Sink|PotBuf[11]           ; uberACync:Sink|PotBuf[11]           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403  ; uberACync:Sink|ExtendOut[0]         ; uberACync:Sink|ExtendOut[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|ExtendOut[1]         ; uberACync:Sink|ExtendOut[1]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|PreloadAna[1]        ; uberACync:Sink|PreloadAna[1]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|PreloadAna[2]        ; uberACync:Sink|PreloadAna[2]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|PreloadAna[0]        ; uberACync:Sink|PreloadAna[0]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|PreloadDig[0]        ; uberACync:Sink|PreloadDig[0]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|PreloadDig[2]        ; uberACync:Sink|PreloadDig[2]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|FifosClear           ; uberACync:Sink|FifosClear           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|StateMode.011        ; uberACync:Sink|StateMode.011        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|StateMode.101        ; uberACync:Sink|StateMode.101        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|AtZeroCrossing       ; uberACync:Sink|AtZeroCrossing       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|StateZero.11         ; uberACync:Sink|StateZero.11         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|StateZero.01         ; uberACync:Sink|StateZero.01         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|StateZero.00         ; uberACync:Sink|StateZero.00         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|AdcClk               ; uberACync:Sink|AdcClk               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|PotBuf[10]           ; uberACync:Sink|PotBuf[10]           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; uberACync:Sink|PotBuf[9]            ; uberACync:Sink|PotBuf[9]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.417  ; uberACync:Sink|Clk3662Hz[0]         ; uberACync:Sink|Clk3662Hz[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.684      ;
; 0.418  ; uberACync:Sink|CtrPot[0]            ; uberACync:Sink|CtrPot[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.448  ; uberACync:Sink|PrbsShift[15]        ; uberACync:Sink|PrbsShift[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.715      ;
; 0.470  ; uberACync:Sink|PotBuf[4]            ; uberACync:Sink|PhaseDelayTime[12]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470  ; uberACync:Sink|PotBuf[2]            ; uberACync:Sink|PhaseDelayTime[10]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.737      ;
; 0.471  ; uberACync:Sink|PotBuf[6]            ; uberACync:Sink|PhaseDelayTime[14]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471  ; uberACync:Sink|PotBuf[3]            ; uberACync:Sink|PhaseDelayTime[11]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471  ; uberACync:Sink|PotBuf[1]            ; uberACync:Sink|PhaseDelayTime[9]    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.738      ;
; 0.479  ; uberACync:Sink|PotBuf[7]            ; uberACync:Sink|PhaseDelayTime[15]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.746      ;
; 0.479  ; uberACync:Sink|PotBuf[8]            ; uberACync:Sink|PhaseDelayTime[16]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.746      ;
; 0.488  ; uberACync:Sink|StateMode.010        ; uberACync:Sink|FifosClear           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.754      ;
; 0.598  ; uberACync:Sink|PrbsShift[12]        ; uberACync:Sink|PrbsShift[13]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.865      ;
; 0.599  ; uberACync:Sink|PrbsShift[13]        ; uberACync:Sink|PrbsShift[14]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.866      ;
; 0.600  ; uberACync:Sink|PrbsShift[5]         ; uberACync:Sink|PrbsShift[6]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.867      ;
; 0.601  ; uberACync:Sink|PrbsShift[14]        ; uberACync:Sink|PrbsShift[15]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.868      ;
; 0.601  ; uberACync:Sink|PrbsShift[6]         ; uberACync:Sink|PrbsShift[7]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.868      ;
; 0.604  ; uberACync:Sink|PreloadDig[0]        ; uberACync:Sink|PreloadDig[1]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.870      ;
; 0.616  ; uberACync:Sink|PrbsShift[8]         ; uberACync:Sink|PrbsShift[9]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.883      ;
; 0.620  ; uberACync:Sink|PrbsShift[0]         ; uberACync:Sink|PrbsShift[1]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.887      ;
; 0.630  ; uberACync:Sink|StateMode.011        ; uberACync:Sink|StateMode.100        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.896      ;
; 0.646  ; uberACync:Sink|PotBuf[5]            ; uberACync:Sink|PhaseDelayTime[13]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646  ; uberACync:Sink|PotBuf[0]            ; uberACync:Sink|PhaseDelayTime[8]    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.913      ;
; 0.654  ; uberACync:Sink|PotBuf[11]           ; uberACync:Sink|PhaseDelayTime[19]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.921      ;
; 0.669  ; uberACync:Sink|DigInBuf[4]          ; uberACync:Sink|DigOut[4]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.936      ;
; 0.669  ; uberACync:Sink|DigInBuf[0]          ; uberACync:Sink|DigOut[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.936      ;
; 0.689  ; uberACync:Sink|PrbsShift[1]         ; uberACync:Sink|PrbsShift[2]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.690  ; uberACync:Sink|PrbsShift[11]        ; uberACync:Sink|PrbsShift[12]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690  ; uberACync:Sink|PrbsShift[9]         ; uberACync:Sink|PrbsShift[10]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690  ; uberACync:Sink|PrbsShift[7]         ; uberACync:Sink|PrbsShift[8]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.691  ; uberACync:Sink|PrbsShift[4]         ; uberACync:Sink|PrbsShift[5]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.691  ; uberACync:Sink|PrbsShift[3]         ; uberACync:Sink|PrbsShift[4]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.691  ; uberACync:Sink|PrbsShift[2]         ; uberACync:Sink|PrbsShift[3]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.692  ; uberACync:Sink|DelayTimer[8]        ; uberACync:Sink|DelayTimer[8]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.959      ;
; 0.692  ; uberACync:Sink|DelayTimer[10]       ; uberACync:Sink|DelayTimer[10]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.959      ;
; 0.692  ; uberACync:Sink|Clk3662Hz[4]         ; uberACync:Sink|Clk3662Hz[4]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.959      ;
; 0.692  ; uberACync:Sink|RetriggerInhibit[9]  ; uberACync:Sink|RetriggerInhibit[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.959      ;
; 0.692  ; uberACync:Sink|RetriggerInhibit[8]  ; uberACync:Sink|RetriggerInhibit[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.959      ;
; 0.693  ; uberACync:Sink|DelayTimer[13]       ; uberACync:Sink|DelayTimer[13]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693  ; uberACync:Sink|DelayTimer[7]        ; uberACync:Sink|DelayTimer[7]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693  ; uberACync:Sink|RetriggerInhibit[13] ; uberACync:Sink|RetriggerInhibit[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693  ; uberACync:Sink|RetriggerInhibit[7]  ; uberACync:Sink|RetriggerInhibit[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693  ; uberACync:Sink|RetriggerInhibit[6]  ; uberACync:Sink|RetriggerInhibit[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.694  ; uberACync:Sink|DelayTimer[12]       ; uberACync:Sink|DelayTimer[12]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; uberACync:Sink|DelayTimer[6]        ; uberACync:Sink|DelayTimer[6]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; uberACync:Sink|DelayTimer[4]        ; uberACync:Sink|DelayTimer[4]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; uberACync:Sink|Clk3662Hz[10]        ; uberACync:Sink|Clk3662Hz[10]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; uberACync:Sink|Clk3662Hz[2]         ; uberACync:Sink|Clk3662Hz[2]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; uberACync:Sink|RetriggerInhibit[16] ; uberACync:Sink|RetriggerInhibit[16] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; uberACync:Sink|RetriggerInhibit[12] ; uberACync:Sink|RetriggerInhibit[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; uberACync:Sink|RetriggerInhibit[5]  ; uberACync:Sink|RetriggerInhibit[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; uberACync:Sink|RetriggerInhibit[2]  ; uberACync:Sink|RetriggerInhibit[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.695  ; uberACync:Sink|DelayTimer[14]       ; uberACync:Sink|DelayTimer[14]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695  ; uberACync:Sink|DelayTimer[5]        ; uberACync:Sink|DelayTimer[5]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695  ; uberACync:Sink|RetriggerInhibit[15] ; uberACync:Sink|RetriggerInhibit[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695  ; uberACync:Sink|RetriggerInhibit[14] ; uberACync:Sink|RetriggerInhibit[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695  ; uberACync:Sink|RetriggerInhibit[4]  ; uberACync:Sink|RetriggerInhibit[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.696  ; uberACync:Sink|DelayTimer[18]       ; uberACync:Sink|DelayTimer[18]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696  ; uberACync:Sink|DelayTimer[15]       ; uberACync:Sink|DelayTimer[15]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696  ; uberACync:Sink|DelayTimer[11]       ; uberACync:Sink|DelayTimer[11]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696  ; uberACync:Sink|Clk3662Hz[6]         ; uberACync:Sink|Clk3662Hz[6]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696  ; uberACync:Sink|Clk3662Hz[5]         ; uberACync:Sink|Clk3662Hz[5]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                                                                                                         ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.669      ;
; 0.471 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.737      ;
; 0.472 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.738      ;
; 0.473 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.739      ;
; 0.502 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.768      ;
; 0.505 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.771      ;
; 0.506 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.772      ;
; 0.512 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.350      ; 1.092      ;
; 0.514 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.350      ; 1.094      ;
; 0.531 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.349      ; 1.110      ;
; 0.560 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.349      ; 1.139      ;
; 0.561 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.350      ; 1.141      ;
; 0.572 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.350      ; 1.152      ;
; 0.577 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.350      ; 1.157      ;
; 0.603 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.869      ;
; 0.615 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.881      ;
; 0.620 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.886      ;
; 0.658 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.924      ;
; 0.664 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.930      ;
; 0.668 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.934      ;
; 0.687 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.953      ;
; 0.687 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.953      ;
; 0.711 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 0.977      ;
; 0.746 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.352      ; 1.328      ;
; 0.754 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.020      ;
; 0.766 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.032      ;
; 0.771 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.037      ;
; 0.773 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.039      ;
; 0.803 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.069      ;
; 0.811 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.077      ;
; 0.816 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.073      ; 1.084      ;
; 0.831 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.350      ; 1.411      ;
; 0.843 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.109      ;
; 0.851 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.351      ; 1.432      ;
; 0.856 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.122      ;
; 0.867 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.133      ;
; 0.867 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.133      ;
; 0.873 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.069      ; 1.137      ;
; 0.875 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.351      ; 1.456      ;
; 0.878 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.364      ; 1.472      ;
; 0.878 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.072      ; 1.145      ;
; 0.881 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.070      ; 1.146      ;
; 0.885 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.151      ;
; 0.888 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.365      ; 1.483      ;
; 0.891 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.157      ;
; 0.895 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.365      ; 1.490      ;
; 0.901 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.167      ;
; 0.905 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.171      ;
; 0.907 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.349      ; 1.486      ;
; 0.907 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.070      ; 1.172      ;
; 0.913 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.179      ;
; 0.917 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.183      ;
; 0.924 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.190      ;
; 0.932 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.069      ; 1.196      ;
; 0.940 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.206      ;
; 0.946 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.212      ;
; 0.951 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.070      ; 1.216      ;
; 0.954 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.072      ; 1.221      ;
; 0.959 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.225      ;
; 0.969 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.235      ;
; 0.980 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.351      ; 1.561      ;
; 0.998 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.264      ;
; 1.022 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.350      ; 1.602      ;
; 1.029 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.072      ; 1.296      ;
; 1.041 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.070      ; 1.306      ;
; 1.042 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.072      ; 1.309      ;
; 1.053 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.069      ; 1.317      ;
; 1.054 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.068      ; 1.317      ;
; 1.056 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.069      ; 1.320      ;
; 1.058 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.350      ; 1.638      ;
; 1.059 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.325      ;
; 1.060 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.326      ;
; 1.064 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.330      ;
; 1.080 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.351      ; 1.661      ;
; 1.081 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.070      ; 1.346      ;
; 1.086 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.353      ; 1.669      ;
; 1.087 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.069      ; 1.351      ;
; 1.105 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.367      ; 1.702      ;
; 1.105 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.371      ;
; 1.110 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.072      ; 1.377      ;
; 1.111 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.365      ; 1.706      ;
; 1.112 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.365      ; 1.707      ;
; 1.112 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.378      ;
; 1.119 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.070      ; 1.384      ;
; 1.119 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.071      ; 1.385      ;
; 1.126 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.073      ; 1.394      ;
; 1.130 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.072      ; 1.397      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.049      ; 3.050      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.049      ; 3.050      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.049      ; 3.050      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.051      ; 3.052      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.051      ; 3.052      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.051      ; 3.052      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.049      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.051      ; 3.052      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.052      ; 3.053      ;
; -1.077 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.051      ; 3.052      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.048      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.048      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.048      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.048      ; 3.048      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
; -1.076 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 2.046      ; 3.046      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                   ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                        ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.527      ;
; -0.935 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.527      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.754      ; 3.534      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.754      ; 3.534      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.745      ; 3.525      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.745      ; 3.525      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.526      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.526      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.756      ; 3.536      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.756      ; 3.536      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[11]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.747      ; 3.527      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.747      ; 3.527      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[27]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.748      ; 3.528      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[43]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.748      ; 3.528      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.750      ; 3.530      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.750      ; 3.530      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.744      ; 3.524      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.744      ; 3.524      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.738      ; 3.518      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.738      ; 3.518      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[23]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.735      ; 3.515      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.735      ; 3.515      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.752      ; 3.532      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.752      ; 3.532      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[4]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.745      ; 3.525      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.745      ; 3.525      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.742      ; 3.522      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.742      ; 3.522      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.740      ; 3.520      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.740      ; 3.520      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.755      ; 3.535      ;
; -0.934 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.755      ; 3.535      ;
; -0.929 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.748      ; 3.523      ;
; -0.929 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.748      ; 3.523      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.756      ; 3.530      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.756      ; 3.530      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.738      ; 3.512      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.738      ; 3.512      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.745      ; 3.519      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.745      ; 3.519      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.757      ; 3.531      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.757      ; 3.531      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.757      ; 3.531      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.757      ; 3.531      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.757      ; 3.531      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.757      ; 3.531      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.755      ; 3.529      ;
; -0.928 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.755      ; 3.529      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.745      ; 3.518      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.745      ; 3.518      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.742      ; 3.515      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.742      ; 3.515      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[6]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.740      ; 3.513      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.740      ; 3.513      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.744      ; 3.517      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[51]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.744      ; 3.517      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.519      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.519      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.754      ; 3.527      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.754      ; 3.527      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[17]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.519      ;
; -0.927 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.519      ;
; -0.926 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.752      ; 3.524      ;
; -0.926 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.752      ; 3.524      ;
; -0.875 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.752      ; 3.588      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.760      ; 3.595      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.751      ; 3.586      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.752      ; 3.587      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.762      ; 3.597      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.753      ; 3.588      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.754      ; 3.589      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.756      ; 3.591      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.750      ; 3.585      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.744      ; 3.579      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.741      ; 3.576      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.758      ; 3.593      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.751      ; 3.586      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.748      ; 3.583      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.581      ;
; -0.874 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.761      ; 3.596      ;
; -0.869 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.754      ; 3.584      ;
; -0.868 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.762      ; 3.591      ;
; -0.868 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.744      ; 3.573      ;
; -0.868 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.751      ; 3.580      ;
; -0.868 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.763      ; 3.592      ;
; -0.868 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.763      ; 3.592      ;
; -0.868 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.763      ; 3.592      ;
; -0.868 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.761      ; 3.590      ;
; -0.867 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.751      ; 3.579      ;
; -0.867 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.748      ; 3.576      ;
; -0.867 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.746      ; 3.574      ;
; -0.867 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.750      ; 3.578      ;
; -0.867 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.752      ; 3.580      ;
; -0.867 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.760      ; 3.588      ;
; -0.867 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.752      ; 3.580      ;
; -0.866 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.758      ; 3.585      ;
; -0.649 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.466      ; 3.039      ;
; -0.649 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.467      ; 3.040      ;
; -0.649 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.467      ; 3.040      ;
; -0.649 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 2.466      ; 3.039      ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                     ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.458      ; 3.040      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.458      ; 3.040      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.455      ; 3.037      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.036      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.458      ; 3.040      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.457      ; 3.039      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.458      ; 3.040      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.458      ; 3.040      ;
; -0.658 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.458      ; 3.040      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.035      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.035      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.453      ; 3.034      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.453      ; 3.034      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.453      ; 3.034      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.453      ; 3.034      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.459      ; 3.040      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.459      ; 3.040      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.459      ; 3.040      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.459      ; 3.040      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.459      ; 3.040      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.454      ; 3.035      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.452      ; 3.033      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.452      ; 3.033      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.453      ; 3.034      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.453      ; 3.034      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.453      ; 3.034      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.456      ; 3.037      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.452      ; 3.033      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.456      ; 3.037      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.453      ; 3.034      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.456      ; 3.037      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.456      ; 3.037      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.459      ; 3.040      ;
; -0.657 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 2.459      ; 3.040      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.228 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.449      ; 3.523      ;
; -0.228 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.466      ; 3.540      ;
; -0.228 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.461      ; 3.535      ;
; -0.228 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.464      ; 3.538      ;
; -0.227 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.453      ; 3.526      ;
; -0.227 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.455      ; 3.528      ;
; -0.227 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.447      ; 3.520      ;
; -0.227 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.459      ; 3.532      ;
; -0.227 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.467      ; 3.540      ;
; -0.227 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.467      ; 3.540      ;
; -0.227 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.463      ; 3.536      ;
; -0.227 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.466      ; 3.539      ;
; -0.226 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.455      ; 3.527      ;
; -0.226 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.452      ; 3.524      ;
; -0.222 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.475      ; 3.543      ;
; -0.222 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.474      ; 3.542      ;
; -0.222 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.475      ; 3.543      ;
; -0.221 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.474      ; 3.541      ;
; -0.221 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.473      ; 3.540      ;
; -0.221 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.469      ; 3.536      ;
; -0.221 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.461      ; 3.528      ;
; -0.221 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.471      ; 3.538      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.465      ; 3.531      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.458      ; 3.524      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.460      ; 3.526      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.465      ; 3.531      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.455      ; 3.521      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.463      ; 3.529      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.464      ; 3.530      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.467      ; 3.533      ;
; -0.220 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.463      ; 3.529      ;
; -0.219 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.452      ; 3.517      ;
; -0.168 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.455      ; 3.584      ;
; -0.168 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.472      ; 3.601      ;
; -0.168 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.467      ; 3.596      ;
; -0.168 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.470      ; 3.599      ;
; -0.167 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.459      ; 3.587      ;
; -0.167 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.461      ; 3.589      ;
; -0.167 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.453      ; 3.581      ;
; -0.167 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.465      ; 3.593      ;
; -0.167 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.473      ; 3.601      ;
; -0.167 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.473      ; 3.601      ;
; -0.167 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.469      ; 3.597      ;
; -0.167 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.472      ; 3.600      ;
; -0.166 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.461      ; 3.588      ;
; -0.166 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.458      ; 3.585      ;
; -0.162 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.481      ; 3.604      ;
; -0.162 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.480      ; 3.603      ;
; -0.162 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.481      ; 3.604      ;
; -0.161 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.480      ; 3.602      ;
; -0.161 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.479      ; 3.601      ;
; -0.161 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.475      ; 3.597      ;
; -0.161 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.467      ; 3.589      ;
; -0.161 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.477      ; 3.599      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.471      ; 3.592      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.464      ; 3.585      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.466      ; 3.587      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.471      ; 3.592      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.461      ; 3.582      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.469      ; 3.590      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.470      ; 3.591      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.473      ; 3.594      ;
; -0.160 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.469      ; 3.590      ;
; -0.159 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.458      ; 3.578      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.057  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.183      ; 3.049      ;
; 0.058  ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 3.182      ; 3.048      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                       ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.810      ; 2.886      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.810      ; 2.886      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.810      ; 2.886      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.810      ; 2.886      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.810      ; 2.886      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.810      ; 2.886      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[2]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.189 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.808      ; 2.884      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.805      ; 2.882      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.805      ; 2.882      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.805      ; 2.882      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.805      ; 2.882      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.805      ; 2.882      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.805      ; 2.882      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.188 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.804      ; 2.881      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.181 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.800      ; 2.885      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.180 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 3.799      ; 2.884      ;
; -1.081 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.085      ; 3.304      ;
; -1.081 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.087      ; 3.306      ;
; -1.081 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.082      ; 3.301      ;
; -1.080 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.079      ; 3.299      ;
; -1.079 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.089      ; 3.310      ;
; -1.079 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.073      ; 3.294      ;
; -1.079 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.075      ; 3.296      ;
; -1.078 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 4.090      ; 3.312      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.054      ; 2.876      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.054      ; 2.876      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.054      ; 2.876      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.054      ; 2.876      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.054      ; 2.876      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.054      ; 2.876      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.054      ; 2.876      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.052      ; 2.874      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.051      ; 2.873      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.443 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.053      ; 2.875      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.049      ; 2.872      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.049      ; 2.872      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.049      ; 2.872      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.049      ; 2.872      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.048      ; 2.871      ;
; -0.442 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.049      ; 2.872      ;
; -0.342 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.342      ; 3.300      ;
; -0.342 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.343      ; 3.301      ;
; -0.342 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.337      ; 3.295      ;
; -0.342 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.339      ; 3.297      ;
; -0.342 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.341      ; 3.299      ;
; -0.341 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.342      ; 3.301      ;
; -0.341 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.343      ; 3.302      ;
; -0.340 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.334      ; 3.294      ;
; -0.339 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.330      ; 3.291      ;
; -0.339 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.327      ; 3.288      ;
; -0.339 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.323      ; 3.284      ;
; -0.339 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.325      ; 3.286      ;
; -0.339 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.329      ; 3.290      ;
; -0.339 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.331      ; 3.292      ;
; -0.339 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.331      ; 3.292      ;
; -0.338 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.330      ; 3.292      ;
; -0.336 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.337      ; 3.301      ;
; -0.335 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.332      ; 3.297      ;
; -0.334 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.342      ; 3.308      ;
; -0.334 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.335      ; 3.301      ;
; -0.334 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.331      ; 3.297      ;
; -0.334 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.341      ; 3.307      ;
; -0.333 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.339      ; 3.306      ;
; -0.333 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.325      ; 3.292      ;
; -0.332 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 3.330      ; 3.298      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.040      ; 2.870      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.040      ; 2.870      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.040      ; 2.870      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.040      ; 2.870      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.046      ; 2.876      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.046      ; 2.876      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.046      ; 2.876      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.046      ; 2.876      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.046      ; 2.876      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.040      ; 2.870      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.040      ; 2.870      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.040      ; 2.870      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.043      ; 2.873      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.043      ; 2.873      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.040      ; 2.870      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.043      ; 2.873      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.043      ; 2.873      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.046      ; 2.876      ;
; -0.435 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.046      ; 2.876      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.039      ; 2.870      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.039      ; 2.870      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.039      ; 2.870      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.042      ; 2.873      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.041      ; 2.872      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.876      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.044      ; 2.875      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.876      ;
; -0.434 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.876      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.432 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.878      ;
; -0.431 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.879      ;
; -0.431 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 3.045      ; 2.879      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                      ;
+-------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.619      ; 2.884      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.619      ; 2.884      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.621      ; 2.886      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.621      ; 2.886      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.619      ; 2.884      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.621      ; 2.886      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.621      ; 2.886      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.621      ; 2.886      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.621      ; 2.886      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.622      ; 2.887      ;
; 0.000 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.621      ; 2.886      ;
; 0.001 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.884      ;
; 0.001 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.884      ;
; 0.001 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.884      ;
; 0.001 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.884      ;
; 0.001 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.884      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.617      ; 2.884      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.617      ; 2.884      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.617      ; 2.884      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.617      ; 2.884      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.885      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.885      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.885      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.885      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.885      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.885      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.885      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.618      ; 2.885      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
; 0.002 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 2.615      ; 2.882      ;
+-------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                          ;
+--------+--------------+----------------+------------+-----------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                          ;
+--------+--------------+----------------+------------+-----------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_we_reg        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                    ;
+--------+--------------+----------------+------------+-----------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                         ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                         ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[11]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[17]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[23]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[27]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[43]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[4]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[51]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[6]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                            ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11            ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                         ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                         ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_address_reg0 ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_datain_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_we_reg       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_we_reg        ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_address_reg0  ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_datain_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_we_reg        ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                     ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                    ;
+--------+--------------+----------------+------------+-----------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                            ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                            ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                      ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0   ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9                       ;
; -3.201 ; 1.000        ; 4.201          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[2]                  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ;
; -1.487 ; 1.000        ; 2.487          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'Clk100'                                                                                           ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                      ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+
; 4.849 ; 4.849        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0]           ;
; 4.849 ; 4.849        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|observablevcoout ;
; 4.904 ; 4.904        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; Clk100~input|o                                              ;
; 4.928 ; 4.928        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.000 ; 5.000        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; Clk100~input|i                                              ;
; 5.000 ; 5.000        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; Clk100~input|i                                              ;
; 5.071 ; 5.071        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.096 ; 5.096        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; Clk100~input|o                                              ;
; 5.149 ; 5.149        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0]           ;
; 5.149 ; 5.149        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|observablevcoout ;
; 6.000 ; 10.000       ; 4.000          ; Port Rate        ; Clk100 ; Rise       ; Clk100                                                      ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                                  ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                             ; Clock Edge ; Target                             ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+------------------------------------+
; 8.025 ; 8.241        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacLoad             ;
; 8.025 ; 8.241        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacWr               ;
; 8.025 ; 8.241        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[0]         ;
; 8.025 ; 8.241        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[1]         ;
; 8.025 ; 8.241        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[0]           ;
; 8.025 ; 8.241        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[1]           ;
; 8.025 ; 8.241        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoAnaWrClk        ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[10]          ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[2]           ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[8]           ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[9]           ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[5]         ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[6]         ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[18]      ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[2]       ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[34]      ;
; 8.027 ; 8.243        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[50]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|AdcConvert          ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[10]       ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[11]       ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[12]       ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[13]       ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[1]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[2]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[3]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[4]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[5]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[6]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[7]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[8]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[9]        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacAddr[0]          ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacAddr[1]          ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacAddr[2]          ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacAddr[3]          ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[5]           ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[10]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[11]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[12]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[13]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[14]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[15]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[16]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[17]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[18]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[19]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[20]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[2]         ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoAnaRdClk        ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[10]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[13]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[14]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[15]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[21]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[26]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[29]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[30]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[31]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[37]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[42]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[45]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[46]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[47]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[53]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[58]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[5]       ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[61]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[62]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[63]      ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PhaseDelayTime[15]  ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PhaseDelayTime[16]  ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PhaseDelayTime[17]  ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PhaseDelayTime[18]  ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PhaseDelayTime[19]  ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PotBuf[11]          ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PotBuf[7]           ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PotBuf[8]           ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|PotStart            ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[0] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[1] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[2] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[3] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[4] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[5] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[6] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[7] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[8] ;
; 8.028 ; 8.244        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|RetriggerInhibit[9] ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|AdcClk              ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[0]        ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[0]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[1]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[2]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[3]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[4]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[5]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[6]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[7]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[8]           ;
; 8.029 ; 8.245        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[0]           ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+
; AC60Hz       ; Clk100     ; 2.525 ; 2.779 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc1         ; Clk100     ; 6.039 ; 6.044 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc2         ; Clk100     ; 5.722 ; 5.749 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc3         ; Clk100     ; 3.776 ; 4.182 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc4         ; Clk100     ; 3.910 ; 4.398 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigIn[*]     ; Clk100     ; 5.195 ; 5.373 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[0]    ; Clk100     ; 5.142 ; 5.267 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[1]    ; Clk100     ; 5.195 ; 5.321 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[2]    ; Clk100     ; 4.948 ; 5.018 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[3]    ; Clk100     ; 4.678 ; 4.828 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[4]    ; Clk100     ; 5.185 ; 5.373 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[5]    ; Clk100     ; 4.906 ; 5.021 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[6]    ; Clk100     ; 5.161 ; 5.342 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[7]    ; Clk100     ; 4.904 ; 5.064 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendIn[*]  ; Clk100     ; 2.727 ; 3.004 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[0] ; Clk100     ; 2.650 ; 2.949 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[1] ; Clk100     ; 2.727 ; 3.004 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Master       ; Clk100     ; 2.766 ; 3.067 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotDat       ; Clk100     ; 2.870 ; 3.112 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                   ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+
; AC60Hz       ; Clk100     ; -1.834 ; -2.081 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc1         ; Clk100     ; -3.509 ; -3.570 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc2         ; Clk100     ; -3.900 ; -3.968 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc3         ; Clk100     ; -2.130 ; -2.353 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc4         ; Clk100     ; -1.530 ; -1.705 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigIn[*]     ; Clk100     ; -3.880 ; -4.016 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[0]    ; Clk100     ; -4.321 ; -4.434 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[1]    ; Clk100     ; -4.391 ; -4.512 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[2]    ; Clk100     ; -4.140 ; -4.198 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[3]    ; Clk100     ; -3.880 ; -4.016 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[4]    ; Clk100     ; -4.360 ; -4.537 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[5]    ; Clk100     ; -4.097 ; -4.201 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[6]    ; Clk100     ; -4.357 ; -4.535 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[7]    ; Clk100     ; -4.094 ; -4.243 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendIn[*]  ; Clk100     ; -1.954 ; -2.245 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[0] ; Clk100     ; -1.954 ; -2.245 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[1] ; Clk100     ; -2.027 ; -2.297 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Master       ; Clk100     ; -2.065 ; -2.357 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotDat       ; Clk100     ; -1.431 ; -1.684 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                       ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; AdcClk        ; Clk100     ; 5.130 ; 4.934 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; AdcConvert    ; Clk100     ; 5.200 ; 5.011 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacAddr[*]    ; Clk100     ; 8.161 ; 7.910 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[0]   ; Clk100     ; 5.888 ; 5.511 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[1]   ; Clk100     ; 6.055 ; 5.711 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[2]   ; Clk100     ; 8.161 ; 7.910 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[3]   ; Clk100     ; 5.428 ; 5.208 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacDat[*]     ; Clk100     ; 8.968 ; 8.860 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[0]    ; Clk100     ; 6.051 ; 5.699 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[1]    ; Clk100     ; 5.416 ; 5.193 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[2]    ; Clk100     ; 6.315 ; 5.902 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[3]    ; Clk100     ; 5.551 ; 5.354 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[4]    ; Clk100     ; 6.194 ; 5.932 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[5]    ; Clk100     ; 6.478 ; 6.069 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[6]    ; Clk100     ; 6.725 ; 6.257 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[7]    ; Clk100     ; 7.050 ; 6.452 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[8]    ; Clk100     ; 8.968 ; 8.860 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[9]    ; Clk100     ; 7.413 ; 6.849 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[10]   ; Clk100     ; 7.061 ; 6.516 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[11]   ; Clk100     ; 5.987 ; 5.646 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[12]   ; Clk100     ; 8.213 ; 7.559 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[13]   ; Clk100     ; 6.832 ; 6.460 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[14]   ; Clk100     ; 8.520 ; 7.702 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[15]   ; Clk100     ; 7.345 ; 6.849 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacLoad       ; Clk100     ; 6.695 ; 6.389 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacWr         ; Clk100     ; 6.200 ; 5.868 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigOut[*]     ; Clk100     ; 7.548 ; 7.398 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[0]    ; Clk100     ; 5.112 ; 4.889 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[1]    ; Clk100     ; 5.520 ; 5.302 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[2]    ; Clk100     ; 5.436 ; 5.139 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[3]    ; Clk100     ; 5.289 ; 4.958 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[4]    ; Clk100     ; 7.548 ; 7.398 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[5]    ; Clk100     ; 5.631 ; 5.265 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[6]    ; Clk100     ; 5.970 ; 5.586 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[7]    ; Clk100     ; 6.289 ; 5.828 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendOut[*]  ; Clk100     ; 6.589 ; 6.061 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[0] ; Clk100     ; 6.258 ; 5.911 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[1] ; Clk100     ; 6.589 ; 6.061 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Led           ; Clk100     ; 9.814 ; 9.656 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotClk        ; Clk100     ; 5.043 ; 4.783 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotStart      ; Clk100     ; 4.937 ; 4.685 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Prbs          ; Clk100     ; 7.148 ; 6.450 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                               ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; AdcClk        ; Clk100     ; 4.514 ; 4.324 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; AdcConvert    ; Clk100     ; 4.581 ; 4.398 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacAddr[*]    ; Clk100     ; 4.799 ; 4.585 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[0]   ; Clk100     ; 5.240 ; 4.877 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[1]   ; Clk100     ; 5.400 ; 5.069 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[2]   ; Clk100     ; 7.516 ; 7.279 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[3]   ; Clk100     ; 4.799 ; 4.585 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacDat[*]     ; Clk100     ; 4.788 ; 4.572 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[0]    ; Clk100     ; 5.398 ; 5.057 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[1]    ; Clk100     ; 4.788 ; 4.572 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[2]    ; Clk100     ; 5.652 ; 5.255 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[3]    ; Clk100     ; 4.921 ; 4.730 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[4]    ; Clk100     ; 5.530 ; 5.277 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[5]    ; Clk100     ; 5.809 ; 5.416 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[6]    ; Clk100     ; 6.048 ; 5.597 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[7]    ; Clk100     ; 6.352 ; 5.777 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[8]    ; Clk100     ; 8.286 ; 8.188 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[9]    ; Clk100     ; 6.707 ; 6.164 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[10]   ; Clk100     ; 6.365 ; 5.841 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[11]   ; Clk100     ; 5.335 ; 5.006 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[12]   ; Clk100     ; 7.472 ; 6.842 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[13]   ; Clk100     ; 6.146 ; 5.787 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[14]   ; Clk100     ; 7.767 ; 6.980 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[15]   ; Clk100     ; 6.639 ; 6.162 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacLoad       ; Clk100     ; 6.014 ; 5.719 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacWr         ; Clk100     ; 5.540 ; 5.219 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigOut[*]     ; Clk100     ; 4.495 ; 4.279 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[0]    ; Clk100     ; 4.495 ; 4.279 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[1]    ; Clk100     ; 4.887 ; 4.675 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[2]    ; Clk100     ; 4.806 ; 4.520 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[3]    ; Clk100     ; 4.664 ; 4.345 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[4]    ; Clk100     ; 6.926 ; 6.786 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[5]    ; Clk100     ; 4.993 ; 4.640 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[6]    ; Clk100     ; 5.318 ; 4.947 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[7]    ; Clk100     ; 5.624 ; 5.180 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendOut[*]  ; Clk100     ; 5.596 ; 5.261 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[0] ; Clk100     ; 5.596 ; 5.261 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[1] ; Clk100     ; 5.914 ; 5.404 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Led           ; Clk100     ; 5.717 ; 5.362 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotClk        ; Clk100     ; 4.429 ; 4.177 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotStart      ; Clk100     ; 4.327 ; 4.083 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Prbs          ; Clk100     ; 6.450 ; 5.778 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+


----------------
; MTBF Summary ;
----------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Synchronizer Summary                                                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+
; Source Node                                                                              ; Synchronization Node                                                                                                              ; Typical MTBF (Years) ; Included in Design MTBF ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                    ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                    ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]   ; Not Calculated       ; Yes                     ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+


Synchronizer Chain #1: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -4.613         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9] ;                ;              ;                  ; -1.451       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9] ;                ;              ;                  ; -3.162       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #2: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.944         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0] ;                ;              ;                  ; -0.877       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0] ;                ;              ;                  ; -3.067       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #3: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -3.910         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;                ;              ;                  ; -0.882       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ;                ;              ;                  ; -3.028       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #4: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.872         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8] ;                ;              ;                  ; -1.140       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8] ;                ;              ;                  ; -2.732       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #5: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.866         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1] ;                ;              ;                  ; -1.231       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1] ;                ;              ;                  ; -2.635       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #6: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -3.560         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;                ;              ;                  ; -0.075       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ;                ;              ;                  ; -3.485       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #7: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.552         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ;                ;              ;                  ; -1.256       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ;                ;              ;                  ; -2.296       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #8: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.520         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1] ;                ;              ;                  ; -1.490       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1] ;                ;              ;                  ; -2.030       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #9: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -3.479         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;                ;              ;                  ; -0.228       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ;                ;              ;                  ; -3.251       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #10: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -3.445         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;                ;              ;                  ; -0.059       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ;                ;              ;                  ; -3.386       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #11: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.440         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2] ;                ;              ;                  ; -0.583       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2] ;                ;              ;                  ; -2.857       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #12: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.388         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4] ;                ;              ;                  ; -0.231       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4] ;                ;              ;                  ; -3.157       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #13: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.149         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0] ;                ;              ;                  ; -0.940       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0] ;                ;              ;                  ; -2.209       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #14: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.139         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5] ;                ;              ;                  ; -0.616       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5] ;                ;              ;                  ; -2.523       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #15: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -3.133         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;                ;              ;                  ; 0.137        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ;                ;              ;                  ; -3.270       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #16: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -3.128         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7] ;                ;              ;                  ; -0.540       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7] ;                ;              ;                  ; -2.588       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #17: Worst-Case MTBF is Not Calculated
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                          ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                 ;
; Included in Design MTBF ; Yes                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                        ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                           ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                            ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                    ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                    ; -3.086         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                       ; 125            ;              ;                  ;              ;
; Source Clock                                                                                    ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                           ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
; Synchronization Registers                                                                       ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;                ;              ;                  ; -3.086       ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #18: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.976         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6] ;                ;              ;                  ; -0.848       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6] ;                ;              ;                  ; -2.128       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #19: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.774         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7] ;                ;              ;                  ; -0.941       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7] ;                ;              ;                  ; -1.833       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #20: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.744         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2] ;                ;              ;                  ; -0.262       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2] ;                ;              ;                  ; -2.482       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #21: Worst-Case MTBF is Not Calculated
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                          ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                 ;
; Included in Design MTBF ; Yes                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                        ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                           ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                            ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                    ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                    ; -2.712         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                       ; 125            ;              ;                  ;              ;
; Source Clock                                                                                    ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                           ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
; Synchronization Registers                                                                       ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;                ;              ;                  ; -2.712       ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #22: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.700         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7] ;                ;              ;                  ; 0.134        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7] ;                ;              ;                  ; -2.834       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #23: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.660         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9] ;                ;              ;                  ; -0.534       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9] ;                ;              ;                  ; -2.126       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #24: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.650         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ;                ;              ;                  ; -0.075       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ;                ;              ;                  ; -2.575       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #25: Worst-Case MTBF is Not Calculated
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                           ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                  ;
; Included in Design MTBF ; Yes                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                     ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                     ; -2.625         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                              ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
; Synchronization Registers                                                                        ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;                ;              ;                  ; -2.625       ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #26: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.589         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ;                ;              ;                  ; -0.618       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ;                ;              ;                  ; -1.971       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #27: Worst-Case MTBF is Not Calculated
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                           ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                  ;
; Included in Design MTBF ; Yes                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                     ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                     ; -2.537         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                              ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
; Synchronization Registers                                                                        ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;                ;              ;                  ; -2.537       ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #28: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.520         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5] ;                ;              ;                  ; -0.072       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5] ;                ;              ;                  ; -2.448       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #29: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.504         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6] ;                ;              ;                  ; -0.228       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6] ;                ;              ;                  ; -2.276       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #30: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.479         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3] ;                ;              ;                  ; 0.136        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3] ;                ;              ;                  ; -2.615       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #31: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.470         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3] ;                ;              ;                  ; 0.137        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3] ;                ;              ;                  ; -2.607       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #32: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.450         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ;                ;              ;                  ; 0.134        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ;                ;              ;                  ; -2.584       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #33: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.369         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1] ;                ;              ;                  ; -0.084       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1] ;                ;              ;                  ; -2.285       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #34: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.348         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ;                ;              ;                  ; -0.407       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ;                ;              ;                  ; -1.941       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #35: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.306         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ;                ;              ;                  ; -0.036       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ;                ;              ;                  ; -2.270       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #36: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.302         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3] ;                ;              ;                  ; -0.073       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3] ;                ;              ;                  ; -2.229       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #37: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.259         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;                ;              ;                  ; -0.074       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ;                ;              ;                  ; -2.185       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #38: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -2.239         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ;                ;              ;                  ; -0.606       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ;                ;              ;                  ; -1.633       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #39: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.191         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5] ;                ;              ;                  ; -0.056       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5] ;                ;              ;                  ; -2.135       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #40: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.145         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0] ;                ;              ;                  ; -0.229       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0] ;                ;              ;                  ; -1.916       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #41: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.074         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6] ;                ;              ;                  ; -0.277       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6] ;                ;              ;                  ; -1.797       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #42: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -2.019         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4] ;                ;              ;                  ; 0.135        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4] ;                ;              ;                  ; -2.154       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #43: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -2.008         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4] ;                ;              ;                  ; 0.136        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4] ;                ;              ;                  ; -2.144       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #44: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -1.997         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2] ;                ;              ;                  ; -0.056       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2] ;                ;              ;                  ; -1.941       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #45: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.934         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7] ;                ;              ;                  ; 0.136        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7] ;                ;              ;                  ; -2.070       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #46: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.922         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8] ;                ;              ;                  ; -0.038       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8] ;                ;              ;                  ; -1.884       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #47: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -1.896         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ;                ;              ;                  ; -0.543       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ;                ;              ;                  ; -1.353       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #48: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.866         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0] ;                ;              ;                  ; 0.135        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0] ;                ;              ;                  ; -2.001       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #49: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -1.863         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ;                ;              ;                  ; 0.136        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ;                ;              ;                  ; -1.999       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #50: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -1.850         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ;                ;              ;                  ; 0.135        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ;                ;              ;                  ; -1.985       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #51: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.845         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5] ;                ;              ;                  ; -0.071       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5] ;                ;              ;                  ; -1.774       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #52: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.793         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8] ;                ;              ;                  ; 0.134        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8] ;                ;              ;                  ; -1.927       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #53: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -1.763         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ;                ;              ;                  ; 0.135        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ;                ;              ;                  ; -1.898       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #54: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -1.749         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ;                ;              ;                  ; 0.134        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ;                ;              ;                  ; -1.883       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #55: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.728         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9] ;                ;              ;                  ; 0.134        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9] ;                ;              ;                  ; -1.862       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #56: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.673         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4] ;                ;              ;                  ; -0.072       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4] ;                ;              ;                  ; -1.601       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #57: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.607         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6] ;                ;              ;                  ; -0.219       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6] ;                ;              ;                  ; -1.388       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #58: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -1.544         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9] ;                ;              ;                  ; -0.071       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9] ;                ;              ;                  ; -1.473       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #59: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.530         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2] ;                ;              ;                  ; -0.199       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2] ;                ;              ;                  ; -1.331       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #60: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.491         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3] ;                ;              ;                  ; 0.135        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3] ;                ;              ;                  ; -1.626       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #61: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -1.482         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8] ;                ;              ;                  ; -0.074       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8] ;                ;              ;                  ; -1.408       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #62: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -1.474         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1] ;                ;              ;                  ; 0.137        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1] ;                ;              ;                  ; -1.611       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



+----------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                         ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; -3.811 ; -85.142       ;
; uberACync:Sink|FifoDigWrClk                       ; -2.387 ; -274.970      ;
; uberACync:Sink|FifoAnaWrClk                       ; -1.780 ; -192.249      ;
; uberACync:Sink|FifoDigRdClk                       ; -1.158 ; -48.569       ;
; uberACync:Sink|FifoAnaRdClk                       ; -0.834 ; -64.166       ;
+---------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                          ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; uberACync:Sink|FifoDigRdClk                       ; -1.072 ; -2.144        ;
; uberACync:Sink|FifoAnaWrClk                       ; -1.036 ; -31.545       ;
; uberACync:Sink|FifoDigWrClk                       ; -1.026 ; -30.252       ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; -0.031 ; -0.089        ;
; uberACync:Sink|FifoAnaRdClk                       ; 0.186  ; 0.000         ;
+---------------------------------------------------+--------+---------------+


+------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                ;
+-----------------------------+--------+---------------+
; Clock                       ; Slack  ; End Point TNS ;
+-----------------------------+--------+---------------+
; uberACync:Sink|FifoDigWrClk ; -0.408 ; -35.417       ;
; uberACync:Sink|FifoAnaRdClk ; -0.323 ; -43.788       ;
; uberACync:Sink|FifoAnaWrClk ; -0.209 ; -14.982       ;
; uberACync:Sink|FifoDigRdClk ; 0.003  ; 0.000         ;
+-----------------------------+--------+---------------+


+------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                 ;
+-----------------------------+--------+---------------+
; Clock                       ; Slack  ; End Point TNS ;
+-----------------------------+--------+---------------+
; uberACync:Sink|FifoDigRdClk ; -0.814 ; -124.558      ;
; uberACync:Sink|FifoAnaRdClk ; -0.466 ; -77.261       ;
; uberACync:Sink|FifoAnaWrClk ; -0.458 ; -32.959       ;
; uberACync:Sink|FifoDigWrClk ; -0.252 ; -21.880       ;
+-----------------------------+--------+---------------+


+----------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                           ;
+---------------------------------------------------+--------+---------------+
; Clock                                             ; Slack  ; End Point TNS ;
+---------------------------------------------------+--------+---------------+
; uberACync:Sink|FifoDigWrClk                       ; -1.000 ; -183.000      ;
; uberACync:Sink|FifoAnaRdClk                       ; -1.000 ; -171.000      ;
; uberACync:Sink|FifoAnaWrClk                       ; -1.000 ; -168.000      ;
; uberACync:Sink|FifoDigRdClk                       ; -1.000 ; -160.000      ;
; Clk100                                            ; 4.414  ; 0.000         ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 8.115  ; 0.000         ;
+---------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                    ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                          ; To Node                   ; Launch Clock                ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+
; -3.811 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5        ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.244     ; 1.506      ;
; -3.776 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.609      ;
; -3.750 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.241     ; 1.448      ;
; -3.732 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.259     ; 1.412      ;
; -3.715 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7        ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.258     ; 1.396      ;
; -3.708 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.541      ;
; -3.706 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.539      ;
; -3.692 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.244     ; 1.387      ;
; -3.690 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17       ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.247     ; 1.382      ;
; -3.682 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0        ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.245     ; 1.376      ;
; -3.681 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.514      ;
; -3.661 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.494      ;
; -3.658 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.252     ; 1.345      ;
; -3.650 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.260     ; 1.329      ;
; -3.650 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.250     ; 1.339      ;
; -3.649 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.260     ; 1.328      ;
; -3.639 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.472      ;
; -3.630 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.463      ;
; -3.618 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1        ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.247     ; 1.310      ;
; -3.615 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.916     ; 1.638      ;
; -3.613 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.247     ; 1.305      ;
; -3.610 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6        ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.249     ; 1.300      ;
; -3.603 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.257     ; 1.285      ;
; -3.602 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25       ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.247     ; 1.294      ;
; -3.578 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4        ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.251     ; 1.266      ;
; -3.556 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.253     ; 1.242      ;
; -3.549 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.905     ; 1.583      ;
; -3.522 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.247     ; 1.214      ;
; -3.521 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27       ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.254     ; 1.206      ;
; -3.516 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16       ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.246     ; 1.209      ;
; -3.516 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.349      ;
; -3.514 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.905     ; 1.548      ;
; -3.512 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.345      ;
; -3.511 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3        ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.252     ; 1.198      ;
; -3.508 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[3]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.106     ; 1.341      ;
; -3.505 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13       ; uberACync:Sink|DigOut[5]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.244     ; 1.200      ;
; -3.505 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9        ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.242     ; 1.202      ;
; -3.493 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.113     ; 1.319      ;
; -3.487 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31       ; uberACync:Sink|DigOut[7]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.255     ; 1.171      ;
; -3.486 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30       ; uberACync:Sink|DigOut[6]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.254     ; 1.171      ;
; -3.478 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.913     ; 1.504      ;
; -3.473 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.917     ; 1.495      ;
; -3.472 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.113     ; 1.298      ;
; -3.456 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.249     ; 1.146      ;
; -3.451 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.907     ; 1.483      ;
; -3.440 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20       ; uberACync:Sink|DigOut[4]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.242     ; 1.137      ;
; -3.440 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.912     ; 1.467      ;
; -3.419 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24       ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.245     ; 1.113      ;
; -3.415 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8        ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.244     ; 1.110      ;
; -3.414 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.907     ; 1.446      ;
; -3.406 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                ; uberACync:Sink|DacDat[3]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.910     ; 1.435      ;
; -3.405 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]               ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.916     ; 1.428      ;
; -3.366 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.907     ; 1.398      ;
; -3.352 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.906     ; 1.385      ;
; -3.348 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.917     ; 1.370      ;
; -3.330 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26       ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.246     ; 1.023      ;
; -3.329 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]               ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.916     ; 1.352      ;
; -3.324 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.912     ; 1.351      ;
; -3.324 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.906     ; 1.357      ;
; -3.304 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]               ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.913     ; 1.330      ;
; -3.283 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2        ; uberACync:Sink|DigOut[2]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.243     ; 0.979      ;
; -3.276 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                ; uberACync:Sink|DacDat[0]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.907     ; 1.308      ;
; -3.264 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.904     ; 1.299      ;
; -3.262 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.909     ; 1.292      ;
; -3.260 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.104     ; 1.095      ;
; -3.255 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.909     ; 1.285      ;
; -3.250 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0] ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.104     ; 1.085      ;
; -3.247 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]               ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.902     ; 1.284      ;
; -3.233 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.913     ; 1.259      ;
; -3.222 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.915     ; 1.246      ;
; -3.220 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.913     ; 1.246      ;
; -3.214 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.904     ; 1.249      ;
; -3.213 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.906     ; 1.246      ;
; -3.206 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]               ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.905     ; 1.240      ;
; -3.204 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.910     ; 1.233      ;
; -3.190 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.903     ; 1.226      ;
; -3.182 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[1]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.104     ; 1.017      ;
; -3.177 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1] ; uberACync:Sink|DigOut[0]  ; uberACync:Sink|FifoDigRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -2.104     ; 1.012      ;
; -3.173 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.904     ; 1.208      ;
; -3.166 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]               ; uberACync:Sink|DacDat[13] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.907     ; 1.198      ;
; -3.145 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                ; uberACync:Sink|DacDat[7]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.905     ; 1.179      ;
; -3.143 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.915     ; 1.167      ;
; -3.137 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]               ; uberACync:Sink|DacDat[15] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.912     ; 1.164      ;
; -3.135 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]               ; uberACync:Sink|DacDat[14] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.909     ; 1.165      ;
; -3.134 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]               ; uberACync:Sink|DacDat[8]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.903     ; 1.170      ;
; -3.133 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]               ; uberACync:Sink|DacDat[10] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.906     ; 1.166      ;
; -3.127 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]               ; uberACync:Sink|DacDat[6]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.916     ; 1.150      ;
; -3.107 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.916     ; 1.130      ;
; -3.106 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.904     ; 1.141      ;
; -3.105 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.900     ; 1.144      ;
; -3.104 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]               ; uberACync:Sink|DacDat[4]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.907     ; 1.136      ;
; -3.100 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]               ; uberACync:Sink|DacDat[13] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.908     ; 1.131      ;
; -3.092 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]               ; uberACync:Sink|DacDat[2]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.909     ; 1.122      ;
; -3.046 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]               ; uberACync:Sink|DacDat[9]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.913     ; 1.072      ;
; -3.041 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]               ; uberACync:Sink|DacDat[12] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.900     ; 1.080      ;
; -3.038 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]               ; uberACync:Sink|DacDat[5]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.910     ; 1.067      ;
; -3.021 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]               ; uberACync:Sink|DacDat[6]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.916     ; 1.044      ;
; -2.986 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]               ; uberACync:Sink|DacDat[3]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.913     ; 1.012      ;
; -2.980 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[17]               ; uberACync:Sink|DacDat[1]  ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.913     ; 1.006      ;
; -2.977 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]               ; uberACync:Sink|DacDat[11] ; uberACync:Sink|FifoAnaRdClk ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.002        ; -1.903     ; 1.013      ;
+--------+--------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------+---------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                                                                         ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -2.387 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.958      ;
; -2.387 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.958      ;
; -2.385 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.435     ; 2.959      ;
; -2.384 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.952      ;
; -2.384 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.952      ;
; -2.382 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.953      ;
; -2.381 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.953      ;
; -2.381 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.953      ;
; -2.381 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.952      ;
; -2.381 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.952      ;
; -2.379 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.434     ; 2.954      ;
; -2.379 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.435     ; 2.953      ;
; -2.378 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.946      ;
; -2.378 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.946      ;
; -2.376 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.947      ;
; -2.375 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.947      ;
; -2.375 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.947      ;
; -2.374 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.945      ;
; -2.374 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.435     ; 2.948      ;
; -2.374 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.945      ;
; -2.373 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.434     ; 2.948      ;
; -2.373 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.941      ;
; -2.373 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.944      ;
; -2.373 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.941      ;
; -2.370 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.941      ;
; -2.370 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.435     ; 2.944      ;
; -2.370 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.941      ;
; -2.369 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.937      ;
; -2.369 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.940      ;
; -2.369 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.937      ;
; -2.366 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.938      ;
; -2.366 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.434     ; 2.941      ;
; -2.366 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.938      ;
; -2.362 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.934      ;
; -2.362 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.434     ; 2.937      ;
; -2.362 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.934      ;
; -2.346 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.917      ;
; -2.346 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.917      ;
; -2.345 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.916      ;
; -2.345 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.435     ; 2.919      ;
; -2.345 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.916      ;
; -2.344 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.435     ; 2.918      ;
; -2.344 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.912      ;
; -2.344 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.915      ;
; -2.344 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.912      ;
; -2.343 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.911      ;
; -2.343 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.911      ;
; -2.341 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.912      ;
; -2.340 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.912      ;
; -2.340 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.912      ;
; -2.338 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.434     ; 2.913      ;
; -2.337 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.907      ;
; -2.337 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.907      ;
; -2.337 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.909      ;
; -2.337 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.434     ; 2.912      ;
; -2.337 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.909      ;
; -2.336 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.909      ;
; -2.336 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.433     ; 2.912      ;
; -2.336 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.909      ;
; -2.335 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.908      ;
; -2.335 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.906      ;
; -2.335 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.906      ;
; -2.334 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.907      ;
; -2.334 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.433     ; 2.910      ;
; -2.334 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.907      ;
; -2.333 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.435     ; 2.907      ;
; -2.333 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.906      ;
; -2.333 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.433     ; 2.909      ;
; -2.333 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.906      ;
; -2.332 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.900      ;
; -2.332 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.900      ;
; -2.331 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.902      ;
; -2.331 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.435     ; 2.905      ;
; -2.331 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.902      ;
; -2.331 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.901      ;
; -2.331 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.901      ;
; -2.330 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.898      ;
; -2.330 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.901      ;
; -2.330 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.441     ; 2.898      ;
; -2.330 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.438     ; 2.901      ;
; -2.329 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.901      ;
; -2.329 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.901      ;
; -2.329 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.902      ;
; -2.329 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.433     ; 2.905      ;
; -2.329 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.902      ;
; -2.329 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.902      ;
; -2.327 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.434     ; 2.902      ;
; -2.323 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.895      ;
; -2.323 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.434     ; 2.898      ;
; -2.323 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.437     ; 2.895      ;
; -2.317 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.887      ;
; -2.317 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.887      ;
; -2.317 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.887      ;
; -2.317 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.887      ;
; -2.315 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.888      ;
; -2.315 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.888      ;
; -2.309 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.882      ;
; -2.309 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.436     ; 2.882      ;
; -2.308 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg       ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.878      ;
; -2.308 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigWrClk ; 1.000        ; -0.439     ; 2.878      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                                                          ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                           ; To Node                                                                                                                        ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -1.780 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.096      ; 2.885      ;
; -1.780 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.096      ; 2.885      ;
; -1.779 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.099      ; 2.887      ;
; -1.769 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.096      ; 2.874      ;
; -1.769 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.096      ; 2.874      ;
; -1.768 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.099      ; 2.876      ;
; -1.754 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.096      ; 2.859      ;
; -1.754 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.096      ; 2.859      ;
; -1.753 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.099      ; 2.861      ;
; -1.753 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.096      ; 2.858      ;
; -1.753 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.096      ; 2.858      ;
; -1.752 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.099      ; 2.860      ;
; -1.729 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.095      ; 2.833      ;
; -1.729 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.095      ; 2.833      ;
; -1.728 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.098      ; 2.835      ;
; -1.718 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.095      ; 2.822      ;
; -1.718 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.095      ; 2.822      ;
; -1.717 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.833      ;
; -1.717 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.833      ;
; -1.717 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.098      ; 2.824      ;
; -1.716 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.110      ; 2.835      ;
; -1.714 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.825      ;
; -1.714 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.825      ;
; -1.713 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.105      ; 2.827      ;
; -1.709 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.822      ;
; -1.709 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.822      ;
; -1.708 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.824      ;
; -1.708 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.817      ;
; -1.708 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.817      ;
; -1.707 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.103      ; 2.819      ;
; -1.706 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.822      ;
; -1.706 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.822      ;
; -1.705 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.110      ; 2.824      ;
; -1.703 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.105      ; 2.817      ;
; -1.703 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.105      ; 2.817      ;
; -1.703 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.095      ; 2.807      ;
; -1.703 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.095      ; 2.807      ;
; -1.703 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.814      ;
; -1.703 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.814      ;
; -1.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.099      ; 2.810      ;
; -1.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.099      ; 2.810      ;
; -1.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.108      ; 2.819      ;
; -1.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.098      ; 2.809      ;
; -1.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.095      ; 2.806      ;
; -1.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.095      ; 2.806      ;
; -1.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.105      ; 2.816      ;
; -1.701 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.812      ;
; -1.701 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.098      ; 2.808      ;
; -1.700 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.810      ;
; -1.700 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.810      ;
; -1.699 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.809      ;
; -1.699 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.809      ;
; -1.699 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.812      ;
; -1.698 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.811      ;
; -1.698 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.811      ;
; -1.698 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.811      ;
; -1.697 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.813      ;
; -1.697 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.806      ;
; -1.697 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.806      ;
; -1.696 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.103      ; 2.808      ;
; -1.692 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.105      ; 2.806      ;
; -1.692 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.105      ; 2.806      ;
; -1.691 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.800      ;
; -1.691 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.800      ;
; -1.691 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.807      ;
; -1.691 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.807      ;
; -1.691 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.099      ; 2.799      ;
; -1.691 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.099      ; 2.799      ;
; -1.691 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.108      ; 2.808      ;
; -1.690 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.103      ; 2.802      ;
; -1.690 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.110      ; 2.809      ;
; -1.690 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.806      ;
; -1.690 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.806      ;
; -1.690 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.801      ;
; -1.690 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.799      ;
; -1.690 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.799      ;
; -1.689 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.110      ; 2.808      ;
; -1.689 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_we_reg        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.799      ;
; -1.689 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.799      ;
; -1.689 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.103      ; 2.801      ;
; -1.688 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.799      ;
; -1.688 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.799      ;
; -1.688 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.798      ;
; -1.688 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.798      ;
; -1.688 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.801      ;
; -1.687 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.105      ; 2.801      ;
; -1.687 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.798      ;
; -1.687 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.102      ; 2.798      ;
; -1.687 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.800      ;
; -1.686 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.105      ; 2.800      ;
; -1.683 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.098      ; 2.790      ;
; -1.683 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.098      ; 2.790      ;
; -1.683 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.796      ;
; -1.683 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.104      ; 2.796      ;
; -1.682 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.101      ; 2.792      ;
; -1.682 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.098      ; 2.789      ;
; -1.682 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.098      ; 2.789      ;
; -1.682 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.107      ; 2.798      ;
; -1.682 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_we_reg       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.791      ;
; -1.682 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaWrClk ; 1.000        ; 0.100      ; 2.791      ;
+--------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                                                                                                         ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                         ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -1.158 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 2.117      ;
; -1.116 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 2.075      ;
; -1.088 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 2.047      ;
; -1.031 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.990      ;
; -1.012 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.963      ;
; -0.977 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.936      ;
; -0.973 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.924      ;
; -0.950 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.904      ;
; -0.949 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.908      ;
; -0.947 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.906      ;
; -0.940 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.894      ;
; -0.934 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.885      ;
; -0.924 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.878      ;
; -0.922 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.873      ;
; -0.921 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.872      ;
; -0.919 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.870      ;
; -0.911 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.865      ;
; -0.902 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.853      ;
; -0.896 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.855      ;
; -0.890 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.849      ;
; -0.885 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.839      ;
; -0.880 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.831      ;
; -0.867 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.818      ;
; -0.863 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.814      ;
; -0.863 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.814      ;
; -0.862 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.813      ;
; -0.848 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.799      ;
; -0.845 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.799      ;
; -0.834 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.100      ; 1.889      ;
; -0.834 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.788      ;
; -0.833 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.101      ; 1.889      ;
; -0.827 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.090      ; 1.872      ;
; -0.826 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.100      ; 1.881      ;
; -0.824 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.775      ;
; -0.823 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.774      ;
; -0.822 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.091      ; 1.868      ;
; -0.821 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.089      ; 1.865      ;
; -0.809 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.760      ;
; -0.808 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.767      ;
; -0.806 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.765      ;
; -0.806 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.765      ;
; -0.801 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.755      ;
; -0.795 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.746      ;
; -0.786 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.090      ; 1.885      ;
; -0.785 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.739      ;
; -0.784 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.743      ;
; -0.784 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.735      ;
; -0.777 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.736      ;
; -0.769 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5             ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.723      ;
; -0.767 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.718      ;
; -0.765 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.091      ; 1.865      ;
; -0.764 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.723      ;
; -0.763 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.722      ;
; -0.757 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.711      ;
; -0.746 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.700      ;
; -0.731 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.091      ; 1.831      ;
; -0.731 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.091      ; 1.831      ;
; -0.730 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.684      ;
; -0.729 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.683      ;
; -0.721 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.094      ; 1.824      ;
; -0.713 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.672      ;
; -0.705 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.100      ; 1.814      ;
; -0.705 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.656      ;
; -0.702 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~portb_address_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.097      ; 1.808      ;
; -0.699 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.039     ; 1.647      ;
; -0.684 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.635      ;
; -0.676 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.630      ;
; -0.673 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.627      ;
; -0.671 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.101      ; 1.781      ;
; -0.670 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.621      ;
; -0.668 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.619      ;
; -0.664 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.106      ; 1.779      ;
; -0.663 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.104      ; 1.776      ;
; -0.654 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.605      ;
; -0.651 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.089      ; 1.749      ;
; -0.649 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.086      ; 1.690      ;
; -0.637 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.097      ; 1.689      ;
; -0.633 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.087      ; 1.675      ;
; -0.630 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.581      ;
; -0.629 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.580      ;
; -0.628 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.106      ; 1.689      ;
; -0.627 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.083      ; 1.665      ;
; -0.622 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.088      ; 1.665      ;
; -0.620 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.100      ; 1.729      ;
; -0.620 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.099      ; 1.674      ;
; -0.615 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.095      ; 1.665      ;
; -0.613 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.572      ;
; -0.612 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.101      ; 1.722      ;
; -0.604 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.558      ;
; -0.601 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0 ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.100      ; 1.710      ;
; -0.601 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                    ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.093      ; 1.649      ;
; -0.601 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.028     ; 1.560      ;
; -0.598 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.552      ;
; -0.597 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                     ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.548      ;
; -0.593 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.090      ; 1.692      ;
; -0.593 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.544      ;
; -0.592 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.036     ; 1.543      ;
; -0.590 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.544      ;
; -0.589 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                        ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; -0.033     ; 1.543      ;
; -0.586 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0  ; uberACync:Sink|FifoDigRdClk ; uberACync:Sink|FifoDigRdClk ; 1.000        ; 0.093      ; 1.688      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                                                                                                      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                       ; To Node                                                                                                                        ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; -0.834 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.945      ;
; -0.813 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.924      ;
; -0.801 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.101      ; 1.911      ;
; -0.786 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.849      ;
; -0.786 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.849      ;
; -0.774 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.889      ;
; -0.764 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.033     ; 1.718      ;
; -0.763 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.033     ; 1.717      ;
; -0.755 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.864      ;
; -0.754 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.109      ; 1.818      ;
; -0.754 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.109      ; 1.818      ;
; -0.746 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.098      ; 1.853      ;
; -0.742 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.799      ;
; -0.742 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.799      ;
; -0.733 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.848      ;
; -0.729 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.842      ;
; -0.729 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.784      ;
; -0.729 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.784      ;
; -0.725 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.105      ; 1.839      ;
; -0.722 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.103      ; 1.834      ;
; -0.719 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.776      ;
; -0.719 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.776      ;
; -0.717 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.776      ;
; -0.717 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.776      ;
; -0.716 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.827      ;
; -0.711 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.099      ; 1.819      ;
; -0.711 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.770      ;
; -0.711 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.770      ;
; -0.708 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.817      ;
; -0.704 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.101      ; 1.814      ;
; -0.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.817      ;
; -0.702 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.033     ; 1.656      ;
; -0.701 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.762      ;
; -0.701 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.762      ;
; -0.698 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.815      ;
; -0.695 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.812      ;
; -0.694 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.101      ; 1.804      ;
; -0.693 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.808      ;
; -0.681 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.109      ; 1.799      ;
; -0.681 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.792      ;
; -0.680 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.796      ;
; -0.680 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.741      ;
; -0.680 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.741      ;
; -0.679 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.103      ; 1.791      ;
; -0.679 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.794      ;
; -0.674 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.783      ;
; -0.671 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.786      ;
; -0.670 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.785      ;
; -0.670 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.098      ; 1.777      ;
; -0.667 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.110      ; 1.786      ;
; -0.666 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.729      ;
; -0.666 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.729      ;
; -0.664 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.105      ; 1.778      ;
; -0.664 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.777      ;
; -0.663 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.772      ;
; -0.661 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.772      ;
; -0.661 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.778      ;
; -0.659 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.105      ; 1.773      ;
; -0.659 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.109      ; 1.723      ;
; -0.659 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.109      ; 1.723      ;
; -0.653 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.762      ;
; -0.652 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                            ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.714      ;
; -0.652 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.714      ;
; -0.652 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.105      ; 1.766      ;
; -0.651 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.109      ; 1.769      ;
; -0.647 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.764      ;
; -0.643 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.103      ; 1.755      ;
; -0.639 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.755      ;
; -0.639 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.754      ;
; -0.638 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.098      ; 1.745      ;
; -0.638 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.749      ;
; -0.637 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.748      ;
; -0.636 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.035     ; 1.588      ;
; -0.634 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.108      ; 1.751      ;
; -0.633 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.744      ;
; -0.629 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.105      ; 1.743      ;
; -0.626 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.033     ; 1.580      ;
; -0.624 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.740      ;
; -0.623 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.038     ; 1.572      ;
; -0.623 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.736      ;
; -0.622 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.684      ;
; -0.622 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.684      ;
; -0.620 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.736      ;
; -0.619 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.728      ;
; -0.618 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.731      ;
; -0.617 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.101      ; 1.727      ;
; -0.609 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.104      ; 1.722      ;
; -0.608 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.719      ;
; -0.608 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.103      ; 1.666      ;
; -0.608 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.103      ; 1.666      ;
; -0.606 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.107      ; 1.722      ;
; -0.605 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.100      ; 1.714      ;
; -0.605 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.033     ; 1.559      ;
; -0.604 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.033     ; 1.558      ;
; -0.603 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.714      ;
; -0.602 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.102      ; 1.713      ;
; -0.601 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                         ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.097      ; 1.707      ;
; -0.599 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; -0.038     ; 1.548      ;
; -0.598 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.106      ; 1.713      ;
; -0.597 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 1.000        ; 0.097      ; 1.703      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.072 ; uberACync:Sink|FifosClear                                                                                                         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.188      ;
; -1.072 ; uberACync:Sink|FifosClear                                                                                                         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.188      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.193  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.037      ; 0.314      ;
; 0.193  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.313      ;
; 0.197  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.317      ;
; 0.199  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.319      ;
; 0.223  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.178      ; 0.505      ;
; 0.224  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.178      ; 0.506      ;
; 0.226  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.178      ; 0.508      ;
; 0.227  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.178      ; 0.509      ;
; 0.239  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.178      ; 0.521      ;
; 0.240  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.180      ; 0.524      ;
; 0.249  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.178      ; 0.531      ;
; 0.264  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.384      ;
; 0.269  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.389      ;
; 0.269  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.389      ;
; 0.272  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.392      ;
; 0.279  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.399      ;
; 0.282  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.402      ;
; 0.283  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.403      ;
; 0.283  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.403      ;
; 0.287  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.407      ;
; 0.291  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.411      ;
; 0.299  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.419      ;
; 0.304  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.424      ;
; 0.308  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.428      ;
; 0.313  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.182      ; 0.599      ;
; 0.314  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.434      ;
; 0.317  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.437      ;
; 0.319  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.439      ;
; 0.324  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                     ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.444      ;
; 0.326  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.446      ;
; 0.329  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.449      ;
; 0.331  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.451      ;
; 0.331  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.451      ;
; 0.331  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.451      ;
; 0.336  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.456      ;
; 0.337  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.037      ; 0.458      ;
; 0.338  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.458      ;
; 0.339  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.459      ;
; 0.341  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.461      ;
; 0.347  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.467      ;
; 0.348  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.037      ; 0.469      ;
; 0.363  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.173      ; 0.640      ;
; 0.367  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.181      ; 0.652      ;
; 0.368  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.488      ;
; 0.368  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.488      ;
; 0.368  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.033      ; 0.485      ;
; 0.369  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.489      ;
; 0.376  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.183      ; 0.663      ;
; 0.377  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.185      ; 0.666      ;
; 0.378  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.183      ; 0.665      ;
; 0.379  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]                                               ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.499      ;
; 0.380  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.180      ; 0.664      ;
; 0.380  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.175      ; 0.659      ;
; 0.381  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.177      ; 0.662      ;
; 0.385  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.174      ; 0.663      ;
; 0.385  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.175      ; 0.664      ;
; 0.386  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.175      ; 0.665      ;
; 0.387  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.188      ; 0.679      ;
; 0.387  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.190      ; 0.681      ;
; 0.387  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.182      ; 0.673      ;
; 0.388  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.186      ; 0.678      ;
; 0.388  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.180      ; 0.672      ;
; 0.388  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.508      ;
; 0.389  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.182      ; 0.675      ;
; 0.389  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.184      ; 0.677      ;
; 0.390  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.175      ; 0.669      ;
; 0.392  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.177      ; 0.673      ;
; 0.393  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.185      ; 0.682      ;
; 0.393  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.183      ; 0.680      ;
; 0.397  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.190      ; 0.691      ;
; 0.397  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.173      ; 0.674      ;
; 0.398  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.036      ; 0.518      ;
; 0.399  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.185      ; 0.688      ;
; 0.401  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.183      ; 0.688      ;
; 0.403  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.188      ; 0.695      ;
; 0.404  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.178      ; 0.686      ;
; 0.406  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.183      ; 0.693      ;
; 0.406  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.175      ; 0.685      ;
; 0.407  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.182      ; 0.693      ;
; 0.408  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.178      ; 0.690      ;
; 0.410  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 0.188      ; 0.702      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                                                                                                                                ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.036 ; uberACync:Sink|FifoOutAna[19]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.942      ; 1.080      ;
; -1.036 ; uberACync:Sink|FifoOutAna[22]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.946      ; 1.084      ;
; -1.033 ; uberACync:Sink|FifoOutAna[21]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.946      ; 1.087      ;
; -1.025 ; uberACync:Sink|FifoOutAna[37]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.946      ; 1.095      ;
; -1.021 ; uberACync:Sink|FifoOutAna[16]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.952      ; 1.105      ;
; -1.021 ; uberACync:Sink|FifoOutAna[34]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.939      ; 1.092      ;
; -1.019 ; uberACync:Sink|FifoOutAna[1]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.946      ; 1.101      ;
; -1.019 ; uberACync:Sink|FifoOutAna[35]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.942      ; 1.097      ;
; -1.016 ; uberACync:Sink|FifoOutAna[6]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.098      ;
; -1.011 ; uberACync:Sink|FifoOutAna[11]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.103      ;
; -1.009 ; uberACync:Sink|FifoOutAna[32]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.952      ; 1.117      ;
; -1.007 ; uberACync:Sink|FifoOutAna[40]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.945      ; 1.112      ;
; -1.006 ; uberACync:Sink|FifoOutAna[49]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.946      ; 1.114      ;
; -1.005 ; uberACync:Sink|FifoOutAna[38]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.946      ; 1.115      ;
; -1.004 ; uberACync:Sink|FifoOutAna[46]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.932      ; 1.102      ;
; -1.000 ; uberACync:Sink|FifoOutAna[8]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.947      ; 1.121      ;
; -0.999 ; uberACync:Sink|FifoOutAna[17]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.942      ; 1.117      ;
; -0.999 ; uberACync:Sink|FifoOutAna[33]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.942      ; 1.117      ;
; -0.998 ; uberACync:Sink|FifoOutAna[39]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.939      ; 1.115      ;
; -0.996 ; uberACync:Sink|FifoOutAna[7]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.942      ; 1.120      ;
; -0.996 ; uberACync:Sink|FifoOutAna[24]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.945      ; 1.123      ;
; -0.995 ; uberACync:Sink|FifoOutAna[4]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.944      ; 1.123      ;
; -0.995 ; uberACync:Sink|FifoOutAna[45]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.946      ; 1.125      ;
; -0.993 ; uberACync:Sink|FifoOutAna[56]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.947      ; 1.128      ;
; -0.987 ; uberACync:Sink|FifoOutAna[14]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.945      ; 1.132      ;
; -0.985 ; uberACync:Sink|FifoOutAna[23]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.939      ; 1.128      ;
; -0.985 ; uberACync:Sink|FifoOutAna[15]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.129      ;
; -0.984 ; uberACync:Sink|FifoOutAna[5]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.944      ; 1.134      ;
; -0.983 ; uberACync:Sink|FifoOutAna[25]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.948      ; 1.139      ;
; -0.982 ; uberACync:Sink|FifoOutAna[55]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.942      ; 1.134      ;
; -0.981 ; uberACync:Sink|FifoOutAna[2]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.943      ; 1.136      ;
; -0.980 ; uberACync:Sink|FifoOutAna[43]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.941      ; 1.135      ;
; -0.979 ; uberACync:Sink|FifoOutAna[42]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.944      ; 1.139      ;
; -0.978 ; uberACync:Sink|FifoOutAna[12]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.953      ; 1.149      ;
; -0.977 ; uberACync:Sink|FifoOutAna[26]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.944      ; 1.141      ;
; -0.977 ; uberACync:Sink|FifoOutAna[62]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.945      ; 1.142      ;
; -0.976 ; uberACync:Sink|FifoOutAna[18]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.939      ; 1.137      ;
; -0.976 ; uberACync:Sink|FifoOutAna[63]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.138      ;
; -0.975 ; uberACync:Sink|FifoOutAna[52]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.941      ; 1.140      ;
; -0.975 ; uberACync:Sink|FifoOutAna[54]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.139      ;
; -0.973 ; uberACync:Sink|FifoOutAna[31]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.935      ; 1.136      ;
; -0.964 ; uberACync:Sink|FifoOutAna[30]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.932      ; 1.142      ;
; -0.961 ; uberACync:Sink|FifoOutAna[59]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.153      ;
; -0.959 ; uberACync:Sink|FifoOutAna[58]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.938      ; 1.153      ;
; -0.959 ; uberACync:Sink|FifoOutAna[27]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.941      ; 1.156      ;
; -0.958 ; uberACync:Sink|FifoOutAna[61]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.945      ; 1.161      ;
; -0.956 ; uberACync:Sink|FifoOutAna[50]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.943      ; 1.161      ;
; -0.956 ; uberACync:Sink|FifoOutAna[3]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.158      ;
; -0.956 ; uberACync:Sink|FifoOutAna[51]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.158      ;
; -0.953 ; uberACync:Sink|FifoOutAna[10]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.938      ; 1.159      ;
; -0.946 ; uberACync:Sink|FifoOutAna[13]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.945      ; 1.173      ;
; -0.944 ; uberACync:Sink|FifoOutAna[20]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.170      ;
; -0.939 ; uberACync:Sink|FifoOutAna[29]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.946      ; 1.181      ;
; -0.938 ; uberACync:Sink|FifoOutAna[60]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.953      ; 1.189      ;
; -0.935 ; uberACync:Sink|FifoOutAna[53]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.944      ; 1.183      ;
; -0.931 ; uberACync:Sink|FifoOutAna[36]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.940      ; 1.183      ;
; -0.924 ; uberACync:Sink|FifoOutAna[57]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.942      ; 1.192      ;
; -0.921 ; uberACync:Sink|FifoOutAna[41]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.948      ; 1.201      ;
; -0.917 ; uberACync:Sink|FifoOutAna[48]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.943      ; 1.200      ;
; -0.901 ; uberACync:Sink|FifoOutAna[47]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.935      ; 1.208      ;
; -0.890 ; uberACync:Sink|FifoOutAna[0]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.943      ; 1.227      ;
; -0.870 ; uberACync:Sink|FifoOutAna[28]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.934      ; 1.238      ;
; -0.848 ; uberACync:Sink|FifoOutAna[44]                                                                                                    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.934      ; 1.260      ;
; -0.834 ; uberACync:Sink|FifoOutAna[9]                                                                                                     ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.942      ; 1.282      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.194  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.314      ;
; 0.194  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.314      ;
; 0.195  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.315      ;
; 0.195  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.315      ;
; 0.195  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.315      ;
; 0.196  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.316      ;
; 0.216  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.336      ;
; 0.253  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.373      ;
; 0.254  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.374      ;
; 0.267  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.387      ;
; 0.267  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.387      ;
; 0.270  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.390      ;
; 0.273  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.393      ;
; 0.280  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.400      ;
; 0.282  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.402      ;
; 0.284  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.404      ;
; 0.284  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.037      ; 0.405      ;
; 0.292  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.412      ;
; 0.308  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.223      ; 0.635      ;
; 0.308  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.036      ; 0.428      ;
; 0.309  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.224      ; 0.637      ;
; 0.316  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.227      ; 0.647      ;
; 0.321  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[8]                                                   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0   ; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 0.223      ; 0.648      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                         ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -1.026 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.736      ; 0.884      ;
; -1.026 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.727      ; 0.875      ;
; -1.015 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.733      ; 0.892      ;
; -1.001 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.733      ; 0.906      ;
; -1.000 ; uberACync:Sink|DigInBuf[0]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.735      ; 0.909      ;
; -0.991 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.736      ; 0.919      ;
; -0.988 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.744      ; 0.930      ;
; -0.985 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.735      ; 0.924      ;
; -0.977 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.747      ; 0.944      ;
; -0.972 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.737      ; 0.939      ;
; -0.972 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.740      ; 0.942      ;
; -0.970 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.731      ; 0.935      ;
; -0.966 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.737      ; 0.945      ;
; -0.962 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.741      ; 0.953      ;
; -0.961 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.736      ; 0.949      ;
; -0.953 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.731      ; 0.952      ;
; -0.945 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.735      ; 0.964      ;
; -0.933 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.744      ; 0.985      ;
; -0.933 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.727      ; 0.968      ;
; -0.929 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.739      ; 0.984      ;
; -0.928 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.743      ; 0.989      ;
; -0.927 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.743      ; 0.990      ;
; -0.925 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.738      ; 0.987      ;
; -0.919 ; uberACync:Sink|DigInBuf[7]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.739      ; 0.994      ;
; -0.917 ; uberACync:Sink|DigInBuf[3]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.742      ; 0.999      ;
; -0.894 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.733      ; 1.013      ;
; -0.889 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.734      ; 1.019      ;
; -0.888 ; uberACync:Sink|DigInBuf[2]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.729      ; 1.015      ;
; -0.878 ; uberACync:Sink|DigInBuf[4]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.723      ; 1.019      ;
; -0.874 ; uberACync:Sink|DigInBuf[1]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.731      ; 1.031      ;
; -0.857 ; uberACync:Sink|DigInBuf[5]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~porta_datain_reg0     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.734      ; 1.051      ;
; -0.851 ; uberACync:Sink|DigInBuf[6]                                                                                                        ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_datain_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.734      ; 1.057      ;
; 0.133  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.218      ; 0.455      ;
; 0.181  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.218      ; 0.503      ;
; 0.182  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.218      ; 0.504      ;
; 0.184  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.218      ; 0.506      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.188  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.307      ;
; 0.194  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.314      ;
; 0.194  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.313      ;
; 0.195  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.314      ;
; 0.195  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.314      ;
; 0.195  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.314      ;
; 0.197  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.316      ;
; 0.207  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.218      ; 0.529      ;
; 0.216  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.335      ;
; 0.217  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.337      ;
; 0.255  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.375      ;
; 0.259  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.379      ;
; 0.261  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.380      ;
; 0.263  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.383      ;
; 0.265  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.223      ; 0.592      ;
; 0.267  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.387      ;
; 0.268  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.387      ;
; 0.268  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.387      ;
; 0.270  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.389      ;
; 0.271  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.390      ;
; 0.280  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.218      ; 0.602      ;
; 0.284  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.404      ;
; 0.286  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.225      ; 0.615      ;
; 0.287  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.407      ;
; 0.290  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.217      ; 0.611      ;
; 0.290  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.410      ;
; 0.291  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.222      ; 0.617      ;
; 0.295  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.415      ;
; 0.296  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.223      ; 0.623      ;
; 0.297  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.223      ; 0.624      ;
; 0.298  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.222      ; 0.624      ;
; 0.298  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.222      ; 0.624      ;
; 0.299  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.223      ; 0.626      ;
; 0.303  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.218      ; 0.625      ;
; 0.303  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.423      ;
; 0.306  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.035      ; 0.425      ;
; 0.308  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.215      ; 0.627      ;
; 0.309  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.220      ; 0.633      ;
; 0.312  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.212      ; 0.628      ;
; 0.316  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.217      ; 0.637      ;
; 0.317  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.437      ;
; 0.317  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.437      ;
; 0.317  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.437      ;
; 0.318  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.438      ;
; 0.319  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0   ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.225      ; 0.648      ;
; 0.319  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.439      ;
; 0.321  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.441      ;
; 0.323  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.443      ;
; 0.323  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 0.036      ; 0.443      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                      ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                           ; To Node                             ; Launch Clock                                      ; Latch Clock                                       ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; -0.031 ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.049      ; 0.307      ;
; -0.030 ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.048      ; 0.307      ;
; -0.028 ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 0.307      ;
; -0.023 ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk         ; uberACync:Sink|FifoDigWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.049      ; 0.315      ;
; -0.022 ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk         ; uberACync:Sink|FifoAnaWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.048      ; 0.315      ;
; -0.020 ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk         ; uberACync:Sink|FifoAnaRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 0.315      ;
; 0.186  ; uberACync:Sink|PotStart             ; uberACync:Sink|PotStart             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; uberACync:Sink|PotBuf[2]            ; uberACync:Sink|PotBuf[2]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; uberACync:Sink|PotBuf[1]            ; uberACync:Sink|PotBuf[1]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; uberACync:Sink|PotBuf[0]            ; uberACync:Sink|PotBuf[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; uberACync:Sink|PotBuf[7]            ; uberACync:Sink|PotBuf[7]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; uberACync:Sink|PotBuf[8]            ; uberACync:Sink|PotBuf[8]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; uberACync:Sink|PotBuf[11]           ; uberACync:Sink|PotBuf[11]           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187  ; uberACync:Sink|ExtendOut[0]         ; uberACync:Sink|ExtendOut[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|ExtendOut[1]         ; uberACync:Sink|ExtendOut[1]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PreloadAna[1]        ; uberACync:Sink|PreloadAna[1]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PreloadAna[2]        ; uberACync:Sink|PreloadAna[2]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PreloadAna[0]        ; uberACync:Sink|PreloadAna[0]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PreloadDig[0]        ; uberACync:Sink|PreloadDig[0]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|FifosClear           ; uberACync:Sink|FifosClear           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|StateMode.011        ; uberACync:Sink|StateMode.011        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|StateMode.101        ; uberACync:Sink|StateMode.101        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|AtZeroCrossing       ; uberACync:Sink|AtZeroCrossing       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|StateZero.11         ; uberACync:Sink|StateZero.11         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|StateZero.01         ; uberACync:Sink|StateZero.01         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|StateZero.00         ; uberACync:Sink|StateZero.00         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|AdcConvert           ; uberACync:Sink|AdcConvert           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|AdcClk               ; uberACync:Sink|AdcClk               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|DacWr                ; uberACync:Sink|DacWr                ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|DacLoad              ; uberACync:Sink|DacLoad              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PotBuf[6]            ; uberACync:Sink|PotBuf[6]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PotBuf[5]            ; uberACync:Sink|PotBuf[5]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PotBuf[4]            ; uberACync:Sink|PotBuf[4]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PotBuf[3]            ; uberACync:Sink|PotBuf[3]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PotBuf[10]           ; uberACync:Sink|PotBuf[10]           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; uberACync:Sink|PotBuf[9]            ; uberACync:Sink|PotBuf[9]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188  ; uberACync:Sink|PreloadDig[2]        ; uberACync:Sink|PreloadDig[2]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.192  ; uberACync:Sink|PotBuf[2]            ; uberACync:Sink|PhaseDelayTime[10]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.313      ;
; 0.193  ; uberACync:Sink|PotBuf[1]            ; uberACync:Sink|PhaseDelayTime[9]    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.194  ; uberACync:Sink|PotBuf[6]            ; uberACync:Sink|PhaseDelayTime[14]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194  ; uberACync:Sink|PotBuf[4]            ; uberACync:Sink|PhaseDelayTime[12]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194  ; uberACync:Sink|PotBuf[3]            ; uberACync:Sink|PhaseDelayTime[11]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194  ; uberACync:Sink|CtrPot[0]            ; uberACync:Sink|CtrPot[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194  ; uberACync:Sink|Clk3662Hz[0]         ; uberACync:Sink|Clk3662Hz[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194  ; uberACync:Sink|PrbsShift[15]        ; uberACync:Sink|PrbsShift[0]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.198  ; uberACync:Sink|PotBuf[7]            ; uberACync:Sink|PhaseDelayTime[15]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.319      ;
; 0.198  ; uberACync:Sink|PotBuf[8]            ; uberACync:Sink|PhaseDelayTime[16]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.319      ;
; 0.216  ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.543      ;
; 0.219  ; uberACync:Sink|StateMode.010        ; uberACync:Sink|FifosClear           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.339      ;
; 0.252  ; uberACync:Sink|PrbsShift[12]        ; uberACync:Sink|PrbsShift[13]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.372      ;
; 0.253  ; uberACync:Sink|PrbsShift[13]        ; uberACync:Sink|PrbsShift[14]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.253  ; uberACync:Sink|PrbsShift[5]         ; uberACync:Sink|PrbsShift[6]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.255  ; uberACync:Sink|PrbsShift[14]        ; uberACync:Sink|PrbsShift[15]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.375      ;
; 0.255  ; uberACync:Sink|PrbsShift[6]         ; uberACync:Sink|PrbsShift[7]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.375      ;
; 0.264  ; uberACync:Sink|PrbsShift[0]         ; uberACync:Sink|PrbsShift[1]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.384      ;
; 0.264  ; uberACync:Sink|PrbsShift[8]         ; uberACync:Sink|PrbsShift[9]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.384      ;
; 0.266  ; uberACync:Sink|PreloadDig[0]        ; uberACync:Sink|PreloadDig[1]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266  ; uberACync:Sink|PotBuf[0]            ; uberACync:Sink|PhaseDelayTime[8]    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.387      ;
; 0.267  ; uberACync:Sink|PotBuf[5]            ; uberACync:Sink|PhaseDelayTime[13]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.269  ; uberACync:Sink|StateMode.011        ; uberACync:Sink|StateMode.100        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.389      ;
; 0.271  ; uberACync:Sink|PotBuf[11]           ; uberACync:Sink|PhaseDelayTime[19]   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.392      ;
; 0.278  ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk         ; uberACync:Sink|FifoDigRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.605      ;
; 0.280  ; uberACync:Sink|DigInBuf[0]          ; uberACync:Sink|DigOut[0]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.400      ;
; 0.281  ; uberACync:Sink|DigInBuf[4]          ; uberACync:Sink|DigOut[4]            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.401      ;
; 0.295  ; uberACync:Sink|PrbsShift[7]         ; uberACync:Sink|PrbsShift[8]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; uberACync:Sink|PrbsShift[4]         ; uberACync:Sink|PrbsShift[5]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; uberACync:Sink|PrbsShift[3]         ; uberACync:Sink|PrbsShift[4]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; uberACync:Sink|PrbsShift[2]         ; uberACync:Sink|PrbsShift[3]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; uberACync:Sink|PrbsShift[1]         ; uberACync:Sink|PrbsShift[2]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296  ; uberACync:Sink|DelayTimer[8]        ; uberACync:Sink|DelayTimer[8]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.417      ;
; 0.296  ; uberACync:Sink|DelayTimer[10]       ; uberACync:Sink|DelayTimer[10]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.417      ;
; 0.296  ; uberACync:Sink|RetriggerInhibit[9]  ; uberACync:Sink|RetriggerInhibit[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.417      ;
; 0.296  ; uberACync:Sink|RetriggerInhibit[8]  ; uberACync:Sink|RetriggerInhibit[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.417      ;
; 0.296  ; uberACync:Sink|PrbsShift[11]        ; uberACync:Sink|PrbsShift[12]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; uberACync:Sink|PrbsShift[9]         ; uberACync:Sink|PrbsShift[10]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.297  ; uberACync:Sink|DelayTimer[13]       ; uberACync:Sink|DelayTimer[13]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; uberACync:Sink|DelayTimer[12]       ; uberACync:Sink|DelayTimer[12]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; uberACync:Sink|DelayTimer[11]       ; uberACync:Sink|DelayTimer[11]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; uberACync:Sink|DelayTimer[7]        ; uberACync:Sink|DelayTimer[7]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; uberACync:Sink|DelayTimer[4]        ; uberACync:Sink|DelayTimer[4]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; uberACync:Sink|RetriggerInhibit[13] ; uberACync:Sink|RetriggerInhibit[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; uberACync:Sink|RetriggerInhibit[7]  ; uberACync:Sink|RetriggerInhibit[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; uberACync:Sink|RetriggerInhibit[6]  ; uberACync:Sink|RetriggerInhibit[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; uberACync:Sink|RetriggerInhibit[2]  ; uberACync:Sink|RetriggerInhibit[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298  ; uberACync:Sink|DelayTimer[18]       ; uberACync:Sink|DelayTimer[18]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|DelayTimer[14]       ; uberACync:Sink|DelayTimer[14]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|DelayTimer[6]        ; uberACync:Sink|DelayTimer[6]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|DelayTimer[5]        ; uberACync:Sink|DelayTimer[5]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|Clk3662Hz[4]         ; uberACync:Sink|Clk3662Hz[4]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; uberACync:Sink|RetriggerInhibit[18] ; uberACync:Sink|RetriggerInhibit[18] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|RetriggerInhibit[16] ; uberACync:Sink|RetriggerInhibit[16] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|RetriggerInhibit[14] ; uberACync:Sink|RetriggerInhibit[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|RetriggerInhibit[12] ; uberACync:Sink|RetriggerInhibit[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|RetriggerInhibit[5]  ; uberACync:Sink|RetriggerInhibit[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; uberACync:Sink|RetriggerInhibit[4]  ; uberACync:Sink|RetriggerInhibit[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.299  ; uberACync:Sink|DelayTimer[15]       ; uberACync:Sink|DelayTimer[15]       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299  ; uberACync:Sink|DelayTimer[3]        ; uberACync:Sink|DelayTimer[3]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299  ; uberACync:Sink|DelayTimer[1]        ; uberACync:Sink|DelayTimer[1]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299  ; uberACync:Sink|Clk3662Hz[10]        ; uberACync:Sink|Clk3662Hz[10]        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; uberACync:Sink|Clk3662Hz[6]         ; uberACync:Sink|Clk3662Hz[6]         ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
+--------+-------------------------------------+-------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                                                                                                         ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                        ; To Node                                                                                                                          ; Launch Clock                ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+
; 0.186 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.315      ;
; 0.205 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.182      ; 0.491      ;
; 0.206 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.182      ; 0.492      ;
; 0.210 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.330      ;
; 0.216 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.181      ; 0.501      ;
; 0.225 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.345      ;
; 0.225 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.345      ;
; 0.233 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.181      ; 0.518      ;
; 0.234 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.182      ; 0.520      ;
; 0.235 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.182      ; 0.521      ;
; 0.235 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.182      ; 0.521      ;
; 0.256 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.376      ;
; 0.262 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.382      ;
; 0.263 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.383      ;
; 0.279 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.399      ;
; 0.281 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.401      ;
; 0.284 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.404      ;
; 0.293 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.413      ;
; 0.308 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.428      ;
; 0.325 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.446      ;
; 0.327 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.184      ; 0.615      ;
; 0.329 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.450      ;
; 0.333 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.454      ;
; 0.334 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.455      ;
; 0.357 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.477      ;
; 0.357 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.477      ;
; 0.358 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.478      ;
; 0.360 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.480      ;
; 0.365 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.038      ; 0.487      ;
; 0.369 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.182      ; 0.655      ;
; 0.370 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.490      ;
; 0.371 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.491      ;
; 0.378 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.183      ; 0.665      ;
; 0.383 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.195      ; 0.682      ;
; 0.383 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.503      ;
; 0.385 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.183      ; 0.672      ;
; 0.387 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.507      ;
; 0.388 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.194      ; 0.686      ;
; 0.390 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.511      ;
; 0.390 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.510      ;
; 0.392 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.512      ;
; 0.392 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.512      ;
; 0.393 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.195      ; 0.692      ;
; 0.393 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.034      ; 0.511      ;
; 0.393 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.514      ;
; 0.394 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.035      ; 0.513      ;
; 0.395 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.516      ;
; 0.398 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.518      ;
; 0.398 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.518      ;
; 0.399 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.520      ;
; 0.403 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.524      ;
; 0.407 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.035      ; 0.526      ;
; 0.419 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.034      ; 0.537      ;
; 0.428 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.548      ;
; 0.432 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.183      ; 0.719      ;
; 0.434 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.555      ;
; 0.436 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.557      ;
; 0.441 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.561      ;
; 0.442 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.562      ;
; 0.446 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.034      ; 0.564      ;
; 0.447 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.568      ;
; 0.449 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.034      ; 0.567      ;
; 0.450 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.181      ; 0.735      ;
; 0.452 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]                                              ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.573      ;
; 0.461 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.182      ; 0.747      ;
; 0.462 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.033      ; 0.579      ;
; 0.462 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.035      ; 0.581      ;
; 0.465 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.585      ;
; 0.478 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.035      ; 0.597      ;
; 0.479 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.035      ; 0.598      ;
; 0.481 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.035      ; 0.600      ;
; 0.488 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.609      ;
; 0.491 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.611      ;
; 0.492 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.039      ; 0.615      ;
; 0.492 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.612      ;
; 0.493 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]                                               ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.614      ;
; 0.493 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.037      ; 0.614      ;
; 0.495 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.182      ; 0.781      ;
; 0.499 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.185      ; 0.788      ;
; 0.500 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0   ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.197      ; 0.801      ;
; 0.500 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.620      ;
; 0.502 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.622      ;
; 0.503 ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; uberACync:Sink|FifoAnaRdClk ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 0.036      ; 0.623      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.408 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.550      ;
; -0.408 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.550      ;
; -0.408 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.550      ;
; -0.408 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.550      ;
; -0.408 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.550      ;
; -0.408 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.550      ;
; -0.408 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.550      ;
; -0.408 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.549      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.549      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.549      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.549      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.235      ; 1.551      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.235      ; 1.551      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.235      ; 1.551      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.235      ; 1.551      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.237      ; 1.553      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.237      ; 1.553      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.237      ; 1.553      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.234      ; 1.550      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.233      ; 1.549      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.238      ; 1.554      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.238      ; 1.554      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.238      ; 1.554      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.236      ; 1.552      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.238      ; 1.554      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.239      ; 1.555      ;
; -0.407 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.002        ; 1.238      ; 1.554      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                   ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                        ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.588      ; 1.788      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[62]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.588      ; 1.788      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.785      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[61]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.785      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.786      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.786      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.590      ; 1.790      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[60]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.590      ; 1.790      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[11]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.784      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[59]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.784      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[27]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.785      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[43]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.785      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.784      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.784      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[8]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.784      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.784      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[23]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.576      ; 1.776      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.576      ; 1.776      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.786      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.786      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.581      ; 1.781      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.581      ; 1.781      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.589      ; 1.789      ;
; -0.323 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.589      ; 1.789      ;
; -0.322 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.582      ; 1.781      ;
; -0.322 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.582      ; 1.781      ;
; -0.322 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[7]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.579      ; 1.778      ;
; -0.322 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.579      ; 1.778      ;
; -0.322 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[4]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.785      ;
; -0.322 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.785      ;
; -0.322 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.583      ; 1.782      ;
; -0.322 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.583      ; 1.782      ;
; -0.318 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.779      ;
; -0.318 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.779      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.590      ; 1.784      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.590      ; 1.784      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.779      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.779      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.579      ; 1.773      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.579      ; 1.773      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.785      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.785      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[6]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.581      ; 1.775      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.581      ; 1.775      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.780      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.780      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.785      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.785      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.589      ; 1.783      ;
; -0.317 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.589      ; 1.783      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.583      ; 1.776      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.583      ; 1.776      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.779      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.779      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.784      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.784      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                            ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.777      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[51]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.777      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.779      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.779      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.588      ; 1.781      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.588      ; 1.781      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[17]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.779      ;
; -0.316 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.779      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.588      ; 1.779      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.776      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a29~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.777      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.590      ; 1.781      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.775      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a27~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.776      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.775      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a8~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.775      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.576      ; 1.767      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.777      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.581      ; 1.772      ;
; -0.260 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.589      ; 1.780      ;
; -0.259 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.582      ; 1.772      ;
; -0.259 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a7~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.579      ; 1.769      ;
; -0.259 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a4~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.776      ;
; -0.259 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.583      ; 1.773      ;
; -0.255 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.770      ;
; -0.254 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.590      ; 1.775      ;
; -0.254 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a31~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.585      ; 1.770      ;
; -0.254 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a28~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.579      ; 1.764      ;
; -0.254 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.776      ;
; -0.254 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a6~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.581      ; 1.766      ;
; -0.254 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.771      ;
; -0.254 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a2~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.776      ;
; -0.254 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.589      ; 1.774      ;
; -0.253 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a30~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.583      ; 1.767      ;
; -0.253 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a9~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.770      ;
; -0.253 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a5~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.591      ; 1.775      ;
; -0.253 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a3~portb_address_reg0  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.584      ; 1.768      ;
; -0.253 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.770      ;
; -0.253 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.588      ; 1.772      ;
; -0.253 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~portb_address_reg0 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.586      ; 1.770      ;
; -0.202 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.438      ; 1.549      ;
; -0.202 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.438      ; 1.549      ;
; -0.202 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.437      ; 1.548      ;
; -0.202 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.002        ; 1.437      ; 1.548      ;
+--------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                     ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.209 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.549      ;
; -0.209 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.549      ;
; -0.209 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.549      ;
; -0.209 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.549      ;
; -0.209 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.549      ;
; -0.209 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.549      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.427      ; 1.544      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.427      ; 1.544      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.426      ; 1.543      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.426      ; 1.543      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.426      ; 1.543      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.426      ; 1.543      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.432      ; 1.549      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.432      ; 1.549      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.432      ; 1.549      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.432      ; 1.549      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.432      ; 1.549      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.427      ; 1.544      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.425      ; 1.542      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.425      ; 1.542      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.426      ; 1.543      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.426      ; 1.543      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.426      ; 1.543      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.429      ; 1.546      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.425      ; 1.542      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.429      ; 1.546      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.426      ; 1.543      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.428      ; 1.545      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.429      ; 1.546      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.431      ; 1.548      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.429      ; 1.546      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.432      ; 1.549      ;
; -0.208 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.002        ; 1.432      ; 1.549      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                     ;
+-------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; 0.003 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.904      ; 1.778      ;
; 0.003 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.909      ; 1.783      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.911      ; 1.784      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.910      ; 1.783      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.912      ; 1.785      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.908      ; 1.781      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.917      ; 1.790      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.917      ; 1.790      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.917      ; 1.790      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.912      ; 1.785      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.915      ; 1.788      ;
; 0.004 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.916      ; 1.789      ;
; 0.005 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.907      ; 1.779      ;
; 0.005 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.914      ; 1.786      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.925      ; 1.792      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.922      ; 1.789      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.914      ; 1.781      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.916      ; 1.783      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.921      ; 1.788      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.927      ; 1.794      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.926      ; 1.793      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.911      ; 1.778      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.927      ; 1.794      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.918      ; 1.785      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.921      ; 1.788      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.922      ; 1.789      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.917      ; 1.784      ;
; 0.010 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.914      ; 1.781      ;
; 0.011 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.924      ; 1.790      ;
; 0.011 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.920      ; 1.786      ;
; 0.011 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.909      ; 1.775      ;
; 0.011 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.920      ; 1.786      ;
; 0.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.904      ; 1.769      ;
; 0.066 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.909      ; 1.774      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a5~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.911      ; 1.775      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.910      ; 1.774      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a28~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.912      ; 1.776      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.908      ; 1.772      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.917      ; 1.781      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.917      ; 1.781      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.917      ; 1.781      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a9~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.912      ; 1.776      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.915      ; 1.779      ;
; 0.067 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.916      ; 1.780      ;
; 0.068 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.907      ; 1.770      ;
; 0.068 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a8~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.914      ; 1.777      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.925      ; 1.783      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.922      ; 1.780      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.914      ; 1.772      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.916      ; 1.774      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.921      ; 1.779      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.927      ; 1.785      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.926      ; 1.784      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.911      ; 1.769      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a29~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.927      ; 1.785      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a4~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.918      ; 1.776      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.921      ; 1.779      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a27~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.922      ; 1.780      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.917      ; 1.775      ;
; 0.073 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.914      ; 1.772      ;
; 0.074 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.924      ; 1.781      ;
; 0.074 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.920      ; 1.777      ;
; 0.074 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~portb_address_reg0   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.909      ; 1.766      ;
; 0.074 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a3~portb_address_reg0    ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.920      ; 1.777      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.124 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.552      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
; 0.125 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.002        ; 1.767      ; 1.551      ;
+-------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                                                                                                       ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.104      ; 1.444      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.109      ; 1.449      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.104      ; 1.444      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.109      ; 1.449      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.104      ; 1.444      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.104      ; 1.444      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.109      ; 1.449      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.104      ; 1.444      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.109      ; 1.449      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.104      ; 1.444      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.109      ; 1.449      ;
; -0.814 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.109      ; 1.449      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[2]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.103      ; 1.444      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|int_rdempty_OTERM17                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.813 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                     ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.106      ; 1.447      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.806 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.446      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.805 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.098      ; 1.447      ;
; -0.787 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.255      ; 1.628      ;
; -0.787 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.254      ; 1.627      ;
; -0.787 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a31                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.252      ; 1.625      ;
; -0.787 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.257      ; 1.630      ;
; -0.786 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.249      ; 1.623      ;
; -0.786 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.244      ; 1.618      ;
; -0.786 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.246      ; 1.620      ;
; -0.786 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a30                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 0.000        ; 2.251      ; 1.625      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.443      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.443      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.443      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.443      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.443      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.751      ; 1.439      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.751      ; 1.439      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.751      ; 1.439      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.751      ; 1.439      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.750      ; 1.438      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.441      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.751      ; 1.439      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.441      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]                                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.443      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.443      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.443      ;
; -0.466 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.754      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.444      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.444      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.444      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]                                               ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.444      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.444      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|int_rdempty_OTERM21                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.444      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.755      ; 1.444      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_msb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdemp_eq_comp_lsb_aeb                                        ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.753      ; 1.442      ;
; -0.465 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.752      ; 1.441      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.906      ; 1.620      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[63]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.906      ; 1.620      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.901      ; 1.615      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.901      ; 1.615      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.907      ; 1.621      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.907      ; 1.621      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[5]                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.907      ; 1.621      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.907      ; 1.621      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.902      ; 1.616      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.902      ; 1.616      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[17]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.902      ; 1.616      ;
; -0.446 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.902      ; 1.616      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.898      ; 1.613      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.898      ; 1.613      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.900      ; 1.615      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.900      ; 1.615      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[9]                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.901      ; 1.616      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.901      ; 1.616      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[6]                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.896      ; 1.611      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.896      ; 1.611      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.902      ; 1.617      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.902      ; 1.617      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.899      ; 1.614      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[51]                             ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.899      ; 1.614      ;
; -0.445 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                              ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 0.000        ; 1.907      ; 1.622      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                                                                                                      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                          ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.743      ; 1.439      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.743      ; 1.439      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.742      ; 1.438      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.742      ; 1.438      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.742      ; 1.438      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.742      ; 1.438      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.743      ; 1.439      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.742      ; 1.438      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.742      ; 1.438      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.742      ; 1.438      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.745      ; 1.441      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.745      ; 1.441      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.742      ; 1.438      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.440      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.745      ; 1.441      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.443      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.745      ; 1.441      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.458 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.748      ; 1.444      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.741      ; 1.438      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.741      ; 1.438      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.741      ; 1.438      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.744      ; 1.441      ;
; -0.457 ; uberACync:Sink|FifosClear ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 0.000        ; 1.747      ; 1.444      ;
+--------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                                                                                                       ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; Slack  ; From Node                 ; To Node                                                                                                                           ; Launch Clock                                      ; Latch Clock                 ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[14]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[15]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.446      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[10]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.446      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[12]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.446      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[13]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.446      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[4]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.548      ; 1.450      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.444      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.449      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.449      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.449      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.449      ;
; -0.252 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.449      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                 ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[11]                                                  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[8]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[9]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.545      ; 1.448      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.545      ; 1.448      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[6]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[5]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[0]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.545      ; 1.448      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[1]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.542      ; 1.445      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[2]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[7]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                           ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.544      ; 1.447      ;
; -0.251 ; uberACync:Sink|FifosClear ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrptr_g[3]                                                   ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 0.000        ; 1.547      ; 1.450      ;
+--------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigWrClk'                                                                                                                                                            ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                            ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a0                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a1                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a10                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a11                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a12                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a13                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a14                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a15                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a2                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a3                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a4                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a5                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a6                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a7                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a8                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|counter8a9                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|parity9                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[0]                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[1]                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[2]                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_7lc:wrptr_g1p|sub_parity10a[3]                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_address_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_datain_reg0     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~porta_we_reg          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_address_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_datain_reg0     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~porta_we_reg          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigWrClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~porta_datain_reg0    ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaRdClk'                                                                                                                                                           ;
+--------+--------------+----------------+------------+-----------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+------------+-----------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a0                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a1                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a10                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM11              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM13              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a11_OTERM9               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a12_OTERM15              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a2                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a3                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a4                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a5                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a6                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a7                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a8                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|counter5a9                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|parity6                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[0]                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[1]                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[2]                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_877:rdptr_g1p|sub_parity7a[3]                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[0]                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[10]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[11]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[12]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[13]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[14]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[15]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[16]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[17]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[18]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[19]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[1]                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[20]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[21]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[22]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[23]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[24]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[25]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[26]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[27]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[28]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[29]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[2]                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[30]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[31]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[32]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[33]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[34]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[35]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[36]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[37]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[38]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[39]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[3]                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[40]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[41]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[42]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[43]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[44]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[45]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[46]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[47]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[48]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[49]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[4]                              ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[50]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[51]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[52]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[53]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[54]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[55]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[56]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[57]                             ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaRdClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|q_b[58]                             ;
+--------+--------------+----------------+------------+-----------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoAnaWrClk'                                                                                                                                                           ;
+--------+--------------+----------------+------------+-----------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+------------+-----------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a0                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a1                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a10                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a11                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a12                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a2                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a3                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a4                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a5                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a6                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a7                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a8                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|counter8a9                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|parity9                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[0]                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[1]                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[2]                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|a_graycounter_4lc:wrptr_g1p|sub_parity10a[3]                 ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_address_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_datain_reg0     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a0~porta_we_reg          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a10~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a11~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a12~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a13~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a14~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a15~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a16~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a17~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a18~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a19~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_address_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_datain_reg0     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a1~porta_we_reg          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a20~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a21~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a22~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a23~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a24~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_datain_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a25~porta_we_reg         ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoAnaWrClk ; Rise       ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|altsyncram_om31:fifo_ram|ram_block11a26~porta_datain_reg0    ;
+--------+--------------+----------------+------------+-----------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'uberACync:Sink|FifoDigRdClk'                                                                                                                                                            ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type       ; Clock                       ; Clock Edge ; Target                                                                                                                            ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a0                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a1                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a10                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a11                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a12                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a13                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a14_OTERM7               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM1               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM3               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a15_OTERM5               ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a2                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a3                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a4                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a5                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a6                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a7                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a8                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|counter5a9                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|parity6                          ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[0]                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[1]                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[2]                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|a_graycounter_b77:rdptr_g1p|sub_parity7a[3]                  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9]  ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[0]                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|addr_store_b[1]                     ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[0]                    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|address_reg_b[1]                    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[0]                ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|out_address_reg_b[1]                ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a0~portb_address_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a10~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a11~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a12~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a13~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a14~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a15~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a16~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a17~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a18~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a19~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a1~portb_address_reg0    ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a2                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a20~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a21~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a22~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a23~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a24~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a25~portb_address_reg0   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26                      ;
; -1.000 ; 1.000        ; 2.000          ; Min Period ; uberACync:Sink|FifoDigRdClk ; Rise       ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|altsyncram_qj31:fifo_ram|ram_block11a26~portb_address_reg0   ;
+--------+--------------+----------------+------------+-----------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'Clk100'                                                                                           ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                      ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+
; 4.414 ; 4.414        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0]           ;
; 4.414 ; 4.414        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|observablevcoout ;
; 4.448 ; 4.448        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; Clk100~input|o                                              ;
; 4.456 ; 4.456        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.000 ; 5.000        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; Clk100~input|i                                              ;
; 5.000 ; 5.000        ; 0.000          ; Low Pulse Width  ; Clk100 ; Rise       ; Clk100~input|i                                              ;
; 5.544 ; 5.544        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|inclk[0]         ;
; 5.552 ; 5.552        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; Clk100~input|o                                              ;
; 5.585 ; 5.585        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0]           ;
; 5.585 ; 5.585        ; 0.000          ; High Pulse Width ; Clk100 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|observablevcoout ;
; 6.000 ; 10.000       ; 4.000          ; Port Rate        ; Clk100 ; Rise       ; Clk100                                                      ;
+-------+--------------+----------------+------------------+--------+------------+-------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '60MHz|altpll_component|auto_generated|pll1|clk[0]'                                                             ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                             ; Clock Edge ; Target                        ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------+
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[10]  ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[11]  ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[12]  ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[13]  ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[1]   ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[2]   ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[3]   ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[4]   ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[5]   ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[6]   ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[7]   ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[8]   ;
; 8.115 ; 8.331        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[9]   ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|AcLineBuf      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|AdcConvert     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|AtZeroCrossing ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|Clk3662Hz[0]   ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[0]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[1]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[2]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[3]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[4]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[5]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[6]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[7]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrAna[8]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[0]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[1]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[2]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[3]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[4]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[5]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[6]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[7]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrDig[8]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[0]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[1]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[2]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[3]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[4]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[5]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[6]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|CtrPot[7]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacAddr[0]     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacAddr[1]     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacAddr[2]     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacAddr[3]     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[0]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[12]     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[13]     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[14]     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[15]     ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[1]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[3]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[4]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[5]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacDat[7]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacLoad        ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DacWr          ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[10] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[11] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[12] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[13] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[14] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[15] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[16] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[17] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[18] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[19] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DelayTimer[20] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[0]    ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[1]    ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[2]    ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[3]    ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[4]    ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[5]    ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[6]    ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigInBuf[7]    ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[0]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[1]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[2]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[3]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[4]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[5]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[6]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|DigOut[7]      ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|ExtendInBuf[0] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|ExtendInBuf[1] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|ExtendOut[0]   ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|ExtendOut[1]   ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoAnaRdClk   ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoAnaWrClk   ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoDigRdClk   ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoDigWrClk   ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[0]  ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[16] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[17] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[19] ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[1]  ;
; 8.116 ; 8.332        ; 0.216          ; High Pulse Width ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; uberACync:Sink|FifoOutAna[20] ;
+-------+--------------+----------------+------------------+---------------------------------------------------+------------+-------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+
; AC60Hz       ; Clk100     ; 1.475 ; 1.887 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc1         ; Clk100     ; 3.251 ; 3.995 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc2         ; Clk100     ; 3.083 ; 3.797 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc3         ; Clk100     ; 2.262 ; 2.433 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc4         ; Clk100     ; 2.307 ; 2.484 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigIn[*]     ; Clk100     ; 2.793 ; 3.674 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[0]    ; Clk100     ; 2.751 ; 3.601 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[1]    ; Clk100     ; 2.762 ; 3.597 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[2]    ; Clk100     ; 2.670 ; 3.482 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[3]    ; Clk100     ; 2.568 ; 3.383 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[4]    ; Clk100     ; 2.793 ; 3.674 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[5]    ; Clk100     ; 2.654 ; 3.497 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[6]    ; Clk100     ; 2.781 ; 3.628 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[7]    ; Clk100     ; 2.671 ; 3.523 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendIn[*]  ; Clk100     ; 1.592 ; 2.010 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[0] ; Clk100     ; 1.531 ; 1.956 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[1] ; Clk100     ; 1.592 ; 2.010 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Master       ; Clk100     ; 1.599 ; 2.021 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotDat       ; Clk100     ; 1.589 ; 2.120 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                   ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+
; AC60Hz       ; Clk100     ; -1.111 ; -1.528 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc1         ; Clk100     ; -2.037 ; -2.632 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc2         ; Clk100     ; -2.228 ; -2.861 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc3         ; Clk100     ; -1.341 ; -1.589 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc4         ; Clk100     ; -1.022 ; -1.310 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigIn[*]     ; Clk100     ; -2.151 ; -2.950 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[0]    ; Clk100     ; -2.327 ; -3.158 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[1]    ; Clk100     ; -2.341 ; -3.167 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[2]    ; Clk100     ; -2.248 ; -3.045 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[3]    ; Clk100     ; -2.151 ; -2.950 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[4]    ; Clk100     ; -2.369 ; -3.228 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[5]    ; Clk100     ; -2.235 ; -3.059 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[6]    ; Clk100     ; -2.362 ; -3.196 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[7]    ; Clk100     ; -2.251 ; -3.084 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendIn[*]  ; Clk100     ; -1.165 ; -1.595 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[0] ; Clk100     ; -1.165 ; -1.595 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[1] ; Clk100     ; -1.223 ; -1.647 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Master       ; Clk100     ; -1.230 ; -1.657 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotDat       ; Clk100     ; -0.909 ; -1.406 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                       ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; AdcClk        ; Clk100     ; 2.416 ; 2.529 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; AdcConvert    ; Clk100     ; 2.453 ; 2.577 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacAddr[*]    ; Clk100     ; 4.532 ; 4.932 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[0]   ; Clk100     ; 2.787 ; 2.908 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[1]   ; Clk100     ; 2.903 ; 3.043 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[2]   ; Clk100     ; 4.532 ; 4.932 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[3]   ; Clk100     ; 2.620 ; 2.751 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacDat[*]     ; Clk100     ; 4.947 ; 5.481 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[0]    ; Clk100     ; 2.874 ; 3.030 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[1]    ; Clk100     ; 2.616 ; 2.744 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[2]    ; Clk100     ; 2.997 ; 3.211 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[3]    ; Clk100     ; 2.680 ; 2.884 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[4]    ; Clk100     ; 2.960 ; 3.161 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[5]    ; Clk100     ; 3.073 ; 3.303 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[6]    ; Clk100     ; 3.177 ; 3.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[7]    ; Clk100     ; 3.284 ; 3.467 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[8]    ; Clk100     ; 4.947 ; 5.481 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[9]    ; Clk100     ; 3.488 ; 3.755 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[10]   ; Clk100     ; 3.322 ; 3.512 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[11]   ; Clk100     ; 2.852 ; 2.997 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[12]   ; Clk100     ; 3.849 ; 4.114 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[13]   ; Clk100     ; 3.243 ; 3.452 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[14]   ; Clk100     ; 3.955 ; 4.202 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[15]   ; Clk100     ; 3.450 ; 3.678 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacLoad       ; Clk100     ; 3.215 ; 3.428 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacWr         ; Clk100     ; 2.945 ; 3.126 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigOut[*]     ; Clk100     ; 4.274 ; 4.652 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[0]    ; Clk100     ; 2.481 ; 2.578 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[1]    ; Clk100     ; 2.661 ; 2.800 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[2]    ; Clk100     ; 2.593 ; 2.711 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[3]    ; Clk100     ; 2.516 ; 2.608 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[4]    ; Clk100     ; 4.274 ; 4.652 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[5]    ; Clk100     ; 2.674 ; 2.794 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[6]    ; Clk100     ; 2.826 ; 2.963 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[7]    ; Clk100     ; 2.959 ; 3.117 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendOut[*]  ; Clk100     ; 3.086 ; 3.241 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[0] ; Clk100     ; 3.005 ; 3.179 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[1] ; Clk100     ; 3.086 ; 3.241 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Led           ; Clk100     ; 4.731 ; 4.610 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotClk        ; Clk100     ; 2.439 ; 2.510 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotStart      ; Clk100     ; 2.383 ; 2.455 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Prbs          ; Clk100     ; 3.284 ; 3.463 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                               ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; AdcClk        ; Clk100     ; 2.103 ; 2.213 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; AdcConvert    ; Clk100     ; 2.139 ; 2.259 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacAddr[*]    ; Clk100     ; 2.298 ; 2.424 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[0]   ; Clk100     ; 2.459 ; 2.575 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[1]   ; Clk100     ; 2.570 ; 2.705 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[2]   ; Clk100     ; 4.205 ; 4.601 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[3]   ; Clk100     ; 2.298 ; 2.424 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacDat[*]     ; Clk100     ; 2.294 ; 2.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[0]    ; Clk100     ; 2.542 ; 2.691 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[1]    ; Clk100     ; 2.294 ; 2.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[2]    ; Clk100     ; 2.664 ; 2.873 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[3]    ; Clk100     ; 2.360 ; 2.559 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[4]    ; Clk100     ; 2.625 ; 2.819 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[5]    ; Clk100     ; 2.738 ; 2.962 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[6]    ; Clk100     ; 2.837 ; 3.071 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[7]    ; Clk100     ; 2.936 ; 3.112 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[8]    ; Clk100     ; 4.604 ; 5.129 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[9]    ; Clk100     ; 3.136 ; 3.395 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[10]   ; Clk100     ; 2.973 ; 3.154 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[11]   ; Clk100     ; 2.520 ; 2.659 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[12]   ; Clk100     ; 3.478 ; 3.733 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[13]   ; Clk100     ; 2.897 ; 3.097 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[14]   ; Clk100     ; 3.580 ; 3.817 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[15]   ; Clk100     ; 3.095 ; 3.314 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacLoad       ; Clk100     ; 2.870 ; 3.074 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacWr         ; Clk100     ; 2.611 ; 2.784 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigOut[*]     ; Clk100     ; 2.165 ; 2.258 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[0]    ; Clk100     ; 2.165 ; 2.258 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[1]    ; Clk100     ; 2.337 ; 2.471 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[2]    ; Clk100     ; 2.273 ; 2.387 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[3]    ; Clk100     ; 2.199 ; 2.286 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[4]    ; Clk100     ; 3.958 ; 4.332 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[5]    ; Clk100     ; 2.350 ; 2.465 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[6]    ; Clk100     ; 2.496 ; 2.628 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[7]    ; Clk100     ; 2.624 ; 2.775 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendOut[*]  ; Clk100     ; 2.668 ; 2.835 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[0] ; Clk100     ; 2.668 ; 2.835 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[1] ; Clk100     ; 2.746 ; 2.894 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Led           ; Clk100     ; 2.714 ; 2.775 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotClk        ; Clk100     ; 2.124 ; 2.192 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotStart      ; Clk100     ; 2.071 ; 2.139 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Prbs          ; Clk100     ; 2.936 ; 3.108 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+


----------------
; MTBF Summary ;
----------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Synchronizer Summary                                                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+
; Source Node                                                                              ; Synchronization Node                                                                                                              ; Typical MTBF (Years) ; Included in Design MTBF ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                    ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                    ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg                                   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg                                   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]          ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14] ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]  ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]   ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]  ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]         ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2]   ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4]   ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9]  ; Not Calculated       ; Yes                     ;
; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]          ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8]  ; Not Calculated       ; Yes                     ;
; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]           ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3]   ; Not Calculated       ; Yes                     ;
+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+----------------------+-------------------------+


Synchronizer Chain #1: Worst-Case MTBF is Not Calculated
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                          ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                 ;
; Included in Design MTBF ; Yes                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                        ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                           ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                            ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                    ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                    ; -1.051         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                       ; 125            ;              ;                  ;              ;
; Source Clock                                                                                    ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                           ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
; Synchronization Registers                                                                       ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;                ;              ;                  ; -1.051       ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #2: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -1.050         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[9]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[9] ;                ;              ;                  ; -0.154       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[9] ;                ;              ;                  ; -0.896       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #3: Worst-Case MTBF is Not Calculated
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                          ;
+-------------------------+------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                 ;
; Included in Design MTBF ; Yes                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                        ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                           ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                            ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                    ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                    ; -0.892         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                       ; 125            ;              ;                  ;              ;
; Source Clock                                                                                    ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                           ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                    ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
; Synchronization Registers                                                                       ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;                ;              ;                  ; -0.892       ;
+-------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #4: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.738         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[1]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[1] ;                ;              ;                  ; -0.054       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[1] ;                ;              ;                  ; -0.684       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #5: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.727         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[8]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[8] ;                ;              ;                  ; -0.014       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[8] ;                ;              ;                  ; -0.713       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #6: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.723         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[0]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[0] ;                ;              ;                  ; 0.144        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[0] ;                ;              ;                  ; -0.867       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #7: Worst-Case MTBF is Not Calculated
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                           ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                  ;
; Included in Design MTBF ; Yes                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                     ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                     ; -0.681         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                              ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
; Synchronization Registers                                                                        ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_msb_mux_reg ;                ;              ;                  ; -0.681       ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #8: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -0.676         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[11]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[11] ;                ;              ;                  ; 0.130        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[11] ;                ;              ;                  ; -0.806       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #9: Worst-Case MTBF is Not Calculated
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                           ;
+-------------------------+-------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;
; Typical MTBF (years)    ; Not Calculated                                                                                  ;
; Included in Design MTBF ; Yes                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                     ; 1              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                     ; -0.641         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                              ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[7]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[14]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[15]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[11]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[10]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[8]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[9]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[12]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[13]            ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                 ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[6]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[1]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[0]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[3]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[2]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[4]             ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rs_dgwp_reg[5]             ;                ;              ;                  ;              ;
; Synchronization Registers                                                                        ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|wrfull_eq_comp_lsb_mux_reg ;                ;              ;                  ; -0.641       ;
+--------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #10: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -0.577         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[12]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[12] ;                ;              ;                  ; 0.511        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[12] ;                ;              ;                  ; -1.088       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #11: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -0.537         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[15]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[15] ;                ;              ;                  ; 0.494        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[15] ;                ;              ;                  ; -1.031       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #12: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.522         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[1]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[1] ;                ;              ;                  ; -0.125       ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[1] ;                ;              ;                  ; -0.397       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #13: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.516         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[10]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[10] ;                ;              ;                  ; -0.045       ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[10] ;                ;              ;                  ; -0.471       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #14: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -0.515         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[10]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[10] ;                ;              ;                  ; 0.434        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[10] ;                ;              ;                  ; -0.949       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #15: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.506         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[4]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[4] ;                ;              ;                  ; 0.428        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[4] ;                ;              ;                  ; -0.934       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #16: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.499         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[2]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[2] ;                ;              ;                  ; 0.296        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[2] ;                ;              ;                  ; -0.795       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #17: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.396         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[0]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[0] ;                ;              ;                  ; 0.088        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[0] ;                ;              ;                  ; -0.484       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #18: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.382         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[5]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[5] ;                ;              ;                  ; 0.247        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[5] ;                ;              ;                  ; -0.629       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #19: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -0.368         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[13]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[13] ;                ;              ;                  ; 0.579        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[13] ;                ;              ;                  ; -0.947       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #20: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.359         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[7]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[7] ;                ;              ;                  ; 0.314        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[7] ;                ;              ;                  ; -0.673       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #21: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -0.313         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[6]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[6] ;                ;              ;                  ; 0.140        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[6] ;                ;              ;                  ; -0.453       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #22: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -0.271         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[7]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[7] ;                ;              ;                  ; 0.055        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[7] ;                ;              ;                  ; -0.326       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #23: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -0.221         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[2]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[2] ;                ;              ;                  ; 0.405        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[2] ;                ;              ;                  ; -0.626       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #24: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.171         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[10]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[10] ;                ;              ;                  ; 0.510        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[10] ;                ;              ;                  ; -0.681       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #25: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; -0.169         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[14]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[14] ;                ;              ;                  ; 0.243        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[14] ;                ;              ;                  ; -0.412       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #26: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.167         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[7]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[7] ;                ;              ;                  ; 0.577        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[7] ;                ;              ;                  ; -0.744       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #27: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -0.132         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[9]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[9] ;                ;              ;                  ; 0.304        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[9] ;                ;              ;                  ; -0.436       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #28: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -0.124         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[3]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[3] ;                ;              ;                  ; 0.578        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[3] ;                ;              ;                  ; -0.702       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #29: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.122         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[3]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[3] ;                ;              ;                  ; 0.577        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[3] ;                ;              ;                  ; -0.699       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #30: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.112         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[5]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[5] ;                ;              ;                  ; 0.513        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[5] ;                ;              ;                  ; -0.625       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #31: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.074         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[12]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[12] ;                ;              ;                  ; 0.576        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[12] ;                ;              ;                  ; -0.650       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #32: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; -0.070         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[1]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[1] ;                ;              ;                  ; 0.471        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[1] ;                ;              ;                  ; -0.541       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #33: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.063         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[6]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[6] ;                ;              ;                  ; 0.431        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[6] ;                ;              ;                  ; -0.494       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #34: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; -0.024         ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[3]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[3] ;                ;              ;                  ; 0.515        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[3] ;                ;              ;                  ; -0.539       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #35: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; 0.001          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[11]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[11] ;                ;              ;                  ; 0.504        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[11] ;                ;              ;                  ; -0.503       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #36: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; 0.008          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[11]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[11] ;                ;              ;                  ; 0.354        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[11] ;                ;              ;                  ; -0.346       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #37: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; 0.022          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[15]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[15] ;                ;              ;                  ; 0.251        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[15] ;                ;              ;                  ; -0.229       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #38: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.029          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[5]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[5] ;                ;              ;                  ; 0.495        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[5] ;                ;              ;                  ; -0.466       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #39: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; 0.068          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[14]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[14] ;                ;              ;                  ; 0.511        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[14] ;                ;              ;                  ; -0.443       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #40: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                          ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; 0.097          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|delayed_wrptr_g[6]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a[6] ;                ;              ;                  ; 0.414        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe14|dffe16a[6] ;                ;              ;                  ; -0.317       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #41: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; 0.118          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[4]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[4] ;                ;              ;                  ; 0.578        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[4] ;                ;              ;                  ; -0.460       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #42: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.123          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[4]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[4] ;                ;              ;                  ; 0.578        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[4] ;                ;              ;                  ; -0.455       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #43: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; 0.127          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[2]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[2] ;                ;              ;                  ; 0.500        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[2] ;                ;              ;                  ; -0.373       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #44: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.133          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[0]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[0] ;                ;              ;                  ; 0.436        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[0] ;                ;              ;                  ; -0.303       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #45: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.165          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[8]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[8] ;                ;              ;                  ; 0.577        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[8] ;                ;              ;                  ; -0.412       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #46: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.186          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[5]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[5] ;                ;              ;                  ; 0.514        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[5] ;                ;              ;                  ; -0.328       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #47: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.189          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[7]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[7] ;                ;              ;                  ; 0.579        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[7] ;                ;              ;                  ; -0.390       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #48: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; 0.191          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[11]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[11] ;                ;              ;                  ; 0.579        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[11] ;                ;              ;                  ; -0.388       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #49: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.198          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[0]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[0] ;                ;              ;                  ; 0.577        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[0] ;                ;              ;                  ; -0.379       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #50: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; 0.199          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[10]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[10] ;                ;              ;                  ; 0.580        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[10] ;                ;              ;                  ; -0.381       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #51: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.206          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[8]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[8] ;                ;              ;                  ; 0.501        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[8] ;                ;              ;                  ; -0.295       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #52: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; 0.207          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|delayed_wrptr_g[12]                                          ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe13a[12] ;                ;              ;                  ; 0.307        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_tld:rs_dgwp|dffpipe_se9:dffpipe12|dffe14a[12] ;                ;              ;                  ; -0.100       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #53: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; 0.248          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[13]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[13] ;                ;              ;                  ; 0.579        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[13] ;                ;              ;                  ; -0.331       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #54: Worst-Case MTBF is Not Calculated
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                             ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                    ;
; Included in Design MTBF ; Yes                                                                                                                               ;
+-------------------------+-----------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                           ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                              ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                               ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                       ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                       ; 0.254          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                          ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                       ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                              ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                       ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                                ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[12]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                          ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[12] ;                ;              ;                  ; 0.579        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[12] ;                ;              ;                  ; -0.325       ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #55: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.261          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[9]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[9] ;                ;              ;                  ; 0.577        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[9] ;                ;              ;                  ; -0.316       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #56: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.324          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[1]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[1] ;                ;              ;                  ; 0.578        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[1] ;                ;              ;                  ; -0.254       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #57: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.330          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[6]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[6] ;                ;              ;                  ; 0.434        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[6] ;                ;              ;                  ; -0.104       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #58: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.340          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[2]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[2] ;                ;              ;                  ; 0.426        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[2] ;                ;              ;                  ; -0.086       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #59: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.347          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[4]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[4] ;                ;              ;                  ; 0.513        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[4] ;                ;              ;                  ; -0.166       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #60: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; 0.370          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[9]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[9] ;                ;              ;                  ; 0.514        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[9] ;                ;              ;                  ; -0.144       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #61: Worst-Case MTBF is Not Calculated
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                  ;
; Synchronization Node    ; FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                   ;
; Included in Design MTBF ; Yes                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                          ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                             ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                              ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                      ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                      ; 0.379          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                         ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                      ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigRdClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                             ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoDigWrClk                                                                                                      ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                               ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|rdptr_g[8]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                         ;                ;              ;                  ;              ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a[8] ;                ;              ;                  ; 0.511        ;
;  FifoD:FifoDigital|dcfifo:dcfifo_component|dcfifo_h0l1:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe17|dffe19a[8] ;                ;              ;                  ; -0.132       ;
+-----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



Synchronizer Chain #62: Worst-Case MTBF is Not Calculated
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                           ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ;
; Synchronization Node    ; FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3] ;
; Typical MTBF (years)    ; Not Calculated                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                             ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Property                                                                                                                         ; Value          ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                            ; User Specified ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                             ; Not Calculated ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                     ; 2              ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                     ; 0.413          ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                        ; 125            ;              ;                  ;              ;
; Source Clock                                                                                                                     ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaRdClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Synchronization Clock                                                                                                            ;                ;              ;                  ;              ;
;  uberACync:Sink|FifoAnaWrClk                                                                                                     ;                ; 1.000        ; 1000.0 MHz       ;              ;
; Asynchronous Source                                                                                                              ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|rdptr_g[3]                                                  ;                ;              ;                  ;              ;
; Synchronization Registers                                                                                                        ;                ;              ;                  ;              ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe16a[3] ;                ;              ;                  ; 0.578        ;
;  FifoA:FifoAnalog|dcfifo:dcfifo_component|dcfifo_o1l1:auto_generated|alt_synch_pipe_uld:ws_dgrp|dffpipe_te9:dffpipe15|dffe17a[3] ;                ;              ;                  ; -0.165       ;
+----------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+



+-----------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                   ;
+----------------------------------------------------+-----------+----------+----------+----------+---------------------+
; Clock                                              ; Setup     ; Hold     ; Recovery ; Removal  ; Minimum Pulse Width ;
+----------------------------------------------------+-----------+----------+----------+----------+---------------------+
; Worst-case Slack                                   ; -8.006    ; -1.718   ; -1.077   ; -1.336   ; -3.201              ;
;  60MHz|altpll_component|auto_generated|pll1|clk[0] ; -8.006    ; -0.429   ; N/A      ; N/A      ; 8.025               ;
;  Clk100                                            ; N/A       ; N/A      ; N/A      ; N/A      ; 4.414               ;
;  uberACync:Sink|FifoAnaRdClk                       ; -3.082    ; 0.186    ; -0.942   ; -0.552   ; -3.201              ;
;  uberACync:Sink|FifoAnaWrClk                       ; -4.992    ; -1.718   ; -0.658   ; -0.540   ; -3.201              ;
;  uberACync:Sink|FifoDigRdClk                       ; -4.025    ; -1.615   ; -0.228   ; -1.336   ; -3.201              ;
;  uberACync:Sink|FifoDigWrClk                       ; -6.764    ; -1.660   ; -1.077   ; -0.252   ; -3.201              ;
; Design-wide TNS                                    ; -2194.754 ; -102.428 ; -289.511 ; -329.329 ; -1617.462           ;
;  60MHz|altpll_component|auto_generated|pll1|clk[0] ; -176.267  ; -1.276   ; N/A      ; N/A      ; 0.000               ;
;  Clk100                                            ; N/A       ; N/A      ; N/A      ; N/A      ; 0.000               ;
;  uberACync:Sink|FifoAnaRdClk                       ; -320.853  ; 0.000    ; -136.110 ; -82.954  ; -418.821            ;
;  uberACync:Sink|FifoAnaWrClk                       ; -594.061  ; -50.989  ; -47.351  ; -38.795  ; -414.360            ;
;  uberACync:Sink|FifoDigRdClk                       ; -276.811  ; -3.230   ; -12.380  ; -200.249 ; -347.616            ;
;  uberACync:Sink|FifoDigWrClk                       ; -826.762  ; -47.267  ; -93.670  ; -21.880  ; -436.665            ;
+----------------------------------------------------+-----------+----------+----------+----------+---------------------+


+------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+
; AC60Hz       ; Clk100     ; 2.901 ; 3.032 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc1         ; Clk100     ; 6.716 ; 6.979 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc2         ; Clk100     ; 6.397 ; 6.653 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc3         ; Clk100     ; 4.305 ; 4.492 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc4         ; Clk100     ; 4.453 ; 4.697 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigIn[*]     ; Clk100     ; 5.841 ; 6.243 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[0]    ; Clk100     ; 5.779 ; 6.120 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[1]    ; Clk100     ; 5.841 ; 6.163 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[2]    ; Clk100     ; 5.583 ; 5.842 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[3]    ; Clk100     ; 5.300 ; 5.621 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[4]    ; Clk100     ; 5.831 ; 6.243 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[5]    ; Clk100     ; 5.520 ; 5.856 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[6]    ; Clk100     ; 5.804 ; 6.188 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[7]    ; Clk100     ; 5.525 ; 5.900 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendIn[*]  ; Clk100     ; 3.122 ; 3.276 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[0] ; Clk100     ; 3.047 ; 3.207 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[1] ; Clk100     ; 3.122 ; 3.276 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Master       ; Clk100     ; 3.179 ; 3.329 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotDat       ; Clk100     ; 3.238 ; 3.466 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+-------+-------+------------+---------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                   ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+
; AC60Hz       ; Clk100     ; -1.111 ; -1.528 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc1         ; Clk100     ; -2.037 ; -2.632 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc2         ; Clk100     ; -2.228 ; -2.861 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc3         ; Clk100     ; -1.341 ; -1.589 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Adc4         ; Clk100     ; -1.022 ; -1.310 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigIn[*]     ; Clk100     ; -2.151 ; -2.950 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[0]    ; Clk100     ; -2.327 ; -3.158 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[1]    ; Clk100     ; -2.341 ; -3.167 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[2]    ; Clk100     ; -2.248 ; -3.045 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[3]    ; Clk100     ; -2.151 ; -2.950 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[4]    ; Clk100     ; -2.369 ; -3.228 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[5]    ; Clk100     ; -2.235 ; -3.059 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[6]    ; Clk100     ; -2.362 ; -3.196 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigIn[7]    ; Clk100     ; -2.251 ; -3.084 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendIn[*]  ; Clk100     ; -1.165 ; -1.595 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[0] ; Clk100     ; -1.165 ; -1.595 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendIn[1] ; Clk100     ; -1.223 ; -1.647 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Master       ; Clk100     ; -1.230 ; -1.657 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotDat       ; Clk100     ; -0.909 ; -1.406 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+--------------+------------+--------+--------+------------+---------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                         ;
+---------------+------------+--------+--------+------------+---------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                   ;
+---------------+------------+--------+--------+------------+---------------------------------------------------+
; AdcClk        ; Clk100     ; 5.486  ; 5.394  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; AdcConvert    ; Clk100     ; 5.554  ; 5.477  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacAddr[*]    ; Clk100     ; 8.981  ; 8.957  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[0]   ; Clk100     ; 6.264  ; 6.062  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[1]   ; Clk100     ; 6.459  ; 6.269  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[2]   ; Clk100     ; 8.981  ; 8.957  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[3]   ; Clk100     ; 5.803  ; 5.721  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacDat[*]     ; Clk100     ; 9.826  ; 10.014 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[0]    ; Clk100     ; 6.440  ; 6.265  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[1]    ; Clk100     ; 5.795  ; 5.703  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[2]    ; Clk100     ; 6.745  ; 6.484  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[3]    ; Clk100     ; 5.926  ; 5.895  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[4]    ; Clk100     ; 6.602  ; 6.537  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[5]    ; Clk100     ; 6.912  ; 6.678  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[6]    ; Clk100     ; 7.159  ; 6.891  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[7]    ; Clk100     ; 7.484  ; 7.112  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[8]    ; Clk100     ; 9.826  ; 10.014 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[9]    ; Clk100     ; 7.884  ; 7.541  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[10]   ; Clk100     ; 7.489  ; 7.177  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[11]   ; Clk100     ; 6.370  ; 6.209  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[12]   ; Clk100     ; 8.721  ; 8.329  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[13]   ; Clk100     ; 7.266  ; 7.128  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[14]   ; Clk100     ; 9.014  ; 8.495  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[15]   ; Clk100     ; 7.790  ; 7.558  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacLoad       ; Clk100     ; 7.133  ; 7.028  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacWr         ; Clk100     ; 6.589  ; 6.446  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigOut[*]     ; Clk100     ; 8.326  ; 8.380  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[0]    ; Clk100     ; 5.473  ; 5.351  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[1]    ; Clk100     ; 5.895  ; 5.823  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[2]    ; Clk100     ; 5.792  ; 5.639  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[3]    ; Clk100     ; 5.635  ; 5.434  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[4]    ; Clk100     ; 8.326  ; 8.380  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[5]    ; Clk100     ; 5.985  ; 5.778  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[6]    ; Clk100     ; 6.349  ; 6.148  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[7]    ; Clk100     ; 6.658  ; 6.414  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendOut[*]  ; Clk100     ; 6.996  ; 6.672  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[0] ; Clk100     ; 6.681  ; 6.496  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[1] ; Clk100     ; 6.996  ; 6.672  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Led           ; Clk100     ; 10.645 ; 10.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotClk        ; Clk100     ; 5.417  ; 5.238  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotStart      ; Clk100     ; 5.286  ; 5.131  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Prbs          ; Clk100     ; 7.520  ; 7.122  ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+---------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                               ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                   ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+
; AdcClk        ; Clk100     ; 2.103 ; 2.213 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; AdcConvert    ; Clk100     ; 2.139 ; 2.259 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacAddr[*]    ; Clk100     ; 2.298 ; 2.424 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[0]   ; Clk100     ; 2.459 ; 2.575 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[1]   ; Clk100     ; 2.570 ; 2.705 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[2]   ; Clk100     ; 4.205 ; 4.601 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacAddr[3]   ; Clk100     ; 2.298 ; 2.424 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacDat[*]     ; Clk100     ; 2.294 ; 2.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[0]    ; Clk100     ; 2.542 ; 2.691 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[1]    ; Clk100     ; 2.294 ; 2.417 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[2]    ; Clk100     ; 2.664 ; 2.873 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[3]    ; Clk100     ; 2.360 ; 2.559 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[4]    ; Clk100     ; 2.625 ; 2.819 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[5]    ; Clk100     ; 2.738 ; 2.962 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[6]    ; Clk100     ; 2.837 ; 3.071 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[7]    ; Clk100     ; 2.936 ; 3.112 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[8]    ; Clk100     ; 4.604 ; 5.129 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[9]    ; Clk100     ; 3.136 ; 3.395 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[10]   ; Clk100     ; 2.973 ; 3.154 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[11]   ; Clk100     ; 2.520 ; 2.659 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[12]   ; Clk100     ; 3.478 ; 3.733 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[13]   ; Clk100     ; 2.897 ; 3.097 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[14]   ; Clk100     ; 3.580 ; 3.817 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DacDat[15]   ; Clk100     ; 3.095 ; 3.314 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacLoad       ; Clk100     ; 2.870 ; 3.074 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DacWr         ; Clk100     ; 2.611 ; 2.784 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; DigOut[*]     ; Clk100     ; 2.165 ; 2.258 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[0]    ; Clk100     ; 2.165 ; 2.258 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[1]    ; Clk100     ; 2.337 ; 2.471 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[2]    ; Clk100     ; 2.273 ; 2.387 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[3]    ; Clk100     ; 2.199 ; 2.286 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[4]    ; Clk100     ; 3.958 ; 4.332 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[5]    ; Clk100     ; 2.350 ; 2.465 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[6]    ; Clk100     ; 2.496 ; 2.628 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  DigOut[7]    ; Clk100     ; 2.624 ; 2.775 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; ExtendOut[*]  ; Clk100     ; 2.668 ; 2.835 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[0] ; Clk100     ; 2.668 ; 2.835 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
;  ExtendOut[1] ; Clk100     ; 2.746 ; 2.894 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Led           ; Clk100     ; 2.714 ; 2.775 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotClk        ; Clk100     ; 2.124 ; 2.192 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; PotStart      ; Clk100     ; 2.071 ; 2.139 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
; Prbs          ; Clk100     ; 2.936 ; 3.108 ; Rise       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+---------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Prbs          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AdcClk        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacLoad       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; PotClk        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; PotStart      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; Led           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacWr         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AdcConvert    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacAddr[3]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacAddr[2]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacAddr[1]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacAddr[0]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[15]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[14]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[13]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[12]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[11]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[10]    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[9]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[8]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[7]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[6]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[5]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[4]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[3]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[2]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[1]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[0]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DigOut[7]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DigOut[6]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DigOut[5]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DigOut[4]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DigOut[3]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DigOut[2]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DigOut[1]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DigOut[0]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ExtendOut[1]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ExtendOut[0]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; Clk100                  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ExtendIn[0]             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ExtendIn[1]             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; Master                  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; Adc1                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; Adc4                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; Adc3                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; Adc2                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; DigIn[7]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; DigIn[6]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; DigIn[5]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; DigIn[4]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; DigIn[3]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; DigIn[2]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; DigIn[1]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; DigIn[0]                ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; AC60Hz                  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PotDat                  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Prbs          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; AdcClk        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DacLoad       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; PotClk        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; PotStart      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; Led           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacWr         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; AdcConvert    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DacAddr[3]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacAddr[2]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.00415 V          ; 0.069 V                              ; 0.222 V                              ; 5.99e-09 s                  ; 5.65e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.00415 V         ; 0.069 V                             ; 0.222 V                             ; 5.99e-09 s                 ; 5.65e-09 s                 ; Yes                       ; Yes                       ;
; DacAddr[1]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacAddr[0]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[15]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[14]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[13]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[12]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[11]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[10]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[9]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-08 V                   ; 3.1 V               ; -0.0301 V           ; 0.124 V                              ; 0.185 V                              ; 1.09e-09 s                  ; 1.06e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-08 V                  ; 3.1 V              ; -0.0301 V          ; 0.124 V                             ; 0.185 V                             ; 1.09e-09 s                 ; 1.06e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[8]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-08 V                   ; 3.09 V              ; -0.0043 V           ; 0.127 V                              ; 0.253 V                              ; 5.96e-09 s                  ; 5.64e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-08 V                  ; 3.09 V             ; -0.0043 V          ; 0.127 V                             ; 0.253 V                             ; 5.96e-09 s                 ; 5.64e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[7]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-08 V                   ; 3.1 V               ; -0.0354 V           ; 0.126 V                              ; 0.238 V                              ; 7.11e-10 s                  ; 6.67e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-08 V                  ; 3.1 V              ; -0.0354 V          ; 0.126 V                             ; 0.238 V                             ; 7.11e-10 s                 ; 6.67e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[6]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-08 V                   ; 3.1 V               ; -0.0301 V           ; 0.124 V                              ; 0.185 V                              ; 1.09e-09 s                  ; 1.06e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-08 V                  ; 3.1 V              ; -0.0301 V          ; 0.124 V                             ; 0.185 V                             ; 1.09e-09 s                 ; 1.06e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[5]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-08 V                   ; 3.1 V               ; -0.0301 V           ; 0.124 V                              ; 0.185 V                              ; 1.09e-09 s                  ; 1.06e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-08 V                  ; 3.1 V              ; -0.0301 V          ; 0.124 V                             ; 0.185 V                             ; 1.09e-09 s                 ; 1.06e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[4]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-08 V                   ; 3.1 V               ; -0.0354 V           ; 0.126 V                              ; 0.238 V                              ; 7.11e-10 s                  ; 6.67e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-08 V                  ; 3.1 V              ; -0.0354 V          ; 0.126 V                             ; 0.238 V                             ; 7.11e-10 s                 ; 6.67e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-08 V                   ; 3.1 V               ; -0.0301 V           ; 0.124 V                              ; 0.185 V                              ; 1.09e-09 s                  ; 1.06e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-08 V                  ; 3.1 V              ; -0.0301 V          ; 0.124 V                             ; 0.185 V                             ; 1.09e-09 s                 ; 1.06e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-08 V                   ; 3.1 V               ; -0.0301 V           ; 0.124 V                              ; 0.185 V                              ; 1.09e-09 s                  ; 1.06e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-08 V                  ; 3.1 V              ; -0.0301 V          ; 0.124 V                             ; 0.185 V                             ; 1.09e-09 s                 ; 1.06e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[7]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[6]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[5]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[4]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.00415 V          ; 0.069 V                              ; 0.222 V                              ; 5.99e-09 s                  ; 5.65e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.00415 V         ; 0.069 V                             ; 0.222 V                             ; 5.99e-09 s                 ; 5.65e-09 s                 ; Yes                       ; Yes                       ;
; DigOut[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; ExtendOut[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; ExtendOut[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.42e-08 V                   ; 3.09 V              ; -0.0297 V           ; 0.063 V                              ; 0.266 V                              ; 7.63e-10 s                  ; 6.85e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.42e-08 V                  ; 3.09 V             ; -0.0297 V          ; 0.063 V                             ; 0.266 V                             ; 7.63e-10 s                 ; 6.85e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.51e-09 V                   ; 3.18 V              ; -0.157 V            ; 0.147 V                              ; 0.259 V                              ; 2.81e-10 s                  ; 2.53e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.51e-09 V                  ; 3.18 V             ; -0.157 V           ; 0.147 V                             ; 0.259 V                             ; 2.81e-10 s                 ; 2.53e-10 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Prbs          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; AdcClk        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DacLoad       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; PotClk        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; PotStart      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; Led           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacWr         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; AdcConvert    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DacAddr[3]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacAddr[2]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.08 V              ; -0.00171 V          ; 0.022 V                              ; 0.159 V                              ; 7.29e-09 s                  ; 7.17e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.08 V             ; -0.00171 V         ; 0.022 V                             ; 0.159 V                             ; 7.29e-09 s                 ; 7.17e-09 s                 ; Yes                       ; Yes                       ;
; DacAddr[1]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacAddr[0]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[15]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[14]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[13]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[12]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[11]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[10]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[9]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.04e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.048 V                              ; 0.136 V                              ; 1.32e-09 s                  ; 1.29e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.04e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.048 V                             ; 0.136 V                             ; 1.32e-09 s                 ; 1.29e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[8]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.04e-07 V                   ; 3.09 V              ; -0.00172 V          ; 0.052 V                              ; 0.174 V                              ; 7.27e-09 s                  ; 7.12e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.04e-07 V                  ; 3.09 V             ; -0.00172 V         ; 0.052 V                             ; 0.174 V                             ; 7.27e-09 s                 ; 7.12e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[7]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.04e-07 V                   ; 3.09 V              ; -0.0143 V           ; 0.06 V                               ; 0.116 V                              ; 8.95e-10 s                  ; 8.68e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.04e-07 V                  ; 3.09 V             ; -0.0143 V          ; 0.06 V                              ; 0.116 V                             ; 8.95e-10 s                 ; 8.68e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[6]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.04e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.048 V                              ; 0.136 V                              ; 1.32e-09 s                  ; 1.29e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.04e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.048 V                             ; 0.136 V                             ; 1.32e-09 s                 ; 1.29e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[5]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.04e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.048 V                              ; 0.136 V                              ; 1.32e-09 s                  ; 1.29e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.04e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.048 V                             ; 0.136 V                             ; 1.32e-09 s                 ; 1.29e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[4]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.04e-07 V                   ; 3.09 V              ; -0.0143 V           ; 0.06 V                               ; 0.116 V                              ; 8.95e-10 s                  ; 8.68e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.04e-07 V                  ; 3.09 V             ; -0.0143 V          ; 0.06 V                              ; 0.116 V                             ; 8.95e-10 s                 ; 8.68e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.04e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.048 V                              ; 0.136 V                              ; 1.32e-09 s                  ; 1.29e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.04e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.048 V                             ; 0.136 V                             ; 1.32e-09 s                 ; 1.29e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.04e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.048 V                              ; 0.136 V                              ; 1.32e-09 s                  ; 1.29e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.04e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.048 V                             ; 0.136 V                             ; 1.32e-09 s                 ; 1.29e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DacDat[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[7]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[6]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[5]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[4]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.08 V              ; -0.00171 V          ; 0.022 V                              ; 0.159 V                              ; 7.29e-09 s                  ; 7.17e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.08 V             ; -0.00171 V         ; 0.022 V                             ; 0.159 V                             ; 7.29e-09 s                 ; 7.17e-09 s                 ; Yes                       ; Yes                       ;
; DigOut[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; DigOut[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; ExtendOut[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; ExtendOut[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.2e-06 V                    ; 3.09 V              ; -0.0134 V           ; 0.034 V                              ; 0.132 V                              ; 9.35e-10 s                  ; 8.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.2e-06 V                   ; 3.09 V             ; -0.0134 V          ; 0.034 V                             ; 0.132 V                             ; 9.35e-10 s                 ; 8.97e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.6e-07 V                    ; 3.13 V              ; -0.103 V            ; 0.164 V                              ; 0.134 V                              ; 3.14e-10 s                  ; 4.05e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.6e-07 V                   ; 3.13 V             ; -0.103 V           ; 0.164 V                             ; 0.134 V                             ; 3.14e-10 s                 ; 4.05e-10 s                 ; Yes                       ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Prbs          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; AdcClk        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DacLoad       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; PotClk        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; PotStart      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; Led           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacWr         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; AdcConvert    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DacAddr[3]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacAddr[2]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.47 V              ; -0.00819 V          ; 0.32 V                               ; 0.312 V                              ; 4.78e-09 s                  ; 4.89e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.47 V             ; -0.00819 V         ; 0.32 V                              ; 0.312 V                             ; 4.78e-09 s                 ; 4.89e-09 s                 ; No                        ; No                        ;
; DacAddr[1]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacAddr[0]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacDat[15]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacDat[14]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacDat[13]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacDat[12]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacDat[11]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacDat[10]    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacDat[9]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.99e-07 V                   ; 3.52 V              ; -0.0531 V           ; 0.244 V                              ; 0.257 V                              ; 8.74e-10 s                  ; 8.74e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.99e-07 V                  ; 3.52 V             ; -0.0531 V          ; 0.244 V                             ; 0.257 V                             ; 8.74e-10 s                 ; 8.74e-10 s                 ; No                        ; No                        ;
; DacDat[8]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.99e-07 V                   ; 3.47 V              ; -0.00847 V          ; 0.317 V                              ; 0.306 V                              ; 4.78e-09 s                  ; 4.89e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.99e-07 V                  ; 3.47 V             ; -0.00847 V         ; 0.317 V                             ; 0.306 V                             ; 4.78e-09 s                 ; 4.89e-09 s                 ; No                        ; No                        ;
; DacDat[7]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.99e-07 V                   ; 3.53 V              ; -0.0671 V           ; 0.386 V                              ; 0.18 V                               ; 5.11e-10 s                  ; 6.25e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.99e-07 V                  ; 3.53 V             ; -0.0671 V          ; 0.386 V                             ; 0.18 V                              ; 5.11e-10 s                 ; 6.25e-10 s                 ; No                        ; No                        ;
; DacDat[6]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.99e-07 V                   ; 3.52 V              ; -0.0531 V           ; 0.244 V                              ; 0.257 V                              ; 8.74e-10 s                  ; 8.74e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.99e-07 V                  ; 3.52 V             ; -0.0531 V          ; 0.244 V                             ; 0.257 V                             ; 8.74e-10 s                 ; 8.74e-10 s                 ; No                        ; No                        ;
; DacDat[5]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.99e-07 V                   ; 3.52 V              ; -0.0531 V           ; 0.244 V                              ; 0.257 V                              ; 8.74e-10 s                  ; 8.74e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.99e-07 V                  ; 3.52 V             ; -0.0531 V          ; 0.244 V                             ; 0.257 V                             ; 8.74e-10 s                 ; 8.74e-10 s                 ; No                        ; No                        ;
; DacDat[4]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.99e-07 V                   ; 3.53 V              ; -0.0671 V           ; 0.386 V                              ; 0.18 V                               ; 5.11e-10 s                  ; 6.25e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.99e-07 V                  ; 3.53 V             ; -0.0671 V          ; 0.386 V                             ; 0.18 V                              ; 5.11e-10 s                 ; 6.25e-10 s                 ; No                        ; No                        ;
; DacDat[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.99e-07 V                   ; 3.52 V              ; -0.0531 V           ; 0.244 V                              ; 0.257 V                              ; 8.74e-10 s                  ; 8.74e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.99e-07 V                  ; 3.52 V             ; -0.0531 V          ; 0.244 V                             ; 0.257 V                             ; 8.74e-10 s                 ; 8.74e-10 s                 ; No                        ; No                        ;
; DacDat[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.99e-07 V                   ; 3.52 V              ; -0.0531 V           ; 0.244 V                              ; 0.257 V                              ; 8.74e-10 s                  ; 8.74e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.99e-07 V                  ; 3.52 V             ; -0.0531 V          ; 0.244 V                             ; 0.257 V                             ; 8.74e-10 s                 ; 8.74e-10 s                 ; No                        ; No                        ;
; DacDat[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DacDat[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DigOut[7]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DigOut[6]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DigOut[5]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DigOut[4]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.47 V              ; -0.00819 V          ; 0.32 V                               ; 0.312 V                              ; 4.78e-09 s                  ; 4.89e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.47 V             ; -0.00819 V         ; 0.32 V                              ; 0.312 V                             ; 4.78e-09 s                 ; 4.89e-09 s                 ; No                        ; No                        ;
; DigOut[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DigOut[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DigOut[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; DigOut[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; ExtendOut[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; ExtendOut[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.95e-07 V                   ; 3.52 V              ; -0.0582 V           ; 0.201 V                              ; 0.186 V                              ; 6.35e-10 s                  ; 6.31e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.95e-07 V                  ; 3.52 V             ; -0.0582 V          ; 0.201 V                             ; 0.186 V                             ; 6.35e-10 s                 ; 6.31e-10 s                 ; No                        ; No                        ;
; ~ALTERA_DCLK~ ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.54e-08 V                   ; 3.66 V              ; -0.26 V             ; 0.41 V                               ; 0.32 V                               ; 1.57e-10 s                  ; 2.15e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 6.54e-08 V                  ; 3.66 V             ; -0.26 V            ; 0.41 V                              ; 0.32 V                              ; 1.57e-10 s                 ; 2.15e-10 s                 ; No                        ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                   ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
; From Clock                                        ; To Clock                                          ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 5561     ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 65       ; 1        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 1        ; 0        ; 0        ;
; uberACync:Sink|FifoDigRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 57       ; 1        ; 0        ; 0        ;
; uberACync:Sink|FifoDigWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 2        ; 2        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaRdClk                       ; uberACync:Sink|FifoAnaRdClk                       ; 1020     ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaRdClk                       ; 13       ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk                       ; 64       ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaRdClk                       ; uberACync:Sink|FifoAnaWrClk                       ; 4199     ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk                       ; 949      ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk                       ; 2        ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk                       ; 936      ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigRdClk                       ; 16       ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk                       ; 32       ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigWrClk                       ; 5360     ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk                       ; 1417     ; 0        ; 0        ; 0        ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                    ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
; From Clock                                        ; To Clock                                          ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 5561     ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 65       ; 1        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 1        ; 0        ; 0        ;
; uberACync:Sink|FifoDigRdClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 57       ; 1        ; 0        ; 0        ;
; uberACync:Sink|FifoDigWrClk                       ; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; 2        ; 2        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaRdClk                       ; uberACync:Sink|FifoAnaRdClk                       ; 1020     ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaRdClk                       ; 13       ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk                       ; 64       ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaRdClk                       ; uberACync:Sink|FifoAnaWrClk                       ; 4199     ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoAnaWrClk                       ; uberACync:Sink|FifoAnaWrClk                       ; 949      ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk                       ; 2        ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigRdClk                       ; 936      ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigRdClk                       ; 16       ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk                       ; 32       ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoDigRdClk                       ; uberACync:Sink|FifoDigWrClk                       ; 5360     ; 0        ; 0        ; 0        ;
; uberACync:Sink|FifoDigWrClk                       ; uberACync:Sink|FifoDigWrClk                       ; 1417     ; 0        ; 0        ; 0        ;
+---------------------------------------------------+---------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                          ;
+---------------------------------------------------+-----------------------------+----------+----------+----------+----------+
; From Clock                                        ; To Clock                    ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------------------------------------+-----------------------------+----------+----------+----------+----------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 171      ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 72       ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 156      ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 87       ; 0        ; 0        ; 0        ;
+---------------------------------------------------+-----------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                           ;
+---------------------------------------------------+-----------------------------+----------+----------+----------+----------+
; From Clock                                        ; To Clock                    ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------------------------------------+-----------------------------+----------+----------+----------+----------+
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaRdClk ; 171      ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoAnaWrClk ; 72       ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigRdClk ; 156      ; 0        ; 0        ; 0        ;
; 60MHz|altpll_component|auto_generated|pll1|clk[0] ; uberACync:Sink|FifoDigWrClk ; 87       ; 0        ; 0        ; 0        ;
+---------------------------------------------------+-----------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 17    ; 17   ;
; Unconstrained Input Port Paths  ; 88    ; 88   ;
; Unconstrained Output Ports      ; 38    ; 38   ;
; Unconstrained Output Port Paths ; 54    ; 54   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Info: Processing started: Tue Mar 31 14:48:35 2015
Info: Command: quartus_sta ACync -c ACync
Info (P0): qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity dcfifo_h0l1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_0f9:dffpipe17|dffe18a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_ve9:dffpipe14|dffe15a* 
    Info (332165): Entity dcfifo_o1l1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_te9:dffpipe15|dffe16a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_se9:dffpipe12|dffe13a* 
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ACync.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info (332110): Deriving PLL clocks
    Info (332110): create_clock -period 10.000 -waveform {0.000 5.000} -name Clk100 Clk100
    Info (332110): create_generated_clock -source {60MHz|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 3 -duty_cycle 50.00 -name {60MHz|altpll_component|auto_generated|pll1|clk[0]} {60MHz|altpll_component|auto_generated|pll1|clk[0]}
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name uberACync:Sink|FifoDigRdClk uberACync:Sink|FifoDigRdClk
    Info (332105): create_clock -period 1.000 -name uberACync:Sink|FifoDigWrClk uberACync:Sink|FifoDigWrClk
    Info (332105): create_clock -period 1.000 -name uberACync:Sink|FifoAnaRdClk uberACync:Sink|FifoAnaRdClk
    Info (332105): create_clock -period 1.000 -name uberACync:Sink|FifoAnaWrClk uberACync:Sink|FifoAnaWrClk
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (P0): Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (P0): Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -8.006
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -8.006            -176.267 60MHz|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -6.764            -826.762 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -4.992            -594.061 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -4.025            -276.811 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -3.082            -320.853 uberACync:Sink|FifoAnaRdClk 
Info (332146): Worst-case hold slack is -1.718
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.718             -50.989 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -1.660             -47.267 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -1.615              -3.230 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -0.317              -0.942 60MHz|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.455               0.000 uberACync:Sink|FifoAnaRdClk 
Info (332146): Worst-case recovery slack is -1.066
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.066             -92.692 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -0.942            -133.263 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -0.628             -45.200 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -0.197              -9.346 uberACync:Sink|FifoDigRdClk 
Info (332146): Worst-case removal slack is -1.336
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.336            -200.249 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -0.552             -82.954 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -0.540             -38.795 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -0.086              -7.331 uberACync:Sink|FifoDigWrClk 
Info (332146): Worst-case minimum pulse width slack is -3.201
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.201            -436.665 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -3.201            -418.821 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -3.201            -414.360 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -3.201            -347.616 uberACync:Sink|FifoDigRdClk 
    Info (332119):     4.851               0.000 Clk100 
    Info (332119):     8.025               0.000 60MHz|altpll_component|auto_generated|pll1|clk[0] 
Info (332114): Report Metastability: Found 62 synchronizer chains.
    Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info (P0): Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -7.337
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -7.337            -160.073 60MHz|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -6.211            -761.524 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -4.630            -547.631 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -3.686            -251.120 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -2.792            -289.875 uberACync:Sink|FifoAnaRdClk 
Info (332146): Worst-case hold slack is -1.464
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.464             -43.265 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -1.429              -2.858 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -1.394             -39.280 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -0.429              -1.276 60MHz|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.403               0.000 uberACync:Sink|FifoAnaRdClk 
Info (332146): Worst-case recovery slack is -1.077
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.077             -93.670 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -0.935            -136.110 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -0.658             -47.351 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -0.228             -12.380 uberACync:Sink|FifoDigRdClk 
Info (332146): Worst-case removal slack is -1.189
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.189            -176.471 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -0.443             -62.701 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -0.435             -31.235 uberACync:Sink|FifoAnaWrClk 
    Info (332119):     0.000               0.000 uberACync:Sink|FifoDigWrClk 
Info (332146): Worst-case minimum pulse width slack is -3.201
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.201            -436.665 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -3.201            -418.821 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -3.201            -414.360 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -3.201            -347.616 uberACync:Sink|FifoDigRdClk 
    Info (332119):     4.849               0.000 Clk100 
    Info (332119):     8.025               0.000 60MHz|altpll_component|auto_generated|pll1|clk[0] 
Info (332114): Report Metastability: Found 62 synchronizer chains.
    Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info (P0): Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.811
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.811             -85.142 60MHz|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -2.387            -274.970 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -1.780            -192.249 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -1.158             -48.569 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -0.834             -64.166 uberACync:Sink|FifoAnaRdClk 
Info (332146): Worst-case hold slack is -1.072
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.072              -2.144 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -1.036             -31.545 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -1.026             -30.252 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -0.031              -0.089 60MHz|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.186               0.000 uberACync:Sink|FifoAnaRdClk 
Info (332146): Worst-case recovery slack is -0.408
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.408             -35.417 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -0.323             -43.788 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -0.209             -14.982 uberACync:Sink|FifoAnaWrClk 
    Info (332119):     0.003               0.000 uberACync:Sink|FifoDigRdClk 
Info (332146): Worst-case removal slack is -0.814
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.814            -124.558 uberACync:Sink|FifoDigRdClk 
    Info (332119):    -0.466             -77.261 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -0.458             -32.959 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -0.252             -21.880 uberACync:Sink|FifoDigWrClk 
Info (332146): Worst-case minimum pulse width slack is -1.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.000            -183.000 uberACync:Sink|FifoDigWrClk 
    Info (332119):    -1.000            -171.000 uberACync:Sink|FifoAnaRdClk 
    Info (332119):    -1.000            -168.000 uberACync:Sink|FifoAnaWrClk 
    Info (332119):    -1.000            -160.000 uberACync:Sink|FifoDigRdClk 
    Info (332119):     4.414               0.000 Clk100 
    Info (332119):     8.115               0.000 60MHz|altpll_component|auto_generated|pll1|clk[0] 
Info (332114): Report Metastability: Found 62 synchronizer chains.
    Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 536 megabytes
    Info: Processing ended: Tue Mar 31 14:48:43 2015
    Info: Elapsed time: 00:00:08
    Info: Total CPU time (on all processors): 00:00:07


