Index of /~astummer/Archives/2015 ACync/Pics

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[IMG]01. Controlling document.jpg2015-01-30 20:36 911K 
[IMG]02. Phase shifted zero crossing, Rev-A.jpg2015-02-26 17:21 128K 
[IMG]03. Zero crossing with no phase shifting, Rev-A.jpg2015-02-26 17:22 128K 
[IMG]04. Passthrough mode, delay of digital out, Rev-A.jpg2015-02-26 19:12 118K 
[IMG]07. Analog channel, zero phase delay, Rev-A.jpg2015-02-27 20:02 219K 
[IMG]08. Analog channel, quarter cycle phase delay, Rev-A.jpg2015-02-27 20:00 220K 
[IMG]09. Analog channel, half cycle phase delay, Rev-A.jpg2015-02-27 20:02 220K 
[IMG]10. Analog channel, almost full cycle phase delay, Rev-A.jpg2015-02-27 20:03 220K 
[IMG]11. Analog delay range in Passthrough mode, Rev-A.jpg2015-02-27 21:48 112K 
[IMG]12. Wall wart supply current (500mA per div), Rev-A.jpg2015-02-27 19:55 149K 
[IMG]13. Analog channel current foldback into 1 Ohm load, Rev-A.jpg2015-03-03 20:25 126K 
[IMG]50. Ramp generated in Verilog, Rev-B.jpg2015-03-31 15:06 81K 
[IMG]Front Panel.jpg2015-04-01 16:32 413K 
[IMG]Isometric, no cover.jpg2015-04-01 16:30 1.8M 
[DIR]Rev-A/2015-04-21 21:20 -  
[IMG]Timing diagram.gif2015-02-19 22:15 5.4K 
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