![[ICO]](/icons/blank.gif) | Name | Last modified | Size | Description |
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![[PARENTDIR]](/icons/back.gif) | Parent Directory | | - | |
![[IMG]](/icons/image2.gif) | 01. Controlling document.jpg | 2015-01-30 20:36 | 911K | |
![[IMG]](/icons/image2.gif) | Timing diagram.gif | 2015-02-19 22:15 | 5.4K | |
![[IMG]](/icons/image2.gif) | 02. Phase shifted zero crossing, Rev-A.jpg | 2015-02-26 17:21 | 128K | |
![[IMG]](/icons/image2.gif) | 03. Zero crossing with no phase shifting, Rev-A.jpg | 2015-02-26 17:22 | 128K | |
![[IMG]](/icons/image2.gif) | 04. Passthrough mode, delay of digital out, Rev-A.jpg | 2015-02-26 19:12 | 118K | |
![[IMG]](/icons/image2.gif) | 12. Wall wart supply current (500mA per div), Rev-A.jpg | 2015-02-27 19:55 | 149K | |
![[IMG]](/icons/image2.gif) | 08. Analog channel, quarter cycle phase delay, Rev-A.jpg | 2015-02-27 20:00 | 220K | |
![[IMG]](/icons/image2.gif) | 07. Analog channel, zero phase delay, Rev-A.jpg | 2015-02-27 20:02 | 219K | |
![[IMG]](/icons/image2.gif) | 09. Analog channel, half cycle phase delay, Rev-A.jpg | 2015-02-27 20:02 | 220K | |
![[IMG]](/icons/image2.gif) | 10. Analog channel, almost full cycle phase delay, Rev-A.jpg | 2015-02-27 20:03 | 220K | |
![[IMG]](/icons/image2.gif) | 11. Analog delay range in Passthrough mode, Rev-A.jpg | 2015-02-27 21:48 | 112K | |
![[IMG]](/icons/image2.gif) | 13. Analog channel current foldback into 1 Ohm load, Rev-A.jpg | 2015-03-03 20:25 | 126K | |
![[IMG]](/icons/image2.gif) | 50. Ramp generated in Verilog, Rev-B.jpg | 2015-03-31 15:06 | 81K | |
![[IMG]](/icons/image2.gif) | Isometric, no cover.jpg | 2015-04-01 16:30 | 1.8M | |
![[IMG]](/icons/image2.gif) | Front Panel.jpg | 2015-04-01 16:32 | 413K | |
![[DIR]](/icons/folder.gif) | Rev-A/ | 2015-04-21 21:20 | - | |
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