Nyquie Plus Internal Protocols ================================================= Started 2016 March Alan Stummer, University of Toronto Last revision: n/a The host computer sends commands to the MCU (Rabbit). Depending on the command, the MCU communicates with the FPGA. NOMENCLATURE ==================================== Sequence: The list of commands to execute, held in the FPGA Command: a 72-bit string with the function and its data Function: 8-bits, what the command does Data: 64-bit, any data for the command MCU COMMUNICATION WITH FPGA PROTOCOL ==================================== MCU is the master. Assume FPGA is far faster than MCU. The FPGA always pumps out its data at the same time. Format is 72-bit clocked serial, as described below. 1) Ensure CS and Clk are low. 2) Blip clk high then low to clock in low CS 3) Set CS high. 4) Set data, MSB first. 5) Clk high. 6) If reading from FPGA, read the bit. 7) Clk low. 8) Repeat for all bits. 9) CS low. 10) Blip clk high then low to clock in low CS SERIAL DATA FORMAT, MCU to FPGA ==================================== Bits Description ----- ----------- 71:64 8-bit FPGA command, or DDS register address 63:0 64-bit FPGA data, or DDS register data SERIAL DATA FORMAT, FPGA to MCU ==================================== Bits Description ----- ----------- 71:68 4-bit MS HDL version 67:64 4-bit LS HDL version 63:0 zeros FPGA COMMANDS ==================================== Func Description ---- ----------- 0x00 MCU reads FPGA version 0x01 Stop (running the sequence) 0x02 Run (the sequence) 0x03 Clear the sequence 0x04 [not used] 0x05 Loop back to start of sequence 0x06 Go to next valid profile 0x07 Wait for Trigger 0x08 Start the ramp 0x09 Wait number of cycles 0x0A Save ramp end frequency in FPGA (bits[31:0]) 0x0B [not used] 0x0C Delay from (burst) Trigger to start of processing ... [not used] 0x7F [not used] >0x7F loads an AD9914 DDS register where DDS address + 0x80 is the function and DDS data is the right justified data ***** MCU RCM6760 PORT MAPPING ************ Note that I/O direction "x" must be left as is PORT DIR DESCRIPTION ---------------------------------------------- PA0 - PA1 - PA2 - PA3 - PA4 - PA5 - PA6 - PA7 - PB0 x [reserved for RCM6760] PB1 x [reserved for ISP] PB2 - PB3 - PB4 - PB5 - PB6 - PB7 - PC0 - PC1 - PC2 O Test point PC3 - PC4 - PC5 O Display async data PC6 x [reserved for ISP] PC7 x [reserved for ISP] PD0 O Clock to FPGA PD1 O Data to FPGA PD2 I Data from FPGA PD3 O CS to FPGA PD4 x [reserved for RCM6760] PD5 x [reserved for RCM6760] PD6 x [reserved for RCM6760] PD7 x [reserved for RCM6760] PE0 O Data to VCO PE1 O Clock to VCO PE2 O LE for VCO PE3 - PE4 x [reserved for RCM6760] PE5 - PE6 - PE7 -