Analysis & Elaboration report for Nyquie_Plus
Wed Mar 23 13:43:53 2016
Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Elaboration Summary
  3. Parallel Compilation
  4. Analysis & Elaboration Settings
  5. Analysis & Elaboration Messages



----------------
; Legal Notice ;
----------------
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that your use is for the sole purpose of programming logic 
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agreement for further details.



+--------------------------------------------------------------------------------------+
; Analysis & Elaboration Summary                                                       ;
+------------------------------------+-------------------------------------------------+
; Analysis & Elaboration Status      ; Successful - Wed Mar 23 13:43:53 2016           ;
; Quartus Prime Version              ; 15.1.0 Build 185 10/21/2015 SJ Standard Edition ;
; Revision Name                      ; Nyquie_Plus                                     ;
; Top-level Entity Name              ; Nyquie_Plus                                     ;
; Family                             ; MAX 10                                          ;
; Total logic elements               ; N/A until Partition Merge                       ;
;     Total combinational functions  ; N/A until Partition Merge                       ;
;     Dedicated logic registers      ; N/A until Partition Merge                       ;
; Total registers                    ; N/A until Partition Merge                       ;
; Total pins                         ; N/A until Partition Merge                       ;
; Total virtual pins                 ; N/A until Partition Merge                       ;
; Total memory bits                  ; N/A until Partition Merge                       ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                       ;
; Total PLLs                         ; N/A until Partition Merge                       ;
; UFM blocks                         ; N/A until Partition Merge                       ;
; ADC blocks                         ; N/A until Partition Merge                       ;
+------------------------------------+-------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Elaboration Settings                                                                                      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; 10M08SAE144I7G     ;                    ;
; Top-level entity name                                                      ; Nyquie_Plus        ; Nyquie_Plus        ;
; Family name                                                                ; MAX 10             ; Cyclone V          ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------+
; Analysis & Elaboration Messages ;
+---------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Elaboration
    Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition
    Info: Processing started: Wed Mar 23 13:43:41 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Nyquie_Plus -c Nyquie_Plus --analysis_and_elaboration
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file nyquie_plus.bdf
    Info (12023): Found entity 1: Nyquie_Plus
Info (12021): Found 1 design units, including 1 entities, in source file ubernyquieplus.sv
    Info (12023): Found entity 1: UberNyquiePlus File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 24
Info (12127): Elaborating entity "Nyquie_Plus" for the top level hierarchy
Info (12128): Elaborating entity "UberNyquiePlus" for hierarchy "UberNyquiePlus:SortaUnique"
Warning (10036): Verilog HDL or VHDL warning at UberNyquiePlus.sv(47): object "RampEndFreq" assigned a value but never read File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 47
Warning (10858): Verilog HDL warning at UberNyquiePlus.sv(52): object ProfileHighest used but never assigned File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 52
Warning (10230): Verilog HDL assignment warning at UberNyquiePlus.sv(70): truncated value with size 25 to match size of target (24) File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 70
Warning (10230): Verilog HDL assignment warning at UberNyquiePlus.sv(117): truncated value with size 25 to match size of target (24) File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 117
Warning (10030): Net "D[7..3]" at UberNyquiePlus.sv(33) has no driver or initial value, using a default initial value '0' File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 33
Warning (10030): Net "ProfileHighest" at UberNyquiePlus.sv(52) has no driver or initial value, using a default initial value '0' File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 52
Warning (10034): Output port "IOupdate" at UberNyquiePlus.sv(34) has no driver File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 34
Warning (10034): Output port "DRctrl" at UberNyquiePlus.sv(37) has no driver File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 37
Warning (10034): Output port "Clk10" at UberNyquiePlus.sv(38) has no driver File: D:/Projects/2016 Nyquie Plus/Verilog/UberNyquiePlus.sv Line: 38
Info: Quartus Prime Analysis & Elaboration was successful. 0 errors, 9 warnings
    Info: Peak virtual memory: 817 megabytes
    Info: Processing ended: Wed Mar 23 13:43:53 2016
    Info: Elapsed time: 00:00:12
    Info: Total CPU time (on all processors): 00:00:24


