D:/Projects/2016 High Nyquist DDS/Verilog/TwoPortRam.v

Mar 09 04PM:03:46>: The following design file, which has identical name but a different extension 
from the specified variation file, already exists in the working directory:

TwoPortRam.vhd

This may create a conflict of design files and/or lead to undesirable side
effects.

Is it OK to continue file generation?