EDA Netlist Writer report for DigiPid
Wed Dec 06 11:24:04 2017
Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Settings
  4. Simulation Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Dec 06 11:24:04 2017 ;
; Revision Name             ; DigiPid                               ;
; Top-level Entity Name     ; DigiPid                               ;
; Family                    ; MAX 10                                ;
; Simulation Files Creation ; Successful                            ;
+---------------------------+---------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                                           ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option                                                                                            ; Setting                   ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only                                                   ; Off                       ;
; Time scale                                                                                        ; 1 ps                      ;
; Truncate long hierarchy paths                                                                     ; Off                       ;
; Map illegal HDL characters                                                                        ; Off                       ;
; Flatten buses into individual nodes                                                               ; Off                       ;
; Maintain hierarchy                                                                                ; Off                       ;
; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
; Enable glitch filtering                                                                           ; Off                       ;
; Do not write top level VHDL entity                                                                ; Off                       ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
; Architecture name in VHDL output netlist                                                          ; structure                 ;
; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
+---------------------------------------------------------------------------------------------------+---------------------------+


+----------------------------------------------------------------+
; Simulation Generated Files                                     ;
+----------------------------------------------------------------+
; Generated Files                                                ;
+----------------------------------------------------------------+
; D:/Projects/2016_DigiPid/Altera/simulation/modelsim/DigiPid.vo ;
+----------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition
    Info: Processing started: Wed Dec 06 11:24:02 2017
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off DigiPid -c DigiPid
Warning (10905): Generated the EDA functional simulation files although EDA timing simulation option is chosen.
Info (204019): Generated file DigiPid.vo in folder "D:/Projects/2016_DigiPid/Altera/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 725 megabytes
    Info: Processing ended: Wed Dec 06 11:24:04 2017
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


