<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">Flow report for DigiPid
Tue Jan 23 16:50:41 2018
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log
  8. Flow Messages
  9. Flow Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2017  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; Flow Summary                                                                         ;
+------------------------------------+-------------------------------------------------+
; Flow Status                        ; Successful - Tue Jan 23 16:50:41 2018           ;
; Quartus Prime Version              ; 17.1.0 Build 590 10/25/2017 SJ Standard Edition ;
; Revision Name                      ; DigiPid                                         ;
; Top-level Entity Name              ; DigiPid                                         ;
; Family                             ; MAX 10                                          ;
; Device                             ; 10M08SAE144I7G                                  ;
; Timing Models                      ; Final                                           ;
; Total logic elements               ; 2,974 / 8,064 ( 37 % )                          ;
;     Total combinational functions  ; 2,083 / 8,064 ( 26 % )                          ;
;     Dedicated logic registers      ; 1,958 / 8,064 ( 24 % )                          ;
; Total registers                    ; 1958                                            ;
; Total pins                         ; 68 / 101 ( 67 % )                               ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 54,272 / 387,072 ( 14 % )                       ;
; Embedded Multiplier 9-bit elements ; 8 / 48 ( 17 % )                                 ;
; Total PLLs                         ; 1 / 1 ( 100 % )                                 ;
; UFM blocks                         ; 0 / 1 ( 0 % )                                   ;
; ADC blocks                         ; 0 / 1 ( 0 % )                                   ;
+------------------------------------+-------------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date &amp; time ; 01/23/2018 16:48:51 ;
; Main task         ; Compilation         ;
; Revision Name     ; DigiPid             ;
+-------------------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                                                                                                                                                                                                                                                                                ;
+--------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------------+
; Assignment Name                      ; Value                                                                                                                                                                                                                                                                                   ; Default Value ; Entity Name ; Section Id       ;
+--------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------------+
; COMPILER_SIGNATURE_ID                ; 31350056883063.151674413107636                                                                                                                                                                                                                                                          ; --            ; --          ; --               ;
; EDA_OUTPUT_DATA_FORMAT               ; Verilog Hdl                                                                                                                                                                                                                                                                             ; --            ; --          ; eda_simulation   ;
; EDA_SIMULATION_TOOL                  ; ModelSim-Altera (Verilog)                                                                                                                                                                                                                                                               ; &lt;None&gt;        ; --          ; --               ;
; EDA_TIME_SCALE                       ; 1 ps                                                                                                                                                                                                                                                                                    ; --            ; --          ; eda_simulation   ;
; ENABLE_SIGNALTAP                     ; On                                                                                                                                                                                                                                                                                      ; --            ; --          ; --               ;
; FITTER_EFFORT                        ; Standard Fit                                                                                                                                                                                                                                                                            ; Auto Fit      ; --          ; --               ;
; FLOW_ENABLE_POWER_ANALYZER           ; On                                                                                                                                                                                                                                                                                      ; Off           ; --          ; --               ;
; MAX_CORE_JUNCTION_TEMP               ; 85                                                                                                                                                                                                                                                                                      ; --            ; --          ; --               ;
; MIN_CORE_JUNCTION_TEMP               ; 0                                                                                                                                                                                                                                                                                       ; --            ; --          ; --               ;
; MISC_FILE                            ; PLL.bsf                                                                                                                                                                                                                                                                                 ; --            ; --          ; --               ;
; MISC_FILE                            ; PLL_bb.v                                                                                                                                                                                                                                                                                ; --            ; --          ; --               ;
; MISC_FILE                            ; PLL.ppf                                                                                                                                                                                                                                                                                 ; --            ; --          ; --               ;
; MISC_FILE                            ; DP_RAM.bsf                                                                                                                                                                                                                                                                              ; --            ; --          ; --               ;
; MISC_FILE                            ; DP_RAM_bb.v                                                                                                                                                                                                                                                                             ; --            ; --          ; --               ;
; MISC_FILE                            ; FreqCounter.bsf                                                                                                                                                                                                                                                                         ; --            ; --          ; --               ;
; MISC_FILE                            ; FreqCounter_bb.v                                                                                                                                                                                                                                                                        ; --            ; --          ; --               ;
; OPTIMIZATION_MODE                    ; High Performance Effort                                                                                                                                                                                                                                                                 ; Balanced      ; --          ; --               ;
; PARTITION_COLOR                      ; -- (Not supported for targeted family)                                                                                                                                                                                                                                                  ; --            ; --          ; Top              ;
; PARTITION_FITTER_PRESERVATION_LEVEL  ; -- (Not supported for targeted family)                                                                                                                                                                                                                                                  ; --            ; --          ; Top              ;
; PARTITION_NETLIST_TYPE               ; -- (Not supported for targeted family)                                                                                                                                                                                                                                                  ; --            ; --          ; Top              ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; On                                                                                                                                                                                                                                                                                      ; Off           ; --          ; --               ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; On                                                                                                                                                                                                                                                                                      ; Off           ; --          ; --               ;
; PLACEMENT_EFFORT_MULTIPLIER          ; 4.0                                                                                                                                                                                                                                                                                     ; 1.0           ; --          ; --               ;
; POWER_AUTO_COMPUTE_TJ                ; Off                                                                                                                                                                                                                                                                                     ; On            ; --          ; --               ;
; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE   ; 12.5 %                                                                                                                                                                                                                                                                                  ; 12.5%         ; --          ; --               ;
; PROJECT_OUTPUT_DIRECTORY             ; D:\Projects\2016_DigiPid\Altera                                                                                                                                                                                                                                                         ; --            ; --          ; --               ;
; ROUTER_TIMING_OPTIMIZATION_LEVEL     ; MAXIMUM                                                                                                                                                                                                                                                                                 ; Normal        ; --          ; --               ;
; SLD_FILE                             ; db/SignalTap VCO_auto_stripped.stp                                                                                                                                                                                                                                                      ; --            ; --          ; --               ;
; SLD_NODE_CREATOR_ID                  ; 110                                                                                                                                                                                                                                                                                     ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_ENTITY_NAME                 ; sld_signaltap                                                                                                                                                                                                                                                                           ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_RAM_BLOCK_TYPE=AUTO                                                                                                                                                                                                                                                                 ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_NODE_INFO=805334528                                                                                                                                                                                                                                                                 ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_POWER_UP_TRIGGER=0                                                                                                                                                                                                                                                                  ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0                                                                                                                                                                                                                                           ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_ATTRIBUTE_MEM_MODE=OFF                                                                                                                                                                                                                                                              ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_STATE_FLOW_USE_GENERATED=0                                                                                                                                                                                                                                                          ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_STATE_BITS=11                                                                                                                                                                                                                                                                       ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_BUFFER_FULL_STOP=1                                                                                                                                                                                                                                                                  ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_CURRENT_RESOURCE_WIDTH=1                                                                                                                                                                                                                                                            ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_INCREMENTAL_ROUTING=1                                                                                                                                                                                                                                                               ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_TRIGGER_LEVEL=1                                                                                                                                                                                                                                                                     ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_TRIGGER_IN_ENABLED=0                                                                                                                                                                                                                                                                ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_TRIGGER_LEVEL_PIPELINE=1                                                                                                                                                                                                                                                            ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_ADVANCED_TRIGGER_ENTITY=basic,1,                                                                                                                                                                                                                                                    ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_ENABLE_ADVANCED_TRIGGER=0                                                                                                                                                                                                                                                           ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_SEGMENT_SIZE=64                                                                                                                                                                                                                                                                     ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_SAMPLE_DEPTH=64                                                                                                                                                                                                                                                                     ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_DATA_BITS=80                                                                                                                                                                                                                                                                        ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_TRIGGER_BITS=80                                                                                                                                                                                                                                                                     ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_STORAGE_QUALIFIER_BITS=80                                                                                                                                                                                                                                                           ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_INVERSION_MASK_LENGTH=260                                                                                                                                                                                                                                                           ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_TRIGGER_PIPELINE=0                                                                                                                                                                                                                                                                  ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_RAM_PIPELINE=0                                                                                                                                                                                                                                                                      ; --            ; --          ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT        ; SLD_COUNTER_PIPELINE=0                                                                                                                                                                                                                                                                  ; --            ; --          ; auto_signaltap_0 ;
; TIMEQUEST_DO_REPORT_TIMING           ; On                                                                                                                                                                                                                                                                                      ; Off           ; --          ; --               ;
; USE_SIGNALTAP_FILE                   ; SignalTap VCO.stp                                                                                                                                                                                                                                                                       ; --            ; --          ; --               ;
; VERILOG_INPUT_VERSION                ; SystemVerilog_2005                                                                                                                                                                                                                                                                      ; Verilog_2001  ; --          ; --               ;
; VERILOG_SHOW_LMF_MAPPING_MESSAGES    ; Off                                                                                                                                                                                                                                                                                     ; --            ; --          ; --               ;
+--------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                             ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis &amp; Synthesis      ; 00:00:51     ; 1.0                     ; 752 MB              ; 00:01:13                           ;
; Fitter                    ; 00:00:26     ; 1.3                     ; 1443 MB             ; 00:00:37                           ;
; Assembler                 ; 00:00:02     ; 1.0                     ; 551 MB              ; 00:00:02                           ;
; Power Analyzer            ; 00:00:14     ; 1.2                     ; 695 MB              ; 00:00:15                           ;
; TimeQuest Timing Analyzer ; 00:00:06     ; 1.6                     ; 663 MB              ; 00:00:07                           ;
; EDA Netlist Writer        ; 00:00:04     ; 1.0                     ; 550 MB              ; 00:00:04                           ;
; Total                     ; 00:01:43     ; --                      ; --                  ; 00:02:18                           ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+


+------------------------------------------------------------------------------------------+
; Flow OS Summary                                                                          ;
+---------------------------+------------------+-------------+------------+----------------+
; Module Name               ; Machine Hostname ; OS Name     ; OS Version ; Processor type ;
+---------------------------+------------------+-------------+------------+----------------+
; Analysis &amp; Synthesis      ; Erbium           ; Windows 8.1 ; 6.3        ; x86_64         ;
; Fitter                    ; Erbium           ; Windows 8.1 ; 6.3        ; x86_64         ;
; Assembler                 ; Erbium           ; Windows 8.1 ; 6.3        ; x86_64         ;
; Power Analyzer            ; Erbium           ; Windows 8.1 ; 6.3        ; x86_64         ;
; TimeQuest Timing Analyzer ; Erbium           ; Windows 8.1 ; 6.3        ; x86_64         ;
; EDA Netlist Writer        ; Erbium           ; Windows 8.1 ; 6.3        ; x86_64         ;
+---------------------------+------------------+-------------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off DigiPid -c DigiPid
quartus_fit --read_settings_files=off --write_settings_files=off DigiPid -c DigiPid
quartus_asm --read_settings_files=off --write_settings_files=off DigiPid -c DigiPid
quartus_pow --read_settings_files=off --write_settings_files=off DigiPid -c DigiPid
quartus_sta DigiPid -c DigiPid
quartus_eda --read_settings_files=off --write_settings_files=off DigiPid -c DigiPid



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