Analysis & Synthesis report for DigiPid
Tue Jan 23 16:49:43 2018
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis DSP Block Usage Summary
 10. Analysis & Synthesis IP Cores Summary
 11. User-Specified and Inferred Latches
 12. Registers Removed During Synthesis
 13. Removed Registers Triggering Further Register Optimizations
 14. General Register Statistics
 15. Inverted Register Statistics
 16. Physical Synthesis Netlist Optimizations
 17. Multiplexer Restructuring Statistics (Restructuring Performed)
 18. Source assignments for DP_RAM:HistoryADC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated
 19. Source assignments for DP_RAM:HistoryDAC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated
 20. Source assignments for sld_signaltap:auto_signaltap_0
 21. Source assignments for UberDigiPid:inst|altsyncram:XferLut_rtl_0|altsyncram_h2e1:auto_generated
 22. Parameter Settings for User Entity Instance: PLL:inst3|altpll:altpll_component
 23. Parameter Settings for User Entity Instance: DP_RAM:HistoryADC|altsyncram:altsyncram_component
 24. Parameter Settings for User Entity Instance: DP_RAM:HistoryDAC|altsyncram:altsyncram_component
 25. Parameter Settings for User Entity Instance: FreqCounter:VCO|lpm_counter:LPM_COUNTER_component
 26. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 27. Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|altsyncram:XferLut_rtl_0
 28. Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|lpm_mult:Mult3
 29. Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|lpm_mult:Mult2
 30. Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|lpm_mult:Mult0
 31. Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|lpm_mult:Mult1
 32. altpll Parameter Settings by Entity Instance
 33. altsyncram Parameter Settings by Entity Instance
 34. lpm_mult Parameter Settings by Entity Instance
 35. Signal Tap Logic Analyzer Settings
 36. Post-Synthesis Netlist Statistics for Top Partition
 37. Post-Synthesis Netlist Statistics for Partition sld_signaltap:auto_signaltap_0
 38. Post-Synthesis Netlist Statistics for Partition sld_hub:auto_hub
 39. Elapsed Time Per Partition
 40. Connections to In-System Debugging Instance "auto_signaltap_0"
 41. Analysis & Synthesis Messages
 42. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2017  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                         ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Jan 23 16:49:43 2018           ;
; Quartus Prime Version              ; 17.1.0 Build 590 10/25/2017 SJ Standard Edition ;
; Revision Name                      ; DigiPid                                         ;
; Top-level Entity Name              ; DigiPid                                         ;
; Family                             ; MAX 10                                          ;
; Total logic elements               ; 3,276                                           ;
;     Total combinational functions  ; 2,081                                           ;
;     Dedicated logic registers      ; 1,990                                           ;
; Total registers                    ; 1990                                            ;
; Total pins                         ; 67                                              ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 54,272                                          ;
; Embedded Multiplier 9-bit elements ; 8                                               ;
; Total PLLs                         ; 1                                               ;
; UFM blocks                         ; 0                                               ;
; ADC blocks                         ; 0                                               ;
+------------------------------------+-------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; 10M08SAE144I7G     ;                    ;
; Top-level entity name                                                      ; DigiPid            ; DigiPid            ;
; Family name                                                                ; MAX 10             ; Cyclone V          ;
; Verilog Show LMF Mapping Messages                                          ; Off                ;                    ;
; Verilog Version                                                            ; SystemVerilog_2005 ; Verilog_2001       ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                              ; Enable             ; Enable             ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; Power Optimization During Synthesis                                        ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.1%      ;
;     Processor 3            ;   0.0%      ;
;     Processor 4            ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                                 ;
+--------------------------------------------------------------------+-----------------+----------------------------------------------+----------------------------------------------------------------------------------------------------+-------------+
; File Name with User-Entered Path                                   ; Used in Netlist ; File Type                                    ; File Name with Absolute Path                                                                       ; Library     ;
+--------------------------------------------------------------------+-----------------+----------------------------------------------+----------------------------------------------------------------------------------------------------+-------------+
; DigiPid.bdf                                                        ; yes             ; User Block Diagram/Schematic File            ; D:/Projects/2016_DigiPid/Altera/DigiPid.bdf                                                        ;             ;
; DigiPid.sv                                                         ; yes             ; User SystemVerilog HDL File                  ; D:/Projects/2016_DigiPid/Altera/DigiPid.sv                                                         ;             ;
; PLL.v                                                              ; yes             ; User Wizard-Generated File                   ; D:/Projects/2016_DigiPid/Altera/PLL.v                                                              ;             ;
; DP_RAM.v                                                           ; yes             ; User Wizard-Generated File                   ; D:/Projects/2016_DigiPid/Altera/DP_RAM.v                                                           ;             ;
; FreqCounter.v                                                      ; yes             ; User Wizard-Generated File                   ; D:/Projects/2016_DigiPid/Altera/FreqCounter.v                                                      ;             ;
; altpll.tdf                                                         ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/altpll.tdf                                           ;             ;
; aglobal171.inc                                                     ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/aglobal171.inc                                       ;             ;
; stratix_pll.inc                                                    ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/stratix_pll.inc                                      ;             ;
; stratixii_pll.inc                                                  ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/stratixii_pll.inc                                    ;             ;
; cycloneii_pll.inc                                                  ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/cycloneii_pll.inc                                    ;             ;
; db/pll_altpll.v                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/pll_altpll.v                                                    ;             ;
; altsyncram.tdf                                                     ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/altsyncram.tdf                                       ;             ;
; stratix_ram_block.inc                                              ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/stratix_ram_block.inc                                ;             ;
; lpm_mux.inc                                                        ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_mux.inc                                          ;             ;
; lpm_decode.inc                                                     ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_decode.inc                                       ;             ;
; a_rdenreg.inc                                                      ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/a_rdenreg.inc                                        ;             ;
; altrom.inc                                                         ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/altrom.inc                                           ;             ;
; altram.inc                                                         ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/altram.inc                                           ;             ;
; altdpram.inc                                                       ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/altdpram.inc                                         ;             ;
; db/altsyncram_82j1.tdf                                             ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/altsyncram_82j1.tdf                                             ;             ;
; lpm_counter.tdf                                                    ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_counter.tdf                                      ;             ;
; lpm_constant.inc                                                   ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_constant.inc                                     ;             ;
; lpm_add_sub.inc                                                    ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_add_sub.inc                                      ;             ;
; cmpconst.inc                                                       ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/cmpconst.inc                                         ;             ;
; lpm_compare.inc                                                    ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_compare.inc                                      ;             ;
; lpm_counter.inc                                                    ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_counter.inc                                      ;             ;
; dffeea.inc                                                         ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/dffeea.inc                                           ;             ;
; alt_counter_stratix.inc                                            ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/alt_counter_stratix.inc                              ;             ;
; db/cntr_a8i.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/cntr_a8i.tdf                                                    ;             ;
; sld_signaltap.vhd                                                  ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/sld_signaltap.vhd                                    ;             ;
; sld_signaltap_impl.vhd                                             ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd                               ;             ;
; sld_ela_control.vhd                                                ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_ela_control.vhd                                  ;             ;
; lpm_shiftreg.tdf                                                   ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_shiftreg.tdf                                     ;             ;
; sld_mbpmg.vhd                                                      ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_mbpmg.vhd                                        ;             ;
; sld_ela_trigger_flow_mgr.vhd                                       ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd                         ;             ;
; sld_buffer_manager.vhd                                             ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd                               ;             ;
; db/altsyncram_oc14.tdf                                             ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/altsyncram_oc14.tdf                                             ;             ;
; altdpram.tdf                                                       ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/altdpram.tdf                                         ;             ;
; memmodes.inc                                                       ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/others/maxplus2/memmodes.inc                                       ;             ;
; a_hdffe.inc                                                        ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/a_hdffe.inc                                          ;             ;
; alt_le_rden_reg.inc                                                ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/alt_le_rden_reg.inc                                  ;             ;
; altsyncram.inc                                                     ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/altsyncram.inc                                       ;             ;
; lpm_mux.tdf                                                        ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_mux.tdf                                          ;             ;
; muxlut.inc                                                         ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/muxlut.inc                                           ;             ;
; bypassff.inc                                                       ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/bypassff.inc                                         ;             ;
; altshift.inc                                                       ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/altshift.inc                                         ;             ;
; db/mux_g7c.tdf                                                     ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/mux_g7c.tdf                                                     ;             ;
; lpm_decode.tdf                                                     ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_decode.tdf                                       ;             ;
; declut.inc                                                         ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/declut.inc                                           ;             ;
; db/decode_3af.tdf                                                  ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/decode_3af.tdf                                                  ;             ;
; db/cntr_9rh.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/cntr_9rh.tdf                                                    ;             ;
; db/cmpr_jrb.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/cmpr_jrb.tdf                                                    ;             ;
; db/cntr_mfi.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/cntr_mfi.tdf                                                    ;             ;
; db/cntr_2rh.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/cntr_2rh.tdf                                                    ;             ;
; db/cmpr_grb.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/cmpr_grb.tdf                                                    ;             ;
; db/cntr_odi.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/cntr_odi.tdf                                                    ;             ;
; db/cmpr_drb.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/cmpr_drb.tdf                                                    ;             ;
; sld_rom_sr.vhd                                                     ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_rom_sr.vhd                                       ;             ;
; sld_jtag_endpoint_adapter.vhd                                      ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd                        ;             ;
; sld_jtag_endpoint_adapter_impl.sv                                  ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter_impl.sv                    ;             ;
; sld_hub.vhd                                                        ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_hub.vhd                                          ; altera_sld  ;
; db/ip/slde880867b/alt_sld_fab.v                                    ; yes             ; Encrypted Auto-Found Verilog HDL File        ; D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/alt_sld_fab.v                                    ; alt_sld_fab ;
; db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab.v             ; yes             ; Encrypted Auto-Found Verilog HDL File        ; D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab.v             ; alt_sld_fab ;
; db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_ident.sv      ; yes             ; Auto-Found SystemVerilog HDL File            ; D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_ident.sv      ; alt_sld_fab ;
; db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_presplit.sv   ; yes             ; Encrypted Auto-Found SystemVerilog HDL File  ; D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_presplit.sv   ; alt_sld_fab ;
; db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd ; yes             ; Encrypted Auto-Found VHDL File               ; D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd ; alt_sld_fab ;
; db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_splitter.sv   ; yes             ; Encrypted Auto-Found SystemVerilog HDL File  ; D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_splitter.sv   ; alt_sld_fab ;
; sld_jtag_hub.vhd                                                   ; yes             ; Encrypted Megafunction                       ; c:/intel/17.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd                                     ;             ;
; db/altsyncram_h2e1.tdf                                             ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/altsyncram_h2e1.tdf                                             ;             ;
; lpm_mult.tdf                                                       ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/lpm_mult.tdf                                         ;             ;
; multcore.inc                                                       ; yes             ; Megafunction                                 ; c:/intel/17.1/quartus/libraries/megafunctions/multcore.inc                                         ;             ;
; db/mult_bms.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/mult_bms.tdf                                                    ;             ;
; db/mult_1hs.tdf                                                    ; yes             ; Auto-Generated Megafunction                  ; D:/Projects/2016_DigiPid/Altera/db/mult_1hs.tdf                                                    ;             ;
+--------------------------------------------------------------------+-----------------+----------------------------------------------+----------------------------------------------------------------------------------------------------+-------------+


+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary               ;
+---------------------------------------------+-------------+
; Resource                                    ; Usage       ;
+---------------------------------------------+-------------+
; Estimated Total logic elements              ; 3,276       ;
;                                             ;             ;
; Total combinational functions               ; 2081        ;
; Logic element usage by number of LUT inputs ;             ;
;     -- 4 input functions                    ; 899         ;
;     -- 3 input functions                    ; 698         ;
;     -- <=2 input functions                  ; 484         ;
;                                             ;             ;
; Logic elements by mode                      ;             ;
;     -- normal mode                          ; 1500        ;
;     -- arithmetic mode                      ; 581         ;
;                                             ;             ;
; Total registers                             ; 1990        ;
;     -- Dedicated logic registers            ; 1990        ;
;     -- I/O registers                        ; 0           ;
;                                             ;             ;
; I/O pins                                    ; 67          ;
; Total memory bits                           ; 54272       ;
;                                             ;             ;
; Embedded Multiplier 9-bit elements          ; 8           ;
;                                             ;             ;
; Total PLLs                                  ; 1           ;
;     -- PLLs                                 ; 1           ;
;                                             ;             ;
; Maximum fan-out node                        ; TtlIn~input ;
; Maximum fan-out                             ; 811         ;
; Total fan-out                               ; 15334       ;
; Average fan-out                             ; 3.51        ;
+---------------------------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
; Compilation Hierarchy Node                                                                                                              ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name                                                                                                                                                                                                                                                                                                                                 ; Entity Name                       ; Library Name ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
; |DigiPid                                                                                                                                ; 2081 (1)            ; 1990 (0)                  ; 54272       ; 0          ; 8            ; 0       ; 4         ; 67   ; 0            ; 0          ; |DigiPid                                                                                                                                                                                                                                                                                                                                            ; DigiPid                           ; work         ;
;    |DP_RAM:HistoryADC|                                                                                                                  ; 0 (0)               ; 0 (0)                     ; 16384       ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|DP_RAM:HistoryADC                                                                                                                                                                                                                                                                                                                          ; DP_RAM                            ; work         ;
;       |altsyncram:altsyncram_component|                                                                                                 ; 0 (0)               ; 0 (0)                     ; 16384       ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|DP_RAM:HistoryADC|altsyncram:altsyncram_component                                                                                                                                                                                                                                                                                          ; altsyncram                        ; work         ;
;          |altsyncram_82j1:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 16384       ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|DP_RAM:HistoryADC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated                                                                                                                                                                                                                                                           ; altsyncram_82j1                   ; work         ;
;    |DP_RAM:HistoryDAC|                                                                                                                  ; 0 (0)               ; 0 (0)                     ; 16384       ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|DP_RAM:HistoryDAC                                                                                                                                                                                                                                                                                                                          ; DP_RAM                            ; work         ;
;       |altsyncram:altsyncram_component|                                                                                                 ; 0 (0)               ; 0 (0)                     ; 16384       ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|DP_RAM:HistoryDAC|altsyncram:altsyncram_component                                                                                                                                                                                                                                                                                          ; altsyncram                        ; work         ;
;          |altsyncram_82j1:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 16384       ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|DP_RAM:HistoryDAC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated                                                                                                                                                                                                                                                           ; altsyncram_82j1                   ; work         ;
;    |FreqCounter:VCO|                                                                                                                    ; 32 (0)              ; 32 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|FreqCounter:VCO                                                                                                                                                                                                                                                                                                                            ; FreqCounter                       ; work         ;
;       |lpm_counter:LPM_COUNTER_component|                                                                                               ; 32 (0)              ; 32 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|FreqCounter:VCO|lpm_counter:LPM_COUNTER_component                                                                                                                                                                                                                                                                                          ; lpm_counter                       ; work         ;
;          |cntr_a8i:auto_generated|                                                                                                      ; 32 (32)             ; 32 (32)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|FreqCounter:VCO|lpm_counter:LPM_COUNTER_component|cntr_a8i:auto_generated                                                                                                                                                                                                                                                                  ; cntr_a8i                          ; work         ;
;    |PLL:inst3|                                                                                                                          ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|PLL:inst3                                                                                                                                                                                                                                                                                                                                  ; PLL                               ; work         ;
;       |altpll:altpll_component|                                                                                                         ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|PLL:inst3|altpll:altpll_component                                                                                                                                                                                                                                                                                                          ; altpll                            ; work         ;
;          |PLL_altpll:auto_generated|                                                                                                    ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|PLL:inst3|altpll:altpll_component|PLL_altpll:auto_generated                                                                                                                                                                                                                                                                                ; PLL_altpll                        ; work         ;
;    |UberDigiPid:inst|                                                                                                                   ; 1377 (1377)         ; 652 (652)                 ; 16384       ; 0          ; 8            ; 0       ; 4         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst                                                                                                                                                                                                                                                                                                                           ; UberDigiPid                       ; work         ;
;       |altsyncram:XferLut_rtl_0|                                                                                                        ; 0 (0)               ; 0 (0)                     ; 16384       ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|altsyncram:XferLut_rtl_0                                                                                                                                                                                                                                                                                                  ; altsyncram                        ; work         ;
;          |altsyncram_h2e1:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 16384       ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|altsyncram:XferLut_rtl_0|altsyncram_h2e1:auto_generated                                                                                                                                                                                                                                                                   ; altsyncram_h2e1                   ; work         ;
;       |lpm_mult:Mult0|                                                                                                                  ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 2            ; 0       ; 1         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|lpm_mult:Mult0                                                                                                                                                                                                                                                                                                            ; lpm_mult                          ; work         ;
;          |mult_1hs:auto_generated|                                                                                                      ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 2            ; 0       ; 1         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|lpm_mult:Mult0|mult_1hs:auto_generated                                                                                                                                                                                                                                                                                    ; mult_1hs                          ; work         ;
;       |lpm_mult:Mult1|                                                                                                                  ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 2            ; 0       ; 1         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|lpm_mult:Mult1                                                                                                                                                                                                                                                                                                            ; lpm_mult                          ; work         ;
;          |mult_1hs:auto_generated|                                                                                                      ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 2            ; 0       ; 1         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|lpm_mult:Mult1|mult_1hs:auto_generated                                                                                                                                                                                                                                                                                    ; mult_1hs                          ; work         ;
;       |lpm_mult:Mult2|                                                                                                                  ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 2            ; 0       ; 1         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|lpm_mult:Mult2                                                                                                                                                                                                                                                                                                            ; lpm_mult                          ; work         ;
;          |mult_1hs:auto_generated|                                                                                                      ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 2            ; 0       ; 1         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|lpm_mult:Mult2|mult_1hs:auto_generated                                                                                                                                                                                                                                                                                    ; mult_1hs                          ; work         ;
;       |lpm_mult:Mult3|                                                                                                                  ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 2            ; 0       ; 1         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|lpm_mult:Mult3                                                                                                                                                                                                                                                                                                            ; lpm_mult                          ; work         ;
;          |mult_bms:auto_generated|                                                                                                      ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 2            ; 0       ; 1         ; 0    ; 0            ; 0          ; |DigiPid|UberDigiPid:inst|lpm_mult:Mult3|mult_bms:auto_generated                                                                                                                                                                                                                                                                                    ; mult_bms                          ; work         ;
;    |sld_hub:auto_hub|                                                                                                                   ; 127 (1)             ; 91 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_hub:auto_hub                                                                                                                                                                                                                                                                                                                           ; sld_hub                           ; altera_sld   ;
;       |alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric| ; 126 (0)             ; 91 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric                                                                                                                                                                                           ; alt_sld_fab_with_jtag_input       ; altera_sld   ;
;          |alt_sld_fab:instrumentation_fabric|                                                                                           ; 126 (0)             ; 91 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric                                                                                                                                                        ; alt_sld_fab                       ; alt_sld_fab  ;
;             |alt_sld_fab_alt_sld_fab:alt_sld_fab|                                                                                       ; 126 (1)             ; 91 (5)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab                                                                                                                    ; alt_sld_fab_alt_sld_fab           ; alt_sld_fab  ;
;                |alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|                                                                            ; 125 (0)             ; 86 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric                                                                        ; alt_sld_fab_alt_sld_fab_sldfabric ; alt_sld_fab  ;
;                   |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|                                                                        ; 125 (86)            ; 86 (58)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub                           ; sld_jtag_hub                      ; work         ;
;                      |sld_rom_sr:hub_info_reg|                                                                                          ; 21 (21)             ; 9 (9)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg   ; sld_rom_sr                        ; work         ;
;                      |sld_shadow_jsm:shadow_jsm|                                                                                        ; 18 (18)             ; 19 (19)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ; sld_shadow_jsm                    ; altera_sld   ;
;    |sld_signaltap:auto_signaltap_0|                                                                                                     ; 544 (2)             ; 1215 (160)                ; 5120        ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                                                                             ; sld_signaltap                     ; work         ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                                                           ; 542 (0)             ; 1055 (0)                  ; 5120        ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                                                                       ; sld_signaltap_impl                ; work         ;
;          |sld_signaltap_implb:sld_signaltap_body|                                                                                       ; 542 (88)            ; 1055 (392)                ; 5120        ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body                                                                                                                                                                                                                                ; sld_signaltap_implb               ; work         ;
;             |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|                                                            ; 15 (0)              ; 40 (40)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem                                                                                                                                                                 ; altdpram                          ; work         ;
;                |lpm_decode:wdecoder|                                                                                                    ; 2 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                             ; lpm_decode                        ; work         ;
;                   |decode_3af:auto_generated|                                                                                           ; 2 (2)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_3af:auto_generated                                                                                                                   ; decode_3af                        ; work         ;
;                |lpm_mux:mux|                                                                                                            ; 13 (0)              ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux                                                                                                                                                     ; lpm_mux                           ; work         ;
;                   |mux_g7c:auto_generated|                                                                                              ; 13 (13)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_g7c:auto_generated                                                                                                                              ; mux_g7c                           ; work         ;
;             |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                                                           ; 0 (0)               ; 0 (0)                     ; 5120        ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                                ; altsyncram                        ; work         ;
;                |altsyncram_oc14:auto_generated|                                                                                         ; 0 (0)               ; 0 (0)                     ; 5120        ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated                                                                                                                                                 ; altsyncram_oc14                   ; work         ;
;             |lpm_shiftreg:segment_offset_config_deserialize|                                                                            ; 0 (0)               ; 6 (6)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize                                                                                                                                                                                 ; lpm_shiftreg                      ; work         ;
;             |lpm_shiftreg:status_register|                                                                                              ; 17 (17)             ; 17 (17)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register                                                                                                                                                                                                   ; lpm_shiftreg                      ; work         ;
;             |serial_crc_16:\tdo_crc_gen:tdo_crc_calc|                                                                                   ; 14 (14)             ; 13 (13)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc                                                                                                                                                                                        ; serial_crc_16                     ; work         ;
;             |sld_buffer_manager:sld_buffer_manager_inst|                                                                                ; 50 (50)             ; 39 (39)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst                                                                                                                                                                                     ; sld_buffer_manager                ; work         ;
;             |sld_ela_control:ela_control|                                                                                               ; 189 (1)             ; 416 (1)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control                                                                                                                                                                                                    ; sld_ela_control                   ; work         ;
;                |lpm_shiftreg:trigger_config_deserialize|                                                                                ; 0 (0)               ; 4 (4)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                            ; lpm_shiftreg                      ; work         ;
;                |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|                                 ; 160 (0)             ; 400 (0)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                             ; sld_ela_basic_multi_level_trigger ; work         ;
;                   |lpm_shiftreg:trigger_condition_deserialize|                                                                          ; 0 (0)               ; 240 (240)                 ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                                  ; lpm_shiftreg                      ; work         ;
;                   |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                                                      ; 160 (0)             ; 160 (0)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                              ; sld_mbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1|                                                           ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1       ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1        ; sld_sbpmg                         ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|                                                            ; 2 (2)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1        ; sld_sbpmg                         ; work         ;
;                |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|                                                          ; 28 (28)             ; 11 (1)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity                                                                                                                                      ; sld_ela_trigger_flow_mgr          ; work         ;
;                   |lpm_shiftreg:trigger_config_deserialize|                                                                             ; 0 (0)               ; 10 (10)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize                                                                                              ; lpm_shiftreg                      ; work         ;
;             |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|                                          ; 139 (9)             ; 124 (0)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                               ; sld_offload_buffer_mgr            ; work         ;
;                |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                                                              ; 9 (0)               ; 7 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                                     ; lpm_counter                       ; work         ;
;                   |cntr_9rh:auto_generated|                                                                                             ; 9 (9)               ; 7 (7)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9rh:auto_generated                                                             ; cntr_9rh                          ; work         ;
;                |lpm_counter:read_pointer_counter|                                                                                       ; 6 (0)               ; 6 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                              ; lpm_counter                       ; work         ;
;                   |cntr_mfi:auto_generated|                                                                                             ; 6 (6)               ; 6 (6)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_mfi:auto_generated                                                                                      ; cntr_mfi                          ; work         ;
;                |lpm_counter:status_advance_pointer_counter|                                                                             ; 6 (0)               ; 4 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter                                                                                                    ; lpm_counter                       ; work         ;
;                   |cntr_2rh:auto_generated|                                                                                             ; 6 (6)               ; 4 (4)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_2rh:auto_generated                                                                            ; cntr_2rh                          ; work         ;
;                |lpm_counter:status_read_pointer_counter|                                                                                ; 3 (0)               ; 1 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter                                                                                                       ; lpm_counter                       ; work         ;
;                   |cntr_odi:auto_generated|                                                                                             ; 3 (3)               ; 1 (1)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_odi:auto_generated                                                                               ; cntr_odi                          ; work         ;
;                |lpm_shiftreg:info_data_shift_out|                                                                                       ; 13 (13)             ; 13 (13)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                              ; lpm_shiftreg                      ; work         ;
;                |lpm_shiftreg:ram_data_shift_out|                                                                                        ; 80 (80)             ; 80 (80)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                               ; lpm_shiftreg                      ; work         ;
;                |lpm_shiftreg:status_data_shift_out|                                                                                     ; 13 (13)             ; 13 (13)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out                                                                                                            ; lpm_shiftreg                      ; work         ;
;             |sld_rom_sr:crc_rom_sr|                                                                                                     ; 30 (30)             ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                          ; sld_rom_sr                        ; work         ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Name                                                                                                                                                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; DP_RAM:HistoryADC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 1024         ; 16           ; 1024         ; 16           ; 16384 ; None ;
; DP_RAM:HistoryDAC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 1024         ; 16           ; 1024         ; 16           ; 16384 ; None ;
; UberDigiPid:inst|altsyncram:XferLut_rtl_0|altsyncram_h2e1:auto_generated|ALTSYNCRAM                                                                                                                   ; AUTO ; Simple Dual Port ; 1024         ; 16           ; 1024         ; 16           ; 16384 ; None ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64           ; 80           ; 64           ; 80           ; 5120  ; None ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 4           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 8           ;
; Signed Embedded Multipliers           ; 3           ;
; Unsigned Embedded Multipliers         ; 1           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                                                                                                                                                              ; IP Include File ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric                                                                                 ;                 ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab                                             ;                 ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_presplit:presplit   ;                 ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ;                 ;
; Altera ; Signal Tap   ; N/A     ; N/A          ; Licensed     ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_splitter:splitter   ;                 ;
; Altera ; RAM: 2-PORT  ; 15.1    ; N/A          ; N/A          ; |DigiPid|DP_RAM:HistoryADC                                                                                                                                                                                                                                                   ; DP_RAM.v        ;
; Altera ; RAM: 2-PORT  ; 15.1    ; N/A          ; N/A          ; |DigiPid|DP_RAM:HistoryDAC                                                                                                                                                                                                                                                   ; DP_RAM.v        ;
; Altera ; ALTPLL       ; 17.1    ; N/A          ; N/A          ; |DigiPid|PLL:inst3                                                                                                                                                                                                                                                           ; PLL.v           ;
; Altera ; LPM_COUNTER  ; 15.1    ; N/A          ; N/A          ; |DigiPid|FreqCounter:VCO                                                                                                                                                                                                                                                     ; FreqCounter.v   ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+


+------------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                        ;
+-----------------------------------------------------+-----------------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal         ; Free of Timing Hazards ;
+-----------------------------------------------------+-----------------------------+------------------------+
; UberDigiPid:inst|Data4Mcu[15]                       ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[14]                       ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[13]                       ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[12]                       ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[11]                       ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[10]                       ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[9]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[8]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[7]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[6]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[5]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[4]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[3]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[2]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[1]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|Data4Mcu[0]                        ; McuRD                       ; yes                    ;
; UberDigiPid:inst|StatusRead                         ; UberDigiPid:inst|StatusRead ; yes                    ;
; Number of user-specified and inferred latches = 17  ;                             ;                        ;
+-----------------------------------------------------+-----------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                          ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                          ; Reason for Removal                                                                                                                                                                                 ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; UberDigiPid:inst|AdcTarget[16..31]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                             ;
; UberDigiPid:inst|Adc[16..31]                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                             ;
; UberDigiPid:inst|ModeOut                                                                                                                                                               ; Merged with UberDigiPid:inst|LocalReg[6][3]                                                                                                                                                        ;
; UberDigiPid:inst|TP1                                                                                                                                                                   ; Merged with UberDigiPid:inst|LocalReg[6][5]                                                                                                                                                        ;
; UberDigiPid:inst|LocalReg[1][15]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMin[15]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[0][15]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMax[15]                                                                                                                                                            ;
; UberDigiPid:inst|ModeOp[2]                                                                                                                                                             ; Merged with UberDigiPid:inst|LocalReg[6][2]                                                                                                                                                        ;
; UberDigiPid:inst|ModeOp[1]                                                                                                                                                             ; Merged with UberDigiPid:inst|LocalReg[6][1]                                                                                                                                                        ;
; UberDigiPid:inst|ModeOp[0]                                                                                                                                                             ; Merged with UberDigiPid:inst|LocalReg[6][0]                                                                                                                                                        ;
; UberDigiPid:inst|LocalReg[1][14]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMin[14]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[0][14]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMax[14]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[1][13]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMin[13]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[0][13]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMax[13]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[1][12]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMin[12]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[0][12]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMax[12]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[1][11]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMin[11]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[0][11]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMax[11]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[1][10]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMin[10]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[0][10]                                                                                                                                                       ; Merged with UberDigiPid:inst|DacMax[10]                                                                                                                                                            ;
; UberDigiPid:inst|LocalReg[1][9]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[9]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][9]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[9]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][8]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[8]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][8]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[8]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][7]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[7]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][7]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[7]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][6]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[6]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][6]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[6]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][5]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[5]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][5]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[5]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][4]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[4]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][4]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[4]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][3]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[3]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][3]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[3]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][2]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[2]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][2]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[2]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][1]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[1]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][1]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[1]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[1][0]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMin[0]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[0][0]                                                                                                                                                        ; Merged with UberDigiPid:inst|DacMax[0]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[7][11]                                                                                                                                                       ; Merged with UberDigiPid:inst|LocalReg[7][10]                                                                                                                                                       ;
; UberDigiPid:inst|LocalReg[7][12]                                                                                                                                                       ; Merged with UberDigiPid:inst|LocalReg[7][10]                                                                                                                                                       ;
; UberDigiPid:inst|LocalReg[7][13]                                                                                                                                                       ; Merged with UberDigiPid:inst|LocalReg[7][10]                                                                                                                                                       ;
; UberDigiPid:inst|LocalReg[7][15]                                                                                                                                                       ; Merged with UberDigiPid:inst|LocalReg[7][10]                                                                                                                                                       ;
; UberDigiPid:inst|LocalReg[7][7]                                                                                                                                                        ; Merged with UberDigiPid:inst|LocalReg[7][10]                                                                                                                                                       ;
; UberDigiPid:inst|LocalReg[7][8]                                                                                                                                                        ; Merged with UberDigiPid:inst|LocalReg[7][10]                                                                                                                                                       ;
; UberDigiPid:inst|LocalReg[7][9]                                                                                                                                                        ; Merged with UberDigiPid:inst|LocalReg[7][10]                                                                                                                                                       ;
; UberDigiPid:inst|LocalReg[7][6]                                                                                                                                                        ; Merged with UberDigiPid:inst|LocalReg[7][14]                                                                                                                                                       ;
; UberDigiPid:inst|LocalReg[6][7]                                                                                                                                                        ; Merged with UberDigiPid:inst|HistorySelect                                                                                                                                                         ;
; UberDigiPid:inst|LocalReg[18][15]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainD[15]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[17][15]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainI[15]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[16][15]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainP[15]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[15][15]                                                                                                                                                      ; Merged with UberDigiPid:inst|AdcTarget[15]                                                                                                                                                         ;
; UberDigiPid:inst|LocalReg[18][14]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainD[14]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[17][14]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainI[14]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[16][14]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainP[14]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[15][14]                                                                                                                                                      ; Merged with UberDigiPid:inst|AdcTarget[14]                                                                                                                                                         ;
; UberDigiPid:inst|LocalReg[18][13]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainD[13]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[17][13]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainI[13]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[16][13]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainP[13]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[15][13]                                                                                                                                                      ; Merged with UberDigiPid:inst|AdcTarget[13]                                                                                                                                                         ;
; UberDigiPid:inst|LocalReg[18][12]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainD[12]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[17][12]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainI[12]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[16][12]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainP[12]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[15][12]                                                                                                                                                      ; Merged with UberDigiPid:inst|AdcTarget[12]                                                                                                                                                         ;
; UberDigiPid:inst|LocalReg[18][11]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainD[11]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[17][11]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainI[11]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[16][11]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainP[11]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[15][11]                                                                                                                                                      ; Merged with UberDigiPid:inst|AdcTarget[11]                                                                                                                                                         ;
; UberDigiPid:inst|LocalReg[18][10]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainD[10]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[17][10]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainI[10]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[16][10]                                                                                                                                                      ; Merged with UberDigiPid:inst|GainP[10]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[15][10]                                                                                                                                                      ; Merged with UberDigiPid:inst|AdcTarget[10]                                                                                                                                                         ;
; UberDigiPid:inst|LocalReg[18][9]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[9]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][9]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[9]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][9]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[9]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][9]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[9]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[18][8]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[8]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][8]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[8]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][8]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[8]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][8]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[8]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[18][7]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[7]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][7]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[7]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][7]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[7]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][7]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[7]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[18][6]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[6]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][6]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[6]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][6]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[6]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][6]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[6]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[6][6]                                                                                                                                                        ; Merged with UberDigiPid:inst|FreezeHistory                                                                                                                                                         ;
; UberDigiPid:inst|LocalReg[18][5]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[5]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][5]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[5]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][5]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[5]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][5]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[5]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[18][4]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[4]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][4]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[4]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][4]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[4]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][4]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[4]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[6][4]                                                                                                                                                        ; Merged with UberDigiPid:inst|FreezeFreqCounters                                                                                                                                                    ;
; UberDigiPid:inst|LocalReg[18][3]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[3]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][3]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[3]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][3]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[3]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][3]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[3]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[18][2]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[2]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][2]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[2]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][2]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[2]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][2]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[2]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[18][1]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[1]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][1]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[1]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][1]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[1]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][1]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[1]                                                                                                                                                          ;
; UberDigiPid:inst|LocalReg[18][0]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainD[0]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[17][0]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainI[0]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[16][0]                                                                                                                                                       ; Merged with UberDigiPid:inst|GainP[0]                                                                                                                                                              ;
; UberDigiPid:inst|LocalReg[15][0]                                                                                                                                                       ; Merged with UberDigiPid:inst|AdcTarget[0]                                                                                                                                                          ;
; UberDigiPid:inst|ErrI2[24..31]                                                                                                                                                         ; Merged with UberDigiPid:inst|ErrI2[23]                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[7][10]                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                             ;
; UberDigiPid:inst|LocalReg[7][14]                                                                                                                                                       ; Stuck at VCC due to stuck port data_in                                                                                                                                                             ;
; Total Number of Removed Registers = 154                                                                                                                                                ;                                                                                                                                                                                                    ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|segment_shift_clk_ena                                                      ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_enable_delayed                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[0] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[0] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[1] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[1] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[2] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[2] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[3] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[3] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[4] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[4] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[5] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[5] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[0]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[0]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[1]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[1]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[2]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[2]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[3]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[3]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[4]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[4]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[5]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[5]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[13..15]                       ; Stuck at GND due to stuck port data_in                                                                                                                                                             ;
; Total Number of Removed Registers = 16                                                                                                                                                 ;                                                                                                                                                                                                    ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                ; Reason for Removal        ; Registers Removed due to This Register                                                                                                                        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[15] ; Stuck at GND              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[14], ;
;                                                                                                                                                              ; due to stuck port data_in ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[13]  ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1990  ;
; Number of registers using Synchronous Clear  ; 64    ;
; Number of registers using Synchronous Load   ; 148   ;
; Number of registers using Asynchronous Clear ; 482   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1118  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                                                                                                                                                                               ; Fan out ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[2] ; 2       ;
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[1] ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5]                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0]                                                                                                                                                   ; 1       ;
; Total number of inverted registers = 9                                                                                                                                                                                                                                                                                          ;         ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+-----------------------------------------------------------------------+
; Physical Synthesis Netlist Optimizations                              ;
+--------------------------------------+----------+---------------------+
; Node                                 ; Action   ; Reason              ;
+--------------------------------------+----------+---------------------+
; UberDigiPid:inst|Add3~1              ; Modified ; Timing optimization ;
; UberDigiPid:inst|Add17~1             ; Modified ; Timing optimization ;
; UberDigiPid:inst|Add18~1             ; Modified ; Timing optimization ;
; UberDigiPid:inst|Add18~2             ; Deleted  ; Timing optimization ;
; UberDigiPid:inst|Add18~3             ; Modified ; Timing optimization ;
; UberDigiPid:inst|Add19~1             ; Modified ; Timing optimization ;
; UberDigiPid:inst|Mux153~0            ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferDiff[0]~9       ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[0]~2  ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[1]~6  ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[1]~7  ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[2]~10 ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[3]~14 ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[4]~18 ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[5]~22 ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[6]~26 ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[7]~30 ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[8]~34 ; Modified ; Timing optimization ;
; UberDigiPid:inst|XferOutWrAddr[9]~38 ; Modified ; Timing optimization ;
; UberDigiPid:inst|nRfOutEn~0          ; Deleted  ; Timing optimization ;
; UberDigiPid:inst|nRfOutEn~0_wirecell ; Modified ; Timing optimization ;
+--------------------------------------+----------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                                                                                                                                                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|HistAddrRd[9]                                                                                                                                                                                                                                                                                                                           ;
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|ErrP[20]                                                                                                                                                                                                                                                                                                                                ;
; 9:1                ; 2 bits    ; 12 LEs        ; 0 LEs                ; 12 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|LocalReg[7][14]                                                                                                                                                                                                                                                                                                                         ;
; 5:1                ; 32 bits   ; 96 LEs        ; 64 LEs               ; 32 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|ErrD[18]                                                                                                                                                                                                                                                                                                                                ;
; 8:1                ; 10 bits   ; 50 LEs        ; 0 LEs                ; 50 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|HistAddrWr[4]                                                                                                                                                                                                                                                                                                                           ;
; 6:1                ; 10 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|DacCalc[8]                                                                                                                                                                                                                                                                                                                              ;
; 11:1               ; 32 bits   ; 224 LEs       ; 32 LEs               ; 192 LEs                ; Yes        ; |DigiPid|UberDigiPid:inst|LastErrD[29]                                                                                                                                                                                                                                                                                                                            ;
; 13:1               ; 16 bits   ; 128 LEs       ; 64 LEs               ; 64 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|DacData[5]                                                                                                                                                                                                                                                                                                                              ;
; 13:1               ; 15 bits   ; 120 LEs       ; 15 LEs               ; 105 LEs                ; Yes        ; |DigiPid|UberDigiPid:inst|DacTmpRun[23]                                                                                                                                                                                                                                                                                                                           ;
; 13:1               ; 16 bits   ; 128 LEs       ; 32 LEs               ; 96 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|DacTmpRun[9]                                                                                                                                                                                                                                                                                                                            ;
; 13:1               ; 32 bits   ; 256 LEs       ; 128 LEs              ; 128 LEs                ; Yes        ; |DigiPid|UberDigiPid:inst|ErrI[22]                                                                                                                                                                                                                                                                                                                                ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |DigiPid|UberDigiPid:inst|XferDiff[13]                                                                                                                                                                                                                                                                                                                            ;
; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; Yes        ; |DigiPid|UberDigiPid:inst|XferDiff[2]                                                                                                                                                                                                                                                                                                                             ;
; 6:1                ; 6 bits    ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |DigiPid|UberDigiPid:inst|DacCalc[0]                                                                                                                                                                                                                                                                                                                              ;
; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |DigiPid|UberDigiPid:inst|Selector198                                                                                                                                                                                                                                                                                                                             ;
; 39:1               ; 2 bits    ; 52 LEs        ; 28 LEs               ; 24 LEs                 ; No         ; |DigiPid|UberDigiPid:inst|Selector10                                                                                                                                                                                                                                                                                                                              ;
; 32:1               ; 10 bits   ; 210 LEs       ; 140 LEs              ; 70 LEs                 ; No         ; |DigiPid|UberDigiPid:inst|Selector9                                                                                                                                                                                                                                                                                                                               ;
; 31:1               ; 4 bits    ; 80 LEs        ; 56 LEs               ; 24 LEs                 ; No         ; |DigiPid|UberDigiPid:inst|Selector12                                                                                                                                                                                                                                                                                                                              ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[13]                                                                                                                                                                                                                    ;
; 3:1                ; 13 bits   ; 26 LEs        ; 13 LEs               ; 13 LEs                 ; Yes        ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[1]                                                                                                                                                                                                                     ;
; 3:1                ; 13 bits   ; 26 LEs        ; 13 LEs               ; 13 LEs                 ; Yes        ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[0]                                                                                                                                                                                              ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[24]                                                                                                                                                                                                                          ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[0]                                                                                                                                                                                                        ;
; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[0]                                                                                                                                                                                        ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; Yes        ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[2]                                                                                                                                                                                                             ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |DigiPid|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count                                                                                                                                                                                      ;
; 3:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[0]                             ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|hub_minor_ver_reg[3]                    ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[0] ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[4]              ;
; 34:1               ; 4 bits    ; 88 LEs        ; 56 LEs               ; 32 LEs                 ; Yes        ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|design_hash_reg[1]                      ;
; 20:1               ; 4 bits    ; 52 LEs        ; 32 LEs               ; 20 LEs                 ; Yes        ; |DigiPid|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Source assignments for DP_RAM:HistoryADC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------+
; Assignment                      ; Value              ; From ; To                                        ;
+---------------------------------+--------------------+------+-------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                         ;
+---------------------------------+--------------------+------+-------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Source assignments for DP_RAM:HistoryDAC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------+
; Assignment                      ; Value              ; From ; To                                        ;
+---------------------------------+--------------------+------+-------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                         ;
+---------------------------------+--------------------+------+-------------------------------------------+


+-------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0 ;
+-----------------+-------+------+----------------------+
; Assignment      ; Value ; From ; To                   ;
+-----------------+-------+------+----------------------+
; MESSAGE_DISABLE ; 13410 ; -    ; -                    ;
+-----------------+-------+------+----------------------+


+-------------------------------------------------------------------------------------------------+
; Source assignments for UberDigiPid:inst|altsyncram:XferLut_rtl_0|altsyncram_h2e1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------+
; Assignment                      ; Value              ; From ; To                                ;
+---------------------------------+--------------------+------+-----------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                 ;
+---------------------------------+--------------------+------+-----------------------------------+


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: PLL:inst3|altpll:altpll_component ;
+-------------------------------+-----------------------+------------------------+
; Parameter Name                ; Value                 ; Type                   ;
+-------------------------------+-----------------------+------------------------+
; OPERATION_MODE                ; NORMAL                ; Untyped                ;
; PLL_TYPE                      ; AUTO                  ; Untyped                ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=PLL ; Untyped                ;
; QUALIFY_CONF_DONE             ; OFF                   ; Untyped                ;
; COMPENSATE_CLOCK              ; CLK0                  ; Untyped                ;
; SCAN_CHAIN                    ; LONG                  ; Untyped                ;
; PRIMARY_CLOCK                 ; INCLK0                ; Untyped                ;
; INCLK0_INPUT_FREQUENCY        ; 41666                 ; Signed Integer         ;
; INCLK1_INPUT_FREQUENCY        ; 0                     ; Untyped                ;
; GATE_LOCK_SIGNAL              ; NO                    ; Untyped                ;
; GATE_LOCK_COUNTER             ; 0                     ; Untyped                ;
; LOCK_HIGH                     ; 1                     ; Untyped                ;
; LOCK_LOW                      ; 1                     ; Untyped                ;
; VALID_LOCK_MULTIPLIER         ; 1                     ; Untyped                ;
; INVALID_LOCK_MULTIPLIER       ; 5                     ; Untyped                ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                   ; Untyped                ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                   ; Untyped                ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                   ; Untyped                ;
; SKIP_VCO                      ; OFF                   ; Untyped                ;
; SWITCH_OVER_COUNTER           ; 0                     ; Untyped                ;
; SWITCH_OVER_TYPE              ; AUTO                  ; Untyped                ;
; FEEDBACK_SOURCE               ; EXTCLK0               ; Untyped                ;
; BANDWIDTH                     ; 0                     ; Untyped                ;
; BANDWIDTH_TYPE                ; AUTO                  ; Untyped                ;
; SPREAD_FREQUENCY              ; 0                     ; Untyped                ;
; DOWN_SPREAD                   ; 0                     ; Untyped                ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                   ; Untyped                ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                   ; Untyped                ;
; CLK9_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK8_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK7_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK6_MULTIPLY_BY              ; 0                     ; Untyped                ;
; CLK5_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK4_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK3_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK2_MULTIPLY_BY              ; 1                     ; Untyped                ;
; CLK1_MULTIPLY_BY              ; 5                     ; Signed Integer         ;
; CLK0_MULTIPLY_BY              ; 25                    ; Signed Integer         ;
; CLK9_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK8_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK7_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK6_DIVIDE_BY                ; 0                     ; Untyped                ;
; CLK5_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK4_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK3_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK2_DIVIDE_BY                ; 1                     ; Untyped                ;
; CLK1_DIVIDE_BY                ; 12                    ; Signed Integer         ;
; CLK0_DIVIDE_BY                ; 6                     ; Signed Integer         ;
; CLK9_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK8_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK7_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK6_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK5_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK4_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK3_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK2_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK1_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK0_PHASE_SHIFT              ; 0                     ; Untyped                ;
; CLK5_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK4_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK3_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK2_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK1_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK0_TIME_DELAY               ; 0                     ; Untyped                ;
; CLK9_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK8_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK7_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK6_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK5_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK4_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK3_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK2_DUTY_CYCLE               ; 50                    ; Untyped                ;
; CLK1_DUTY_CYCLE               ; 50                    ; Signed Integer         ;
; CLK0_DUTY_CYCLE               ; 50                    ; Signed Integer         ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                ;
; LOCK_WINDOW_UI                ;  0.05                 ; Untyped                ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                ; Untyped                ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                ; Untyped                ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                ; Untyped                ;
; DPA_MULTIPLY_BY               ; 0                     ; Untyped                ;
; DPA_DIVIDE_BY                 ; 1                     ; Untyped                ;
; DPA_DIVIDER                   ; 0                     ; Untyped                ;
; EXTCLK3_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK2_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK1_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK0_MULTIPLY_BY           ; 1                     ; Untyped                ;
; EXTCLK3_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK2_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK1_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK0_DIVIDE_BY             ; 1                     ; Untyped                ;
; EXTCLK3_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK2_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK1_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK0_PHASE_SHIFT           ; 0                     ; Untyped                ;
; EXTCLK3_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK2_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK1_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK0_TIME_DELAY            ; 0                     ; Untyped                ;
; EXTCLK3_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK2_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK1_DUTY_CYCLE            ; 50                    ; Untyped                ;
; EXTCLK0_DUTY_CYCLE            ; 50                    ; Untyped                ;
; VCO_MULTIPLY_BY               ; 0                     ; Untyped                ;
; VCO_DIVIDE_BY                 ; 0                     ; Untyped                ;
; SCLKOUT0_PHASE_SHIFT          ; 0                     ; Untyped                ;
; SCLKOUT1_PHASE_SHIFT          ; 0                     ; Untyped                ;
; VCO_MIN                       ; 0                     ; Untyped                ;
; VCO_MAX                       ; 0                     ; Untyped                ;
; VCO_CENTER                    ; 0                     ; Untyped                ;
; PFD_MIN                       ; 0                     ; Untyped                ;
; PFD_MAX                       ; 0                     ; Untyped                ;
; M_INITIAL                     ; 0                     ; Untyped                ;
; M                             ; 0                     ; Untyped                ;
; N                             ; 1                     ; Untyped                ;
; M2                            ; 1                     ; Untyped                ;
; N2                            ; 1                     ; Untyped                ;
; SS                            ; 1                     ; Untyped                ;
; C0_HIGH                       ; 0                     ; Untyped                ;
; C1_HIGH                       ; 0                     ; Untyped                ;
; C2_HIGH                       ; 0                     ; Untyped                ;
; C3_HIGH                       ; 0                     ; Untyped                ;
; C4_HIGH                       ; 0                     ; Untyped                ;
; C5_HIGH                       ; 0                     ; Untyped                ;
; C6_HIGH                       ; 0                     ; Untyped                ;
; C7_HIGH                       ; 0                     ; Untyped                ;
; C8_HIGH                       ; 0                     ; Untyped                ;
; C9_HIGH                       ; 0                     ; Untyped                ;
; C0_LOW                        ; 0                     ; Untyped                ;
; C1_LOW                        ; 0                     ; Untyped                ;
; C2_LOW                        ; 0                     ; Untyped                ;
; C3_LOW                        ; 0                     ; Untyped                ;
; C4_LOW                        ; 0                     ; Untyped                ;
; C5_LOW                        ; 0                     ; Untyped                ;
; C6_LOW                        ; 0                     ; Untyped                ;
; C7_LOW                        ; 0                     ; Untyped                ;
; C8_LOW                        ; 0                     ; Untyped                ;
; C9_LOW                        ; 0                     ; Untyped                ;
; C0_INITIAL                    ; 0                     ; Untyped                ;
; C1_INITIAL                    ; 0                     ; Untyped                ;
; C2_INITIAL                    ; 0                     ; Untyped                ;
; C3_INITIAL                    ; 0                     ; Untyped                ;
; C4_INITIAL                    ; 0                     ; Untyped                ;
; C5_INITIAL                    ; 0                     ; Untyped                ;
; C6_INITIAL                    ; 0                     ; Untyped                ;
; C7_INITIAL                    ; 0                     ; Untyped                ;
; C8_INITIAL                    ; 0                     ; Untyped                ;
; C9_INITIAL                    ; 0                     ; Untyped                ;
; C0_MODE                       ; BYPASS                ; Untyped                ;
; C1_MODE                       ; BYPASS                ; Untyped                ;
; C2_MODE                       ; BYPASS                ; Untyped                ;
; C3_MODE                       ; BYPASS                ; Untyped                ;
; C4_MODE                       ; BYPASS                ; Untyped                ;
; C5_MODE                       ; BYPASS                ; Untyped                ;
; C6_MODE                       ; BYPASS                ; Untyped                ;
; C7_MODE                       ; BYPASS                ; Untyped                ;
; C8_MODE                       ; BYPASS                ; Untyped                ;
; C9_MODE                       ; BYPASS                ; Untyped                ;
; C0_PH                         ; 0                     ; Untyped                ;
; C1_PH                         ; 0                     ; Untyped                ;
; C2_PH                         ; 0                     ; Untyped                ;
; C3_PH                         ; 0                     ; Untyped                ;
; C4_PH                         ; 0                     ; Untyped                ;
; C5_PH                         ; 0                     ; Untyped                ;
; C6_PH                         ; 0                     ; Untyped                ;
; C7_PH                         ; 0                     ; Untyped                ;
; C8_PH                         ; 0                     ; Untyped                ;
; C9_PH                         ; 0                     ; Untyped                ;
; L0_HIGH                       ; 1                     ; Untyped                ;
; L1_HIGH                       ; 1                     ; Untyped                ;
; G0_HIGH                       ; 1                     ; Untyped                ;
; G1_HIGH                       ; 1                     ; Untyped                ;
; G2_HIGH                       ; 1                     ; Untyped                ;
; G3_HIGH                       ; 1                     ; Untyped                ;
; E0_HIGH                       ; 1                     ; Untyped                ;
; E1_HIGH                       ; 1                     ; Untyped                ;
; E2_HIGH                       ; 1                     ; Untyped                ;
; E3_HIGH                       ; 1                     ; Untyped                ;
; L0_LOW                        ; 1                     ; Untyped                ;
; L1_LOW                        ; 1                     ; Untyped                ;
; G0_LOW                        ; 1                     ; Untyped                ;
; G1_LOW                        ; 1                     ; Untyped                ;
; G2_LOW                        ; 1                     ; Untyped                ;
; G3_LOW                        ; 1                     ; Untyped                ;
; E0_LOW                        ; 1                     ; Untyped                ;
; E1_LOW                        ; 1                     ; Untyped                ;
; E2_LOW                        ; 1                     ; Untyped                ;
; E3_LOW                        ; 1                     ; Untyped                ;
; L0_INITIAL                    ; 1                     ; Untyped                ;
; L1_INITIAL                    ; 1                     ; Untyped                ;
; G0_INITIAL                    ; 1                     ; Untyped                ;
; G1_INITIAL                    ; 1                     ; Untyped                ;
; G2_INITIAL                    ; 1                     ; Untyped                ;
; G3_INITIAL                    ; 1                     ; Untyped                ;
; E0_INITIAL                    ; 1                     ; Untyped                ;
; E1_INITIAL                    ; 1                     ; Untyped                ;
; E2_INITIAL                    ; 1                     ; Untyped                ;
; E3_INITIAL                    ; 1                     ; Untyped                ;
; L0_MODE                       ; BYPASS                ; Untyped                ;
; L1_MODE                       ; BYPASS                ; Untyped                ;
; G0_MODE                       ; BYPASS                ; Untyped                ;
; G1_MODE                       ; BYPASS                ; Untyped                ;
; G2_MODE                       ; BYPASS                ; Untyped                ;
; G3_MODE                       ; BYPASS                ; Untyped                ;
; E0_MODE                       ; BYPASS                ; Untyped                ;
; E1_MODE                       ; BYPASS                ; Untyped                ;
; E2_MODE                       ; BYPASS                ; Untyped                ;
; E3_MODE                       ; BYPASS                ; Untyped                ;
; L0_PH                         ; 0                     ; Untyped                ;
; L1_PH                         ; 0                     ; Untyped                ;
; G0_PH                         ; 0                     ; Untyped                ;
; G1_PH                         ; 0                     ; Untyped                ;
; G2_PH                         ; 0                     ; Untyped                ;
; G3_PH                         ; 0                     ; Untyped                ;
; E0_PH                         ; 0                     ; Untyped                ;
; E1_PH                         ; 0                     ; Untyped                ;
; E2_PH                         ; 0                     ; Untyped                ;
; E3_PH                         ; 0                     ; Untyped                ;
; M_PH                          ; 0                     ; Untyped                ;
; C1_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C2_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C3_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C4_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C5_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C6_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C7_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C8_USE_CASC_IN                ; OFF                   ; Untyped                ;
; C9_USE_CASC_IN                ; OFF                   ; Untyped                ;
; CLK0_COUNTER                  ; G0                    ; Untyped                ;
; CLK1_COUNTER                  ; G0                    ; Untyped                ;
; CLK2_COUNTER                  ; G0                    ; Untyped                ;
; CLK3_COUNTER                  ; G0                    ; Untyped                ;
; CLK4_COUNTER                  ; G0                    ; Untyped                ;
; CLK5_COUNTER                  ; G0                    ; Untyped                ;
; CLK6_COUNTER                  ; E0                    ; Untyped                ;
; CLK7_COUNTER                  ; E1                    ; Untyped                ;
; CLK8_COUNTER                  ; E2                    ; Untyped                ;
; CLK9_COUNTER                  ; E3                    ; Untyped                ;
; L0_TIME_DELAY                 ; 0                     ; Untyped                ;
; L1_TIME_DELAY                 ; 0                     ; Untyped                ;
; G0_TIME_DELAY                 ; 0                     ; Untyped                ;
; G1_TIME_DELAY                 ; 0                     ; Untyped                ;
; G2_TIME_DELAY                 ; 0                     ; Untyped                ;
; G3_TIME_DELAY                 ; 0                     ; Untyped                ;
; E0_TIME_DELAY                 ; 0                     ; Untyped                ;
; E1_TIME_DELAY                 ; 0                     ; Untyped                ;
; E2_TIME_DELAY                 ; 0                     ; Untyped                ;
; E3_TIME_DELAY                 ; 0                     ; Untyped                ;
; M_TIME_DELAY                  ; 0                     ; Untyped                ;
; N_TIME_DELAY                  ; 0                     ; Untyped                ;
; EXTCLK3_COUNTER               ; E3                    ; Untyped                ;
; EXTCLK2_COUNTER               ; E2                    ; Untyped                ;
; EXTCLK1_COUNTER               ; E1                    ; Untyped                ;
; EXTCLK0_COUNTER               ; E0                    ; Untyped                ;
; ENABLE0_COUNTER               ; L0                    ; Untyped                ;
; ENABLE1_COUNTER               ; L0                    ; Untyped                ;
; CHARGE_PUMP_CURRENT           ; 2                     ; Untyped                ;
; LOOP_FILTER_R                 ;  1.000000             ; Untyped                ;
; LOOP_FILTER_C                 ; 5                     ; Untyped                ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                  ; Untyped                ;
; LOOP_FILTER_R_BITS            ; 9999                  ; Untyped                ;
; LOOP_FILTER_C_BITS            ; 9999                  ; Untyped                ;
; VCO_POST_SCALE                ; 0                     ; Untyped                ;
; CLK2_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; CLK1_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; CLK0_OUTPUT_FREQUENCY         ; 0                     ; Untyped                ;
; INTENDED_DEVICE_FAMILY        ; MAX 10                ; Untyped                ;
; PORT_CLKENA0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA2                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA3                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA4                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKENA5                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_EXTCLK0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK2                  ; PORT_UNUSED           ; Untyped                ;
; PORT_EXTCLK3                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKBAD0                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKBAD1                  ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK0                     ; PORT_USED             ; Untyped                ;
; PORT_CLK1                     ; PORT_USED             ; Untyped                ;
; PORT_CLK2                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK3                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK4                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK5                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK6                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK7                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK8                     ; PORT_UNUSED           ; Untyped                ;
; PORT_CLK9                     ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDATA                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDATAOUT              ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANDONE                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKLOSS                  ; PORT_UNUSED           ; Untyped                ;
; PORT_INCLK1                   ; PORT_UNUSED           ; Untyped                ;
; PORT_INCLK0                   ; PORT_USED             ; Untyped                ;
; PORT_FBIN                     ; PORT_UNUSED           ; Untyped                ;
; PORT_PLLENA                   ; PORT_UNUSED           ; Untyped                ;
; PORT_CLKSWITCH                ; PORT_UNUSED           ; Untyped                ;
; PORT_ARESET                   ; PORT_UNUSED           ; Untyped                ;
; PORT_PFDENA                   ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANCLK                  ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANACLR                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANREAD                 ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANWRITE                ; PORT_UNUSED           ; Untyped                ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_LOCKED                   ; PORT_UNUSED           ; Untyped                ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED           ; Untyped                ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_PHASEDONE                ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASESTEP                ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED           ; Untyped                ;
; PORT_SCANCLKENA               ; PORT_UNUSED           ; Untyped                ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED           ; Untyped                ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY     ; Untyped                ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY     ; Untyped                ;
; M_TEST_SOURCE                 ; 5                     ; Untyped                ;
; C0_TEST_SOURCE                ; 5                     ; Untyped                ;
; C1_TEST_SOURCE                ; 5                     ; Untyped                ;
; C2_TEST_SOURCE                ; 5                     ; Untyped                ;
; C3_TEST_SOURCE                ; 5                     ; Untyped                ;
; C4_TEST_SOURCE                ; 5                     ; Untyped                ;
; C5_TEST_SOURCE                ; 5                     ; Untyped                ;
; C6_TEST_SOURCE                ; 5                     ; Untyped                ;
; C7_TEST_SOURCE                ; 5                     ; Untyped                ;
; C8_TEST_SOURCE                ; 5                     ; Untyped                ;
; C9_TEST_SOURCE                ; 5                     ; Untyped                ;
; CBXI_PARAMETER                ; PLL_altpll            ; Untyped                ;
; VCO_FREQUENCY_CONTROL         ; AUTO                  ; Untyped                ;
; VCO_PHASE_SHIFT_STEP          ; 0                     ; Untyped                ;
; WIDTH_CLOCK                   ; 5                     ; Signed Integer         ;
; WIDTH_PHASECOUNTERSELECT      ; 4                     ; Untyped                ;
; USING_FBMIMICBIDIR_PORT       ; OFF                   ; Untyped                ;
; DEVICE_FAMILY                 ; MAX 10                ; Untyped                ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                ; Untyped                ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                   ; Untyped                ;
; AUTO_CARRY_CHAINS             ; ON                    ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS          ; OFF                   ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS           ; ON                    ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS        ; OFF                   ; IGNORE_CASCADE         ;
+-------------------------------+-----------------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DP_RAM:HistoryADC|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------------+
; Parameter Name                     ; Value                ; Type                               ;
+------------------------------------+----------------------+------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                            ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                     ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                            ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                            ;
; WIDTH_A                            ; 16                   ; Signed Integer                     ;
; WIDTHAD_A                          ; 10                   ; Signed Integer                     ;
; NUMWORDS_A                         ; 1024                 ; Signed Integer                     ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                            ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                            ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                            ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                            ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                            ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                            ;
; WIDTH_B                            ; 16                   ; Signed Integer                     ;
; WIDTHAD_B                          ; 10                   ; Signed Integer                     ;
; NUMWORDS_B                         ; 1024                 ; Signed Integer                     ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                            ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                            ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                            ;
; OUTDATA_REG_B                      ; CLOCK1               ; Untyped                            ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                            ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                            ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                            ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                            ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                            ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                            ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                            ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                     ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                            ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                            ;
; BYTE_SIZE                          ; 8                    ; Untyped                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                            ;
; INIT_FILE                          ; UNUSED               ; Untyped                            ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                            ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                            ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                            ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS               ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS               ; Untyped                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                            ;
; ENABLE_ECC                         ; FALSE                ; Untyped                            ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                            ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                            ;
; DEVICE_FAMILY                      ; MAX 10               ; Untyped                            ;
; CBXI_PARAMETER                     ; altsyncram_82j1      ; Untyped                            ;
+------------------------------------+----------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DP_RAM:HistoryDAC|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------------+
; Parameter Name                     ; Value                ; Type                               ;
+------------------------------------+----------------------+------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                            ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                     ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                            ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                            ;
; WIDTH_A                            ; 16                   ; Signed Integer                     ;
; WIDTHAD_A                          ; 10                   ; Signed Integer                     ;
; NUMWORDS_A                         ; 1024                 ; Signed Integer                     ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                            ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                            ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                            ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                            ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                            ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                            ;
; WIDTH_B                            ; 16                   ; Signed Integer                     ;
; WIDTHAD_B                          ; 10                   ; Signed Integer                     ;
; NUMWORDS_B                         ; 1024                 ; Signed Integer                     ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                            ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                            ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                            ;
; OUTDATA_REG_B                      ; CLOCK1               ; Untyped                            ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                            ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                            ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                            ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                            ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                            ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                            ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                            ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                     ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                            ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                            ;
; BYTE_SIZE                          ; 8                    ; Untyped                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                            ;
; INIT_FILE                          ; UNUSED               ; Untyped                            ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                            ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                            ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                            ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS               ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS               ; Untyped                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                            ;
; ENABLE_ECC                         ; FALSE                ; Untyped                            ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                            ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                            ;
; DEVICE_FAMILY                      ; MAX 10               ; Untyped                            ;
; CBXI_PARAMETER                     ; altsyncram_82j1      ; Untyped                            ;
+------------------------------------+----------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FreqCounter:VCO|lpm_counter:LPM_COUNTER_component ;
+------------------------+-------------+---------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                    ;
+------------------------+-------------+---------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                              ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                            ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                            ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                          ;
; LPM_WIDTH              ; 32          ; Signed Integer                                          ;
; LPM_DIRECTION          ; UP          ; Untyped                                                 ;
; LPM_MODULUS            ; 0           ; Untyped                                                 ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                                 ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                                 ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                 ;
; DEVICE_FAMILY          ; MAX 10      ; Untyped                                                 ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                 ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                      ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                      ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                                 ;
; LABWIDE_SCLR           ; ON          ; Untyped                                                 ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                                 ;
; CBXI_PARAMETER         ; cntr_a8i    ; Untyped                                                 ;
+------------------------+-------------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                         ;
+-------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Parameter Name                                  ; Value                                                                                                                                                                                                                                                                ; Type           ;
+-------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; lpm_type                                        ; sld_signaltap                                                                                                                                                                                                                                                        ; String         ;
; sld_node_info                                   ; 805334528                                                                                                                                                                                                                                                            ; Untyped        ;
; SLD_SECTION_ID                                  ; hdl_signaltap_0                                                                                                                                                                                                                                                      ; String         ;
; SLD_IP_VERSION                                  ; 6                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_IP_MINOR_VERSION                            ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_COMMON_IP_VERSION                           ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; sld_data_bits                                   ; 80                                                                                                                                                                                                                                                                   ; Untyped        ;
; sld_trigger_bits                                ; 80                                                                                                                                                                                                                                                                   ; Untyped        ;
; SLD_NODE_CRC_BITS                               ; 32                                                                                                                                                                                                                                                                   ; Signed Integer ;
; SLD_NODE_CRC_HIWORD                             ; 41394                                                                                                                                                                                                                                                                ; Signed Integer ;
; SLD_NODE_CRC_LOWORD                             ; 50132                                                                                                                                                                                                                                                                ; Signed Integer ;
; sld_incremental_routing                         ; 1                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_sample_depth                                ; 64                                                                                                                                                                                                                                                                   ; Untyped        ;
; sld_segment_size                                ; 64                                                                                                                                                                                                                                                                   ; Untyped        ;
; sld_ram_block_type                              ; AUTO                                                                                                                                                                                                                                                                 ; Untyped        ;
; sld_state_bits                                  ; 11                                                                                                                                                                                                                                                                   ; Untyped        ;
; sld_buffer_full_stop                            ; 1                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_MEM_ADDRESS_BITS                            ; 7                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_DATA_BIT_CNTR_BITS                          ; 4                                                                                                                                                                                                                                                                    ; Signed Integer ;
; sld_trigger_level                               ; 1                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_trigger_in_enabled                          ; 0                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_HPS_TRIGGER_IN_ENABLED                      ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_HPS_TRIGGER_OUT_ENABLED                     ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_HPS_EVENT_ENABLED                           ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_HPS_EVENT_ID                                ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; sld_advanced_trigger_entity                     ; basic,1,                                                                                                                                                                                                                                                             ; Untyped        ;
; sld_trigger_level_pipeline                      ; 1                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_trigger_pipeline                            ; 0                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_ram_pipeline                                ; 0                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_counter_pipeline                            ; 0                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_enable_advanced_trigger                     ; 0                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_ADVANCED_TRIGGER_1                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_2                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_3                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_4                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_5                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_6                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_7                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_8                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_9                          ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; SLD_ADVANCED_TRIGGER_10                         ; NONE                                                                                                                                                                                                                                                                 ; String         ;
; sld_inversion_mask_length                       ; 260                                                                                                                                                                                                                                                                  ; Untyped        ;
; sld_inversion_mask                              ; 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Untyped        ;
; sld_power_up_trigger                            ; 0                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_STATE_FLOW_MGR_ENTITY                       ; state_flow_mgr_entity.vhd                                                                                                                                                                                                                                            ; String         ;
; sld_state_flow_use_generated                    ; 0                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_current_resource_width                      ; 1                                                                                                                                                                                                                                                                    ; Untyped        ;
; sld_attribute_mem_mode                          ; OFF                                                                                                                                                                                                                                                                  ; Untyped        ;
; sld_storage_qualifier_bits                      ; 80                                                                                                                                                                                                                                                                   ; Untyped        ;
; SLD_STORAGE_QUALIFIER_GAP_RECORD                ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_MODE                      ; OFF                                                                                                                                                                                                                                                                  ; String         ;
; SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; sld_storage_qualifier_inversion_mask_length     ; 0                                                                                                                                                                                                                                                                    ; Untyped        ;
; SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY ; basic                                                                                                                                                                                                                                                                ; String         ;
; SLD_STORAGE_QUALIFIER_PIPELINE                  ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_CREATE_MONITOR_INTERFACE                    ; 0                                                                                                                                                                                                                                                                    ; Signed Integer ;
; SLD_USE_JTAG_SIGNAL_ADAPTER                     ; 1                                                                                                                                                                                                                                                                    ; Signed Integer ;
+-------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|altsyncram:XferLut_rtl_0 ;
+------------------------------------+----------------------+--------------------------------+
; Parameter Name                     ; Value                ; Type                           ;
+------------------------------------+----------------------+--------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                        ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                     ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                   ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                 ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                        ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                        ;
; WIDTH_A                            ; 16                   ; Untyped                        ;
; WIDTHAD_A                          ; 10                   ; Untyped                        ;
; NUMWORDS_A                         ; 1024                 ; Untyped                        ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                        ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                        ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                        ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                        ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                        ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                        ;
; WIDTH_B                            ; 16                   ; Untyped                        ;
; WIDTHAD_B                          ; 10                   ; Untyped                        ;
; NUMWORDS_B                         ; 1024                 ; Untyped                        ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                        ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                        ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                        ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                        ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                        ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                        ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                        ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                        ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                        ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                        ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                        ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                        ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                        ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                        ;
; BYTE_SIZE                          ; 8                    ; Untyped                        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                        ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                        ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                        ;
; INIT_FILE                          ; UNUSED               ; Untyped                        ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                        ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                        ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                        ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                        ;
; ENABLE_ECC                         ; FALSE                ; Untyped                        ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                        ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                        ;
; DEVICE_FAMILY                      ; MAX 10               ; Untyped                        ;
; CBXI_PARAMETER                     ; altsyncram_h2e1      ; Untyped                        ;
+------------------------------------+----------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|lpm_mult:Mult3 ;
+------------------------------------------------+----------+----------------------+
; Parameter Name                                 ; Value    ; Type                 ;
+------------------------------------------------+----------+----------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY           ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY         ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE         ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE       ;
; LPM_WIDTHA                                     ; 16       ; Untyped              ;
; LPM_WIDTHB                                     ; 6        ; Untyped              ;
; LPM_WIDTHP                                     ; 22       ; Untyped              ;
; LPM_WIDTHR                                     ; 22       ; Untyped              ;
; LPM_WIDTHS                                     ; 1        ; Untyped              ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped              ;
; LPM_PIPELINE                                   ; 0        ; Untyped              ;
; LATENCY                                        ; 0        ; Untyped              ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped              ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped              ;
; USE_EAB                                        ; OFF      ; Untyped              ;
; MAXIMIZE_SPEED                                 ; 6        ; Untyped              ;
; DEVICE_FAMILY                                  ; MAX 10   ; Untyped              ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped              ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT      ; TECH_MAPPER_APEX20K  ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped              ;
; CBXI_PARAMETER                                 ; mult_bms ; Untyped              ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped              ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped              ;
; USE_AHDL_IMPLEMENTATION                        ; OFF      ; Untyped              ;
+------------------------------------------------+----------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|lpm_mult:Mult2 ;
+------------------------------------------------+----------+----------------------+
; Parameter Name                                 ; Value    ; Type                 ;
+------------------------------------------------+----------+----------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY           ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY         ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE         ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE       ;
; LPM_WIDTHA                                     ; 18       ; Untyped              ;
; LPM_WIDTHB                                     ; 17       ; Untyped              ;
; LPM_WIDTHP                                     ; 35       ; Untyped              ;
; LPM_WIDTHR                                     ; 35       ; Untyped              ;
; LPM_WIDTHS                                     ; 1        ; Untyped              ;
; LPM_REPRESENTATION                             ; SIGNED   ; Untyped              ;
; LPM_PIPELINE                                   ; 0        ; Untyped              ;
; LATENCY                                        ; 0        ; Untyped              ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped              ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped              ;
; USE_EAB                                        ; OFF      ; Untyped              ;
; MAXIMIZE_SPEED                                 ; 6        ; Untyped              ;
; DEVICE_FAMILY                                  ; MAX 10   ; Untyped              ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped              ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT      ; TECH_MAPPER_APEX20K  ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped              ;
; CBXI_PARAMETER                                 ; mult_1hs ; Untyped              ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped              ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped              ;
; USE_AHDL_IMPLEMENTATION                        ; OFF      ; Untyped              ;
+------------------------------------------------+----------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|lpm_mult:Mult0 ;
+------------------------------------------------+----------+----------------------+
; Parameter Name                                 ; Value    ; Type                 ;
+------------------------------------------------+----------+----------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY           ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY         ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE         ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE       ;
; LPM_WIDTHA                                     ; 18       ; Untyped              ;
; LPM_WIDTHB                                     ; 17       ; Untyped              ;
; LPM_WIDTHP                                     ; 35       ; Untyped              ;
; LPM_WIDTHR                                     ; 35       ; Untyped              ;
; LPM_WIDTHS                                     ; 1        ; Untyped              ;
; LPM_REPRESENTATION                             ; SIGNED   ; Untyped              ;
; LPM_PIPELINE                                   ; 0        ; Untyped              ;
; LATENCY                                        ; 0        ; Untyped              ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped              ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped              ;
; USE_EAB                                        ; OFF      ; Untyped              ;
; MAXIMIZE_SPEED                                 ; 6        ; Untyped              ;
; DEVICE_FAMILY                                  ; MAX 10   ; Untyped              ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped              ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT      ; TECH_MAPPER_APEX20K  ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped              ;
; CBXI_PARAMETER                                 ; mult_1hs ; Untyped              ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped              ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped              ;
; USE_AHDL_IMPLEMENTATION                        ; OFF      ; Untyped              ;
+------------------------------------------------+----------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: UberDigiPid:inst|lpm_mult:Mult1 ;
+------------------------------------------------+----------+----------------------+
; Parameter Name                                 ; Value    ; Type                 ;
+------------------------------------------------+----------+----------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY           ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY         ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE         ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE       ;
; LPM_WIDTHA                                     ; 18       ; Untyped              ;
; LPM_WIDTHB                                     ; 17       ; Untyped              ;
; LPM_WIDTHP                                     ; 35       ; Untyped              ;
; LPM_WIDTHR                                     ; 35       ; Untyped              ;
; LPM_WIDTHS                                     ; 1        ; Untyped              ;
; LPM_REPRESENTATION                             ; SIGNED   ; Untyped              ;
; LPM_PIPELINE                                   ; 0        ; Untyped              ;
; LATENCY                                        ; 0        ; Untyped              ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped              ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped              ;
; USE_EAB                                        ; OFF      ; Untyped              ;
; MAXIMIZE_SPEED                                 ; 6        ; Untyped              ;
; DEVICE_FAMILY                                  ; MAX 10   ; Untyped              ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped              ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT      ; TECH_MAPPER_APEX20K  ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped              ;
; CBXI_PARAMETER                                 ; mult_1hs ; Untyped              ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped              ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped              ;
; USE_AHDL_IMPLEMENTATION                        ; OFF      ; Untyped              ;
+------------------------------------------------+----------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                      ;
+-------------------------------+-----------------------------------+
; Name                          ; Value                             ;
+-------------------------------+-----------------------------------+
; Number of entity instances    ; 1                                 ;
; Entity Instance               ; PLL:inst3|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                            ;
;     -- PLL_TYPE               ; AUTO                              ;
;     -- PRIMARY_CLOCK          ; INCLK0                            ;
;     -- INCLK0_INPUT_FREQUENCY ; 41666                             ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                 ;
;     -- VCO_MULTIPLY_BY        ; 0                                 ;
;     -- VCO_DIVIDE_BY          ; 0                                 ;
+-------------------------------+-----------------------------------+


+-----------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                              ;
+-------------------------------------------+---------------------------------------------------+
; Name                                      ; Value                                             ;
+-------------------------------------------+---------------------------------------------------+
; Number of entity instances                ; 3                                                 ;
; Entity Instance                           ; DP_RAM:HistoryADC|altsyncram:altsyncram_component ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                         ;
;     -- WIDTH_A                            ; 16                                                ;
;     -- NUMWORDS_A                         ; 1024                                              ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                      ;
;     -- WIDTH_B                            ; 16                                                ;
;     -- NUMWORDS_B                         ; 1024                                              ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                            ;
;     -- OUTDATA_REG_B                      ; CLOCK1                                            ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                              ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                         ;
; Entity Instance                           ; DP_RAM:HistoryDAC|altsyncram:altsyncram_component ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                         ;
;     -- WIDTH_A                            ; 16                                                ;
;     -- NUMWORDS_A                         ; 1024                                              ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                      ;
;     -- WIDTH_B                            ; 16                                                ;
;     -- NUMWORDS_B                         ; 1024                                              ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                            ;
;     -- OUTDATA_REG_B                      ; CLOCK1                                            ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                              ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                         ;
; Entity Instance                           ; UberDigiPid:inst|altsyncram:XferLut_rtl_0         ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                         ;
;     -- WIDTH_A                            ; 16                                                ;
;     -- NUMWORDS_A                         ; 1024                                              ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                      ;
;     -- WIDTH_B                            ; 16                                                ;
;     -- NUMWORDS_B                         ; 1024                                              ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                            ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                      ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                              ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                         ;
+-------------------------------------------+---------------------------------------------------+


+-------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                          ;
+---------------------------------------+---------------------------------+
; Name                                  ; Value                           ;
+---------------------------------------+---------------------------------+
; Number of entity instances            ; 4                               ;
; Entity Instance                       ; UberDigiPid:inst|lpm_mult:Mult3 ;
;     -- LPM_WIDTHA                     ; 16                              ;
;     -- LPM_WIDTHB                     ; 6                               ;
;     -- LPM_WIDTHP                     ; 22                              ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                        ;
;     -- INPUT_A_IS_CONSTANT            ; NO                              ;
;     -- INPUT_B_IS_CONSTANT            ; NO                              ;
;     -- USE_EAB                        ; OFF                             ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                            ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                              ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                              ;
; Entity Instance                       ; UberDigiPid:inst|lpm_mult:Mult2 ;
;     -- LPM_WIDTHA                     ; 18                              ;
;     -- LPM_WIDTHB                     ; 17                              ;
;     -- LPM_WIDTHP                     ; 35                              ;
;     -- LPM_REPRESENTATION             ; SIGNED                          ;
;     -- INPUT_A_IS_CONSTANT            ; NO                              ;
;     -- INPUT_B_IS_CONSTANT            ; NO                              ;
;     -- USE_EAB                        ; OFF                             ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                            ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                              ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                              ;
; Entity Instance                       ; UberDigiPid:inst|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 18                              ;
;     -- LPM_WIDTHB                     ; 17                              ;
;     -- LPM_WIDTHP                     ; 35                              ;
;     -- LPM_REPRESENTATION             ; SIGNED                          ;
;     -- INPUT_A_IS_CONSTANT            ; NO                              ;
;     -- INPUT_B_IS_CONSTANT            ; NO                              ;
;     -- USE_EAB                        ; OFF                             ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                            ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                              ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                              ;
; Entity Instance                       ; UberDigiPid:inst|lpm_mult:Mult1 ;
;     -- LPM_WIDTHA                     ; 18                              ;
;     -- LPM_WIDTHB                     ; 17                              ;
;     -- LPM_WIDTHP                     ; 35                              ;
;     -- LPM_REPRESENTATION             ; SIGNED                          ;
;     -- INPUT_A_IS_CONSTANT            ; NO                              ;
;     -- INPUT_B_IS_CONSTANT            ; NO                              ;
;     -- USE_EAB                        ; OFF                             ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                            ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                              ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                              ;
+---------------------------------------+---------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Tap Logic Analyzer Settings                                                                                                                                                                                                                                      ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Segments ; Storage Qualifier Type ; Trigger Flow Control ; Trigger Conditions ; Advanced Trigger Conditions ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; 0              ; auto_signaltap_0 ; 80                  ; 80               ; 64           ; 1        ; continuous             ; sequential           ; 1                  ; 0                           ; no              ; no               ; no                       ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 67                          ;
; cycloneiii_ff         ; 684                         ;
;     ENA               ; 497                         ;
;     ENA CLR           ; 42                          ;
;     ENA SLD           ; 84                          ;
;     SCLR              ; 16                          ;
;     plain             ; 45                          ;
; cycloneiii_io_obuf    ; 16                          ;
; cycloneiii_lcell_comb ; 1410                        ;
;     arith             ; 514                         ;
;         1 data inputs ; 1                           ;
;         2 data inputs ; 233                         ;
;         3 data inputs ; 280                         ;
;     normal            ; 896                         ;
;         0 data inputs ; 2                           ;
;         1 data inputs ; 13                          ;
;         2 data inputs ; 110                         ;
;         3 data inputs ; 221                         ;
;         4 data inputs ; 550                         ;
; cycloneiii_mac_mult   ; 4                           ;
; cycloneiii_mac_out    ; 4                           ;
; cycloneiii_pll        ; 1                           ;
; cycloneiii_ram_block  ; 48                          ;
;                       ;                             ;
; Max LUT depth         ; 12.00                       ;
; Average LUT depth     ; 4.71                        ;
+-----------------------+-----------------------------+


+--------------------------------------------------------------------------------+
; Post-Synthesis Netlist Statistics for Partition sld_signaltap:auto_signaltap_0 ;
+-----------------------+--------------------------------------------------------+
; Type                  ; Count                                                  ;
+-----------------------+--------------------------------------------------------+
; boundary_port         ; 484                                                    ;
; cycloneiii_ff         ; 1215                                                   ;
;     CLR               ; 110                                                    ;
;     ENA               ; 96                                                     ;
;     ENA CLR           ; 292                                                    ;
;     ENA SCLR SLD      ; 36                                                     ;
;     ENA SLD           ; 7                                                      ;
;     SLD               ; 11                                                     ;
;     plain             ; 663                                                    ;
; cycloneiii_lcell_comb ; 544                                                    ;
;     arith             ; 59                                                     ;
;         2 data inputs ; 58                                                     ;
;         3 data inputs ; 1                                                      ;
;     normal            ; 485                                                    ;
;         0 data inputs ; 6                                                      ;
;         1 data inputs ; 4                                                      ;
;         2 data inputs ; 22                                                     ;
;         3 data inputs ; 156                                                    ;
;         4 data inputs ; 297                                                    ;
; cycloneiii_ram_block  ; 80                                                     ;
;                       ;                                                        ;
; Max LUT depth         ; 4.10                                                   ;
; Average LUT depth     ; 1.60                                                   ;
+-----------------------+--------------------------------------------------------+


+------------------------------------------------------------------+
; Post-Synthesis Netlist Statistics for Partition sld_hub:auto_hub ;
+-----------------------+------------------------------------------+
; Type                  ; Count                                    ;
+-----------------------+------------------------------------------+
; boundary_port         ; 107                                      ;
; cycloneiii_ff         ; 91                                       ;
;     CLR               ; 4                                        ;
;     ENA               ; 16                                       ;
;     ENA CLR           ; 33                                       ;
;     ENA CLR SLD       ; 1                                        ;
;     ENA SCLR          ; 5                                        ;
;     ENA SLD           ; 9                                        ;
;     SCLR              ; 7                                        ;
;     plain             ; 16                                       ;
; cycloneiii_lcell_comb ; 127                                      ;
;     arith             ; 8                                        ;
;         2 data inputs ; 8                                        ;
;     normal            ; 119                                      ;
;         0 data inputs ; 1                                        ;
;         1 data inputs ; 6                                        ;
;         2 data inputs ; 20                                       ;
;         3 data inputs ; 40                                       ;
;         4 data inputs ; 52                                       ;
;                       ;                                          ;
; Max LUT depth         ; 4.00                                     ;
; Average LUT depth     ; 1.81                                     ;
+-----------------------+------------------------------------------+


+-----------------------------------------------+
; Elapsed Time Per Partition                    ;
+--------------------------------+--------------+
; Partition Name                 ; Elapsed Time ;
+--------------------------------+--------------+
; sld_signaltap:auto_signaltap_0 ; 00:00:03     ;
; Top                            ; 00:00:14     ;
; sld_hub:auto_hub               ; 00:00:01     ;
+--------------------------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Connections to In-System Debugging Instance "auto_signaltap_0"                                                                                                  ;
+--------------------------------+---------------+-----------+--------------------------------+-------------------+-------------------------------------+---------+
; Name                           ; Type          ; Status    ; Partition Name                 ; Netlist Type Used ; Actual Connection                   ; Details ;
+--------------------------------+---------------+-----------+--------------------------------+-------------------+-------------------------------------+---------+
; TP2                            ; pre-synthesis ; connected ; Top                            ; post-synthesis    ; TtlIn                               ; N/A     ;
; UberDigiPid:inst|Adc[0]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[0]             ; N/A     ;
; UberDigiPid:inst|Adc[0]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[0]             ; N/A     ;
; UberDigiPid:inst|Adc[10]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[10]            ; N/A     ;
; UberDigiPid:inst|Adc[10]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[10]            ; N/A     ;
; UberDigiPid:inst|Adc[11]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[11]            ; N/A     ;
; UberDigiPid:inst|Adc[11]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[11]            ; N/A     ;
; UberDigiPid:inst|Adc[12]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[12]            ; N/A     ;
; UberDigiPid:inst|Adc[12]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[12]            ; N/A     ;
; UberDigiPid:inst|Adc[13]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[13]            ; N/A     ;
; UberDigiPid:inst|Adc[13]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[13]            ; N/A     ;
; UberDigiPid:inst|Adc[14]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[14]            ; N/A     ;
; UberDigiPid:inst|Adc[14]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[14]            ; N/A     ;
; UberDigiPid:inst|Adc[15]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[15]            ; N/A     ;
; UberDigiPid:inst|Adc[15]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[15]            ; N/A     ;
; UberDigiPid:inst|Adc[1]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[1]             ; N/A     ;
; UberDigiPid:inst|Adc[1]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[1]             ; N/A     ;
; UberDigiPid:inst|Adc[2]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[2]             ; N/A     ;
; UberDigiPid:inst|Adc[2]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[2]             ; N/A     ;
; UberDigiPid:inst|Adc[3]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[3]             ; N/A     ;
; UberDigiPid:inst|Adc[3]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[3]             ; N/A     ;
; UberDigiPid:inst|Adc[4]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[4]             ; N/A     ;
; UberDigiPid:inst|Adc[4]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[4]             ; N/A     ;
; UberDigiPid:inst|Adc[5]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[5]             ; N/A     ;
; UberDigiPid:inst|Adc[5]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[5]             ; N/A     ;
; UberDigiPid:inst|Adc[6]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[6]             ; N/A     ;
; UberDigiPid:inst|Adc[6]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[6]             ; N/A     ;
; UberDigiPid:inst|Adc[7]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[7]             ; N/A     ;
; UberDigiPid:inst|Adc[7]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[7]             ; N/A     ;
; UberDigiPid:inst|Adc[8]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[8]             ; N/A     ;
; UberDigiPid:inst|Adc[8]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[8]             ; N/A     ;
; UberDigiPid:inst|Adc[9]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[9]             ; N/A     ;
; UberDigiPid:inst|Adc[9]        ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|Adc[9]             ; N/A     ;
; UberDigiPid:inst|DacTmpRun[0]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[0]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[0]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[0]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[10] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[10]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[10] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[10]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[11] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[11]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[11] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[11]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[12] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[12]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[12] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[12]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[13] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[13]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[13] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[13]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[14] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[14]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[14] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[14]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[15] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[15]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[15] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[15]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[16] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[16]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[16] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[16]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[17] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[17]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[17] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[17]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[18] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[18]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[18] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[18]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[19] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[19]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[19] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[19]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[1]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[1]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[1]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[1]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[20] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[20]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[20] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[20]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[21] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[21]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[21] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[21]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[22] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[22]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[22] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[22]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[23] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[23]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[23] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[23]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[24] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[24]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[24] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[24]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[25] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[25]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[25] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[25]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[26] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[26]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[26] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[26]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[27] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[27]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[27] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[27]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[28] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[28]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[28] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[28]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[29] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[29]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[29] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[29]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[2]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[2]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[2]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[2]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[30] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[30]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[30] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[30]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[31] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[31]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[31] ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[31]      ; N/A     ;
; UberDigiPid:inst|DacTmpRun[3]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[3]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[3]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[3]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[4]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[4]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[4]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[4]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[5]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[5]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[5]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[5]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[6]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[6]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[6]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[6]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[7]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[7]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[7]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[7]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[8]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[8]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[8]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[8]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[9]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[9]       ; N/A     ;
; UberDigiPid:inst|DacTmpRun[9]  ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|DacTmpRun[9]       ; N/A     ;
; UberDigiPid:inst|ErrP[0]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[0]            ; N/A     ;
; UberDigiPid:inst|ErrP[0]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[0]            ; N/A     ;
; UberDigiPid:inst|ErrP[10]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[10]           ; N/A     ;
; UberDigiPid:inst|ErrP[10]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[10]           ; N/A     ;
; UberDigiPid:inst|ErrP[11]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[11]           ; N/A     ;
; UberDigiPid:inst|ErrP[11]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[11]           ; N/A     ;
; UberDigiPid:inst|ErrP[12]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[12]           ; N/A     ;
; UberDigiPid:inst|ErrP[12]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[12]           ; N/A     ;
; UberDigiPid:inst|ErrP[13]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[13]           ; N/A     ;
; UberDigiPid:inst|ErrP[13]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[13]           ; N/A     ;
; UberDigiPid:inst|ErrP[14]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[14]           ; N/A     ;
; UberDigiPid:inst|ErrP[14]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[14]           ; N/A     ;
; UberDigiPid:inst|ErrP[15]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[15]           ; N/A     ;
; UberDigiPid:inst|ErrP[15]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[15]           ; N/A     ;
; UberDigiPid:inst|ErrP[16]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[16]           ; N/A     ;
; UberDigiPid:inst|ErrP[16]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[16]           ; N/A     ;
; UberDigiPid:inst|ErrP[17]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[17]           ; N/A     ;
; UberDigiPid:inst|ErrP[17]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[17]           ; N/A     ;
; UberDigiPid:inst|ErrP[18]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[18]           ; N/A     ;
; UberDigiPid:inst|ErrP[18]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[18]           ; N/A     ;
; UberDigiPid:inst|ErrP[19]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[19]           ; N/A     ;
; UberDigiPid:inst|ErrP[19]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[19]           ; N/A     ;
; UberDigiPid:inst|ErrP[1]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[1]            ; N/A     ;
; UberDigiPid:inst|ErrP[1]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[1]            ; N/A     ;
; UberDigiPid:inst|ErrP[20]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[20]           ; N/A     ;
; UberDigiPid:inst|ErrP[20]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[20]           ; N/A     ;
; UberDigiPid:inst|ErrP[21]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[21]           ; N/A     ;
; UberDigiPid:inst|ErrP[21]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[21]           ; N/A     ;
; UberDigiPid:inst|ErrP[22]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[22]           ; N/A     ;
; UberDigiPid:inst|ErrP[22]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[22]           ; N/A     ;
; UberDigiPid:inst|ErrP[23]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[23]           ; N/A     ;
; UberDigiPid:inst|ErrP[23]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[23]           ; N/A     ;
; UberDigiPid:inst|ErrP[24]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[24]           ; N/A     ;
; UberDigiPid:inst|ErrP[24]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[24]           ; N/A     ;
; UberDigiPid:inst|ErrP[25]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[25]           ; N/A     ;
; UberDigiPid:inst|ErrP[25]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[25]           ; N/A     ;
; UberDigiPid:inst|ErrP[26]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[26]           ; N/A     ;
; UberDigiPid:inst|ErrP[26]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[26]           ; N/A     ;
; UberDigiPid:inst|ErrP[27]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[27]           ; N/A     ;
; UberDigiPid:inst|ErrP[27]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[27]           ; N/A     ;
; UberDigiPid:inst|ErrP[28]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[28]           ; N/A     ;
; UberDigiPid:inst|ErrP[28]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[28]           ; N/A     ;
; UberDigiPid:inst|ErrP[29]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[29]           ; N/A     ;
; UberDigiPid:inst|ErrP[29]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[29]           ; N/A     ;
; UberDigiPid:inst|ErrP[2]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[2]            ; N/A     ;
; UberDigiPid:inst|ErrP[2]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[2]            ; N/A     ;
; UberDigiPid:inst|ErrP[30]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[30]           ; N/A     ;
; UberDigiPid:inst|ErrP[30]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[30]           ; N/A     ;
; UberDigiPid:inst|ErrP[31]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[31]           ; N/A     ;
; UberDigiPid:inst|ErrP[31]      ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[31]           ; N/A     ;
; UberDigiPid:inst|ErrP[3]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[3]            ; N/A     ;
; UberDigiPid:inst|ErrP[3]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[3]            ; N/A     ;
; UberDigiPid:inst|ErrP[4]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[4]            ; N/A     ;
; UberDigiPid:inst|ErrP[4]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[4]            ; N/A     ;
; UberDigiPid:inst|ErrP[5]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[5]            ; N/A     ;
; UberDigiPid:inst|ErrP[5]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[5]            ; N/A     ;
; UberDigiPid:inst|ErrP[6]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[6]            ; N/A     ;
; UberDigiPid:inst|ErrP[6]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[6]            ; N/A     ;
; UberDigiPid:inst|ErrP[7]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[7]            ; N/A     ;
; UberDigiPid:inst|ErrP[7]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[7]            ; N/A     ;
; UberDigiPid:inst|ErrP[8]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[8]            ; N/A     ;
; UberDigiPid:inst|ErrP[8]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[8]            ; N/A     ;
; UberDigiPid:inst|ErrP[9]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[9]            ; N/A     ;
; UberDigiPid:inst|ErrP[9]       ; post-fitting  ; connected ; Top                            ; post-synthesis    ; UberDigiPid:inst|ErrP[9]            ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|gnd           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~GND ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
; auto_signaltap_0|vcc           ; post-fitting  ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis    ; sld_signaltap:auto_signaltap_0|~VCC ; N/A     ;
+--------------------------------+---------------+-----------+--------------------------------+-------------------+-------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition
    Info: Processing started: Tue Jan 23 16:48:50 2018
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DigiPid -c DigiPid
Info (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file digipid.bdf
    Info (12023): Found entity 1: DigiPid
Info (12021): Found 1 design units, including 1 entities, in source file digipid.sv
    Info (12023): Found entity 1: UberDigiPid File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 31
Info (12021): Found 1 design units, including 1 entities, in source file pll.v
    Info (12023): Found entity 1: PLL File: D:/Projects/2016_DigiPid/Altera/PLL.v Line: 39
Info (12021): Found 1 design units, including 1 entities, in source file dp_ram.v
    Info (12023): Found entity 1: DP_RAM File: D:/Projects/2016_DigiPid/Altera/DP_RAM.v Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file freqcounter.v
    Info (12023): Found entity 1: FreqCounter File: D:/Projects/2016_DigiPid/Altera/FreqCounter.v Line: 40
Info (12127): Elaborating entity "DigiPid" for the top level hierarchy
Info (12128): Elaborating entity "UberDigiPid" for hierarchy "UberDigiPid:inst"
Warning (10230): Verilog HDL assignment warning at DigiPid.sv(132): truncated value with size 32 to match size of target (16) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 132
Warning (10240): Verilog HDL Always Construct warning at DigiPid.sv(115): inferring latch(es) for variable "Data4Mcu", which holds its previous value in one or more paths through the always construct File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Warning (10240): Verilog HDL Always Construct warning at DigiPid.sv(115): inferring latch(es) for variable "StatusRead", which holds its previous value in one or more paths through the always construct File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Warning (10762): Verilog HDL Case Statement warning at DigiPid.sv(443): can't check case statement for completeness because the case expression has too many possible states File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 443
Warning (10030): Net "LocalReg[31..19]" at DigiPid.sv(66) has no driver or initial value, using a default initial value '0' File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 66
Warning (10030): Net "LocalReg[13]" at DigiPid.sv(66) has no driver or initial value, using a default initial value '0' File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 66
Warning (10030): Net "LocalReg[9]" at DigiPid.sv(66) has no driver or initial value, using a default initial value '0' File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 66
Warning (10030): Net "LocalReg[5..4]" at DigiPid.sv(66) has no driver or initial value, using a default initial value '0' File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 66
Info (10041): Inferred latch for "StatusRead" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[0]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[1]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[2]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[3]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[4]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[5]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[6]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[7]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[8]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[9]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[10]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[11]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[12]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[13]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[14]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (10041): Inferred latch for "Data4Mcu[15]" at DigiPid.sv(115) File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 115
Info (12128): Elaborating entity "altpll" for hierarchy "PLL:inst3|altpll:altpll_component" File: D:/Projects/2016_DigiPid/Altera/PLL.v Line: 94
Info (12130): Elaborated megafunction instantiation "PLL:inst3|altpll:altpll_component" File: D:/Projects/2016_DigiPid/Altera/PLL.v Line: 94
Info (12133): Instantiated megafunction "PLL:inst3|altpll:altpll_component" with the following parameter: File: D:/Projects/2016_DigiPid/Altera/PLL.v Line: 94
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "6"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "25"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "12"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "5"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "41666"
    Info (12134): Parameter "intended_device_family" = "MAX 10"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=PLL"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pll_altpll.v
    Info (12023): Found entity 1: PLL_altpll File: D:/Projects/2016_DigiPid/Altera/db/pll_altpll.v Line: 29
Info (12128): Elaborating entity "PLL_altpll" for hierarchy "PLL:inst3|altpll:altpll_component|PLL_altpll:auto_generated" File: c:/intel/17.1/quartus/libraries/megafunctions/altpll.tdf Line: 897
Info (12128): Elaborating entity "DP_RAM" for hierarchy "DP_RAM:HistoryADC"
Info (12128): Elaborating entity "altsyncram" for hierarchy "DP_RAM:HistoryADC|altsyncram:altsyncram_component" File: D:/Projects/2016_DigiPid/Altera/DP_RAM.v Line: 91
Info (12130): Elaborated megafunction instantiation "DP_RAM:HistoryADC|altsyncram:altsyncram_component" File: D:/Projects/2016_DigiPid/Altera/DP_RAM.v Line: 91
Info (12133): Instantiated megafunction "DP_RAM:HistoryADC|altsyncram:altsyncram_component" with the following parameter: File: D:/Projects/2016_DigiPid/Altera/DP_RAM.v Line: 91
    Info (12134): Parameter "address_aclr_b" = "NONE"
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
    Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
    Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
    Info (12134): Parameter "intended_device_family" = "MAX 10"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "1024"
    Info (12134): Parameter "numwords_b" = "1024"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_b" = "CLOCK1"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "widthad_a" = "10"
    Info (12134): Parameter "widthad_b" = "10"
    Info (12134): Parameter "width_a" = "16"
    Info (12134): Parameter "width_b" = "16"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_82j1.tdf
    Info (12023): Found entity 1: altsyncram_82j1 File: D:/Projects/2016_DigiPid/Altera/db/altsyncram_82j1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_82j1" for hierarchy "DP_RAM:HistoryADC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated" File: c:/intel/17.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "FreqCounter" for hierarchy "FreqCounter:VCO"
Info (12128): Elaborating entity "lpm_counter" for hierarchy "FreqCounter:VCO|lpm_counter:LPM_COUNTER_component" File: D:/Projects/2016_DigiPid/Altera/FreqCounter.v Line: 69
Info (12130): Elaborated megafunction instantiation "FreqCounter:VCO|lpm_counter:LPM_COUNTER_component" File: D:/Projects/2016_DigiPid/Altera/FreqCounter.v Line: 69
Info (12133): Instantiated megafunction "FreqCounter:VCO|lpm_counter:LPM_COUNTER_component" with the following parameter: File: D:/Projects/2016_DigiPid/Altera/FreqCounter.v Line: 69
    Info (12134): Parameter "lpm_direction" = "UP"
    Info (12134): Parameter "lpm_port_updown" = "PORT_UNUSED"
    Info (12134): Parameter "lpm_type" = "LPM_COUNTER"
    Info (12134): Parameter "lpm_width" = "32"
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_a8i.tdf
    Info (12023): Found entity 1: cntr_a8i File: D:/Projects/2016_DigiPid/Altera/db/cntr_a8i.tdf Line: 25
Info (12128): Elaborating entity "cntr_a8i" for hierarchy "FreqCounter:VCO|lpm_counter:LPM_COUNTER_component|cntr_a8i:auto_generated" File: c:/intel/17.1/quartus/libraries/megafunctions/lpm_counter.tdf Line: 258
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_oc14.tdf
    Info (12023): Found entity 1: altsyncram_oc14 File: D:/Projects/2016_DigiPid/Altera/db/altsyncram_oc14.tdf Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_g7c.tdf
    Info (12023): Found entity 1: mux_g7c File: D:/Projects/2016_DigiPid/Altera/db/mux_g7c.tdf Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_3af.tdf
    Info (12023): Found entity 1: decode_3af File: D:/Projects/2016_DigiPid/Altera/db/decode_3af.tdf Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_9rh.tdf
    Info (12023): Found entity 1: cntr_9rh File: D:/Projects/2016_DigiPid/Altera/db/cntr_9rh.tdf Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_jrb.tdf
    Info (12023): Found entity 1: cmpr_jrb File: D:/Projects/2016_DigiPid/Altera/db/cmpr_jrb.tdf Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_mfi.tdf
    Info (12023): Found entity 1: cntr_mfi File: D:/Projects/2016_DigiPid/Altera/db/cntr_mfi.tdf Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_2rh.tdf
    Info (12023): Found entity 1: cntr_2rh File: D:/Projects/2016_DigiPid/Altera/db/cntr_2rh.tdf Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_grb.tdf
    Info (12023): Found entity 1: cmpr_grb File: D:/Projects/2016_DigiPid/Altera/db/cmpr_grb.tdf Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_odi.tdf
    Info (12023): Found entity 1: cntr_odi File: D:/Projects/2016_DigiPid/Altera/db/cntr_odi.tdf Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_drb.tdf
    Info (12023): Found entity 1: cmpr_drb File: D:/Projects/2016_DigiPid/Altera/db/cmpr_drb.tdf Line: 22
Info (12033): Analysis and Synthesis generated Signal Tap or debug node instance "auto_signaltap_0"
Info (11170): Starting IP generation for the debug fabric: alt_sld_fab.
Info (11172): 2018.01.23.16:49:13 Progress: Loading slde880867b/alt_sld_fab_wrapper_hw.tcl
Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG
Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH
Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab"
Info (11172): Presplit: "alt_sld_fab" instantiated altera_super_splitter "presplit"
Info (11172): Splitter: "alt_sld_fab" instantiated altera_sld_splitter "splitter"
Info (11172): Sldfabric: "alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"
Info (11172): Ident: "alt_sld_fab" instantiated altera_connection_identification_hub "ident"
Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 6 files
Info (11171): Finished IP generation for the debug fabric: alt_sld_fab.
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/slde880867b/alt_sld_fab.v
    Info (12023): Found entity 1: alt_sld_fab File: D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/alt_sld_fab.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab.v
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab File: D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_ident.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident File: D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_ident.sv Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_presplit.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit File: D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_presplit.sv Line: 3
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd
    Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl File: D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 102
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric File: D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_splitter.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter File: D:/Projects/2016_DigiPid/Altera/db/ip/slde880867b/submodules/alt_sld_fab_alt_sld_fab_splitter.sv Line: 3
Warning (276027): Inferred dual-clock RAM node "UberDigiPid:inst|XferLut_rtl_0" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
Info (19000): Inferred 1 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "UberDigiPid:inst|XferLut_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 16
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 16
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK1
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (278001): Inferred 4 megafunctions from design logic
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "UberDigiPid:inst|Mult3" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 403
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "UberDigiPid:inst|Mult2" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 327
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "UberDigiPid:inst|Mult0" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 325
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "UberDigiPid:inst|Mult1" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 326
Info (12130): Elaborated megafunction instantiation "UberDigiPid:inst|altsyncram:XferLut_rtl_0"
Info (12133): Instantiated megafunction "UberDigiPid:inst|altsyncram:XferLut_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
    Info (12134): Parameter "WIDTH_A" = "16"
    Info (12134): Parameter "WIDTHAD_A" = "10"
    Info (12134): Parameter "NUMWORDS_A" = "1024"
    Info (12134): Parameter "WIDTH_B" = "16"
    Info (12134): Parameter "WIDTHAD_B" = "10"
    Info (12134): Parameter "NUMWORDS_B" = "1024"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_h2e1.tdf
    Info (12023): Found entity 1: altsyncram_h2e1 File: D:/Projects/2016_DigiPid/Altera/db/altsyncram_h2e1.tdf Line: 27
Info (12130): Elaborated megafunction instantiation "UberDigiPid:inst|lpm_mult:Mult3" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 403
Info (12133): Instantiated megafunction "UberDigiPid:inst|lpm_mult:Mult3" with the following parameter: File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 403
    Info (12134): Parameter "LPM_WIDTHA" = "16"
    Info (12134): Parameter "LPM_WIDTHB" = "6"
    Info (12134): Parameter "LPM_WIDTHP" = "22"
    Info (12134): Parameter "LPM_WIDTHR" = "22"
    Info (12134): Parameter "LPM_WIDTHS" = "1"
    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
    Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_bms.tdf
    Info (12023): Found entity 1: mult_bms File: D:/Projects/2016_DigiPid/Altera/db/mult_bms.tdf Line: 28
Info (12130): Elaborated megafunction instantiation "UberDigiPid:inst|lpm_mult:Mult2" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 327
Info (12133): Instantiated megafunction "UberDigiPid:inst|lpm_mult:Mult2" with the following parameter: File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 327
    Info (12134): Parameter "LPM_WIDTHA" = "18"
    Info (12134): Parameter "LPM_WIDTHB" = "17"
    Info (12134): Parameter "LPM_WIDTHP" = "35"
    Info (12134): Parameter "LPM_WIDTHR" = "35"
    Info (12134): Parameter "LPM_WIDTHS" = "1"
    Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED"
    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
    Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_1hs.tdf
    Info (12023): Found entity 1: mult_1hs File: D:/Projects/2016_DigiPid/Altera/db/mult_1hs.tdf Line: 28
Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[0]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[0]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[0]~1" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[1]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[1]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[1]~5" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[2]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[2]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[2]~9" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[3]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[3]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[3]~13" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[4]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[4]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[4]~17" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[5]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[5]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[5]~21" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[6]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[6]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[6]~25" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[7]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[7]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[7]~29" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[8]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[8]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[8]~33" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (13310): Register "UberDigiPid:inst|XferOutWrAddr[9]" is converted into an equivalent circuit using register "UberDigiPid:inst|XferOutWrAddr[9]~_emulated" and latch "UberDigiPid:inst|XferOutWrAddr[9]~37" File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
Info (286031): Timing-Driven Synthesis is running on partition "Top"
Info (128000): Starting physical synthesis optimizations for speed
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info (332127): Assuming a default timing requirement
Info (332111): Found 8 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):    1.000      AdcBusy
    Info (332111):   41.666        Clk24
    Info (332111):    9.999 inst3|altpll_component|auto_generated|pll1|clk[0]
    Info (332111):   99.998 inst3|altpll_component|auto_generated|pll1|clk[1]
    Info (332111):    1.000        McuRD
    Info (332111):    1.000        McuWR
    Info (332111):    1.000 UberDigiPid:inst|DacClk
    Info (332111):    1.000       VcoMon
Info (128002): Starting physical synthesis algorithm register retiming
Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
Info (13000): Registers with preset signals will power-up high File: c:/intel/17.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 356
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286031): Timing-Driven Synthesis is running on partition "sld_signaltap:auto_signaltap_0"
Info (128000): Starting physical synthesis optimizations for speed
Info (128002): Starting physical synthesis algorithm register retiming
Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
Info (13000): Registers with preset signals will power-up high File: c:/intel/17.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd Line: 386
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286031): Timing-Driven Synthesis is running on partition "sld_hub:auto_hub"
Info (128000): Starting physical synthesis optimizations for speed
Info (128002): Starting physical synthesis algorithm register retiming
Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:00
Info (144001): Generated suppressed messages file D:/Projects/2016_DigiPid/Altera/DigiPid.map.smsg
Info (35024): Successfully connected in-system debug instance "auto_signaltap_0" to all 193 required data inputs, trigger inputs, acquisition clocks, and dynamic pins
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 3507 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 31 input pins
    Info (21059): Implemented 24 output pins
    Info (21060): Implemented 16 bidirectional pins
    Info (21061): Implemented 3298 logic cells
    Info (21064): Implemented 128 RAM segments
    Info (21065): Implemented 1 PLLs
    Info (21062): Implemented 8 DSP elements
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 21 warnings
    Info: Peak virtual memory: 752 megabytes
    Info: Processing ended: Tue Jan 23 16:49:43 2018
    Info: Elapsed time: 00:00:53
    Info: Total CPU time (on all processors): 00:01:16


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/Projects/2016_DigiPid/Altera/DigiPid.map.smsg.


