<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">TimeQuest Timing Analyzer report for DigiPid
Tue Jan 23 16:50:36 2018
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Slow 1200mV 85C Model Setup Summary
  7. Slow 1200mV 85C Model Hold Summary
  8. Slow 1200mV 85C Model Recovery Summary
  9. Slow 1200mV 85C Model Removal Summary
 10. Slow 1200mV 85C Model Minimum Pulse Width Summary
 11. Slow 1200mV 85C Model Metastability Summary
 12. Slow 1200mV 0C Model Fmax Summary
 13. Slow 1200mV 0C Model Setup Summary
 14. Slow 1200mV 0C Model Hold Summary
 15. Slow 1200mV 0C Model Recovery Summary
 16. Slow 1200mV 0C Model Removal Summary
 17. Slow 1200mV 0C Model Minimum Pulse Width Summary
 18. Slow 1200mV 0C Model Metastability Summary
 19. Fast 1200mV 0C Model Setup Summary
 20. Fast 1200mV 0C Model Hold Summary
 21. Fast 1200mV 0C Model Recovery Summary
 22. Fast 1200mV 0C Model Removal Summary
 23. Fast 1200mV 0C Model Minimum Pulse Width Summary
 24. Fast 1200mV 0C Model Metastability Summary
 25. Multicorner Timing Analysis Summary
 26. Board Trace Model Assignments
 27. Input Transition Times
 28. Signal Integrity Metrics (Slow 1200mv 0c Model)
 29. Signal Integrity Metrics (Slow 1200mv 85c Model)
 30. Signal Integrity Metrics (Fast 1200mv 0c Model)
 31. Setup Transfers
 32. Hold Transfers
 33. Recovery Transfers
 34. Removal Transfers
 35. Report TCCS
 36. Report RSKM
 37. Unconstrained Paths Summary
 38. Clock Status Summary
 39. Unconstrained Input Ports
 40. Unconstrained Output Ports
 41. Unconstrained Input Ports
 42. Unconstrained Output Ports
 43. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2017  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.



+---------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                               ;
+-----------------------+---------------------------------------------------------+
; Quartus Prime Version ; Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition ;
; Timing Analyzer       ; TimeQuest                                               ;
; Revision Name         ; DigiPid                                                 ;
; Device Family         ; MAX 10                                                  ;
; Device Name           ; 10M08SAE144I7G                                          ;
; Timing Models         ; Final                                                   ;
; Delay Model           ; Combined                                                ;
; Rise/Fall Delays      ; Enabled                                                 ;
+-----------------------+---------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.65        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  21.8%      ;
;     Processors 3-4         ;  21.6%      ;
+----------------------------+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                    ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+
; Clock Name          ; Type ; Period  ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                 ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+
; altera_reserved_tck ; Base ; 100.000 ; 10.0 MHz  ; 0.000 ; 50.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { altera_reserved_tck } ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+


+-----------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                        ;
+------------+-----------------+---------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name          ; Note ;
+------------+-----------------+---------------------+------+
; 168.35 MHz ; 168.35 MHz      ; altera_reserved_tck ;      ;
+------------+-----------------+---------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+----------------------------------------------+
; Slow 1200mV 85C Model Setup Summary          ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 47.030 ; 0.000         ;
+---------------------+--------+---------------+


+---------------------------------------------+
; Slow 1200mV 85C Model Hold Summary          ;
+---------------------+-------+---------------+
; Clock               ; Slack ; End Point TNS ;
+---------------------+-------+---------------+
; altera_reserved_tck ; 0.320 ; 0.000         ;
+---------------------+-------+---------------+


+----------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary       ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 96.855 ; 0.000         ;
+---------------------+--------+---------------+


+---------------------------------------------+
; Slow 1200mV 85C Model Removal Summary       ;
+---------------------+-------+---------------+
; Clock               ; Slack ; End Point TNS ;
+---------------------+-------+---------------+
; altera_reserved_tck ; 0.914 ; 0.000         ;
+---------------------+-------+---------------+


+---------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+---------------------+--------+--------------------+
; Clock               ; Slack  ; End Point TNS      ;
+---------------------+--------+--------------------+
; altera_reserved_tck ; 49.461 ; 0.000              ;
+---------------------+--------+--------------------+


-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 2
Shortest Synchronizer Chain: 4 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 343.873 ns




+-----------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                         ;
+------------+-----------------+---------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name          ; Note ;
+------------+-----------------+---------------------+------+
; 179.92 MHz ; 179.92 MHz      ; altera_reserved_tck ;      ;
+------------+-----------------+---------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+----------------------------------------------+
; Slow 1200mV 0C Model Setup Summary           ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 47.221 ; 0.000         ;
+---------------------+--------+---------------+


+---------------------------------------------+
; Slow 1200mV 0C Model Hold Summary           ;
+---------------------+-------+---------------+
; Clock               ; Slack ; End Point TNS ;
+---------------------+-------+---------------+
; altera_reserved_tck ; 0.310 ; 0.000         ;
+---------------------+-------+---------------+


+----------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary        ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 97.148 ; 0.000         ;
+---------------------+--------+---------------+


+---------------------------------------------+
; Slow 1200mV 0C Model Removal Summary        ;
+---------------------+-------+---------------+
; Clock               ; Slack ; End Point TNS ;
+---------------------+-------+---------------+
; altera_reserved_tck ; 0.837 ; 0.000         ;
+---------------------+-------+---------------+


+--------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+---------------------+--------+-------------------+
; Clock               ; Slack  ; End Point TNS     ;
+---------------------+--------+-------------------+
; altera_reserved_tck ; 49.467 ; 0.000             ;
+---------------------+--------+-------------------+


----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 2
Shortest Synchronizer Chain: 4 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 344.414 ns




+----------------------------------------------+
; Fast 1200mV 0C Model Setup Summary           ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 49.129 ; 0.000         ;
+---------------------+--------+---------------+


+---------------------------------------------+
; Fast 1200mV 0C Model Hold Summary           ;
+---------------------+-------+---------------+
; Clock               ; Slack ; End Point TNS ;
+---------------------+-------+---------------+
; altera_reserved_tck ; 0.118 ; 0.000         ;
+---------------------+-------+---------------+


+----------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary        ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 98.485 ; 0.000         ;
+---------------------+--------+---------------+


+---------------------------------------------+
; Fast 1200mV 0C Model Removal Summary        ;
+---------------------+-------+---------------+
; Clock               ; Slack ; End Point TNS ;
+---------------------+-------+---------------+
; altera_reserved_tck ; 0.410 ; 0.000         ;
+---------------------+-------+---------------+


+--------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+---------------------+--------+-------------------+
; Clock               ; Slack  ; End Point TNS     ;
+---------------------+--------+-------------------+
; altera_reserved_tck ; 49.253 ; 0.000             ;
+---------------------+--------+-------------------+


----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 2
Shortest Synchronizer Chain: 4 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 347.804 ns




+----------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                              ;
+----------------------+--------+-------+----------+---------+---------------------+
; Clock                ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+----------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack     ; 47.030 ; 0.118 ; 96.855   ; 0.410   ; 49.253              ;
;  altera_reserved_tck ; 47.030 ; 0.118 ; 96.855   ; 0.410   ; 49.253              ;
; Design-wide TNS      ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  altera_reserved_tck ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+----------------------+--------+-------+----------+---------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin                 ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; DacClk              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; nRfOutEn            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; TP1                 ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; TP2                 ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; nAdcCnvst           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; TtlOut10MHz         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; TtlOut              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[15]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[14]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[13]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[12]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[11]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[10]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[9]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[8]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[7]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[6]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[5]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[4]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[3]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[2]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[1]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DacDat[0]           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[15]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[14]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[13]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[12]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[11]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[10]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[9]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[8]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[7]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[6]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[5]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[4]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[3]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[2]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[1]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; McuData[0]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; altera_reserved_tdo ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+---------------------------------------------------------------------------------+
; Input Transition Times                                                          ;
+---------------------+-----------------------+-----------------+-----------------+
; Pin                 ; I/O Standard          ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------------+-----------------------+-----------------+-----------------+
; McuData[15]         ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[14]         ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[13]         ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[12]         ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[11]         ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[10]         ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[9]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[8]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[7]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[6]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[5]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[4]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[3]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[2]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[1]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuData[0]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; StopIn              ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; TtlIn               ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuWR               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; McuAddr[2]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuAddr[1]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuAddr[0]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuRD               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; McuAddr[4]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; McuAddr[3]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; Clk24               ; 2.5 V                 ; 2000 ps         ; 2000 ps         ;
; AdcDat[15]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcBusy             ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[14]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[13]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[12]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[11]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[10]          ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[9]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[8]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[7]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[6]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[5]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[4]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[3]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[2]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[1]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; AdcDat[0]           ; 3.3-V LVCMOS          ; 2640 ps         ; 2640 ps         ;
; VcoMon              ; LVDS                  ; 2000 ps         ; 2000 ps         ;
; altera_reserved_tms ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tck ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tdi ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_CONFIG_SEL~ ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_nCONFIG~    ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_nSTATUS~    ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_CONF_DONE~  ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; VcoMon(n)           ; LVDS                  ; 2000 ps         ; 2000 ps         ;
+---------------------+-----------------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DacClk              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; nRfOutEn            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; TP1                 ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.25e-09 V                   ; 2.41 V              ; -0.0859 V           ; 0.289 V                              ; 0.136 V                              ; 3.15e-10 s                  ; 4.16e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.25e-09 V                  ; 2.41 V             ; -0.0859 V          ; 0.289 V                             ; 0.136 V                             ; 3.15e-10 s                 ; 4.16e-10 s                 ; No                        ; Yes                       ;
; TP2                 ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.25e-09 V                   ; 2.41 V              ; -0.0871 V           ; 0.291 V                              ; 0.138 V                              ; 3.15e-10 s                  ; 4.16e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.25e-09 V                  ; 2.41 V             ; -0.0871 V          ; 0.291 V                             ; 0.138 V                             ; 3.15e-10 s                 ; 4.16e-10 s                 ; No                        ; Yes                       ;
; nAdcCnvst           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; TtlOut10MHz         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0389 V           ; 0.263 V                              ; 0.324 V                              ; 8.79e-10 s                  ; 8.89e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0389 V          ; 0.263 V                             ; 0.324 V                             ; 8.79e-10 s                 ; 8.89e-10 s                 ; No                        ; No                        ;
; TtlOut              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; DacDat[15]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; DacDat[14]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; DacDat[13]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0389 V           ; 0.263 V                              ; 0.324 V                              ; 8.79e-10 s                  ; 8.89e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0389 V          ; 0.263 V                             ; 0.324 V                             ; 8.79e-10 s                 ; 8.89e-10 s                 ; No                        ; No                        ;
; DacDat[12]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; DacDat[11]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0389 V           ; 0.263 V                              ; 0.324 V                              ; 8.79e-10 s                  ; 8.89e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0389 V          ; 0.263 V                             ; 0.324 V                             ; 8.79e-10 s                 ; 8.89e-10 s                 ; No                        ; No                        ;
; DacDat[10]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.09 V              ; -0.00102 V          ; 0.306 V                              ; 0.211 V                              ; 8.15e-09 s                  ; 8.39e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.61e-08 V                  ; 3.09 V             ; -0.00102 V         ; 0.306 V                             ; 0.211 V                             ; 8.15e-09 s                 ; 8.39e-09 s                 ; No                        ; Yes                       ;
; DacDat[9]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0389 V           ; 0.263 V                              ; 0.324 V                              ; 8.79e-10 s                  ; 8.89e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0389 V          ; 0.263 V                             ; 0.324 V                             ; 8.79e-10 s                 ; 8.89e-10 s                 ; No                        ; No                        ;
; DacDat[8]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; DacDat[7]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0389 V           ; 0.263 V                              ; 0.324 V                              ; 8.79e-10 s                  ; 8.89e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0389 V          ; 0.263 V                             ; 0.324 V                             ; 8.79e-10 s                 ; 8.89e-10 s                 ; No                        ; No                        ;
; DacDat[6]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; DacDat[5]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0389 V           ; 0.263 V                              ; 0.324 V                              ; 8.79e-10 s                  ; 8.89e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0389 V          ; 0.263 V                             ; 0.324 V                             ; 8.79e-10 s                 ; 8.89e-10 s                 ; No                        ; No                        ;
; DacDat[4]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; DacDat[3]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0392 V           ; 0.263 V                              ; 0.326 V                              ; 8.79e-10 s                  ; 8.91e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0392 V          ; 0.263 V                             ; 0.326 V                             ; 8.79e-10 s                 ; 8.91e-10 s                 ; No                        ; No                        ;
; DacDat[2]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.0389 V           ; 0.263 V                              ; 0.324 V                              ; 8.79e-10 s                  ; 8.89e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.0389 V          ; 0.263 V                             ; 0.324 V                             ; 8.79e-10 s                 ; 8.89e-10 s                 ; No                        ; No                        ;
; DacDat[1]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.195 V                              ; 0.236 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.195 V                             ; 0.236 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; DacDat[0]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[15]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[14]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[13]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.195 V                              ; 0.236 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.195 V                             ; 0.236 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.195 V                              ; 0.236 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.195 V                             ; 0.236 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.195 V                              ; 0.236 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.195 V                             ; 0.236 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.09 V              ; -0.00102 V          ; 0.306 V                              ; 0.211 V                              ; 8.15e-09 s                  ; 8.39e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.61e-08 V                  ; 3.09 V             ; -0.00102 V         ; 0.306 V                             ; 0.211 V                             ; 8.15e-09 s                 ; 8.39e-09 s                 ; No                        ; Yes                       ;
; McuData[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.09 V              ; -0.00102 V          ; 0.306 V                              ; 0.211 V                              ; 8.15e-09 s                  ; 8.39e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.61e-08 V                  ; 3.09 V             ; -0.00102 V         ; 0.306 V                             ; 0.211 V                             ; 8.15e-09 s                 ; 8.39e-09 s                 ; No                        ; Yes                       ;
; McuData[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.195 V                              ; 0.236 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.195 V                             ; 0.236 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.195 V                              ; 0.236 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.195 V                             ; 0.236 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.196 V                              ; 0.235 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.196 V                             ; 0.235 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; McuData[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.61e-08 V                   ; 3.13 V              ; -0.043 V            ; 0.195 V                              ; 0.236 V                              ; 8.37e-10 s                  ; 8.32e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.61e-08 V                  ; 3.13 V             ; -0.043 V           ; 0.195 V                             ; 0.236 V                             ; 8.37e-10 s                 ; 8.32e-10 s                 ; No                        ; No                        ;
; altera_reserved_tdo ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.73e-08 V                   ; 3.2 V               ; -0.127 V            ; 0.219 V                              ; 0.346 V                              ; 4.45e-10 s                  ; 4.51e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.73e-08 V                  ; 3.2 V              ; -0.127 V           ; 0.219 V                             ; 0.346 V                             ; 4.45e-10 s                 ; 4.51e-10 s                 ; No                        ; No                        ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DacClk              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; nRfOutEn            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; TP1                 ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.16e-06 V                   ; 2.37 V              ; -0.049 V            ; 0.154 V                              ; 0.186 V                              ; 4.63e-10 s                  ; 4.5e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 1.16e-06 V                  ; 2.37 V             ; -0.049 V           ; 0.154 V                             ; 0.186 V                             ; 4.63e-10 s                 ; 4.5e-10 s                  ; Yes                       ; Yes                       ;
; TP2                 ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.16e-06 V                   ; 2.37 V              ; -0.0508 V           ; 0.153 V                              ; 0.187 V                              ; 4.63e-10 s                  ; 4.49e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.16e-06 V                  ; 2.37 V             ; -0.0508 V          ; 0.153 V                             ; 0.187 V                             ; 4.63e-10 s                 ; 4.49e-10 s                 ; Yes                       ; Yes                       ;
; nAdcCnvst           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; TtlOut10MHz         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.239 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.239 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; TtlOut              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[15]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[14]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[13]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.239 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.239 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[12]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[11]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.239 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.239 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[10]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.08 V              ; 6.03e-06 V          ; 0.224 V                              ; 0.111 V                              ; 9.78e-09 s                  ; 1.02e-08 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.08 V             ; 6.03e-06 V         ; 0.224 V                             ; 0.111 V                             ; 9.78e-09 s                 ; 1.02e-08 s                 ; Yes                       ; Yes                       ;
; DacDat[9]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.239 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.239 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[8]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[7]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.239 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.239 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[6]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[5]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.239 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.239 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[4]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[3]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.241 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.241 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[2]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.1 V               ; -0.0185 V           ; 0.239 V                              ; 0.18 V                               ; 1.08e-09 s                  ; 1.18e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.03e-06 V                  ; 3.1 V              ; -0.0185 V          ; 0.239 V                             ; 0.18 V                              ; 1.08e-09 s                 ; 1.18e-09 s                 ; Yes                       ; No                        ;
; DacDat[1]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.298 V                              ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.298 V                             ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; DacDat[0]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[15]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[14]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[13]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.298 V                              ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.298 V                             ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.298 V                              ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.298 V                             ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.298 V                              ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.298 V                             ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.08 V              ; 6.03e-06 V          ; 0.224 V                              ; 0.111 V                              ; 9.78e-09 s                  ; 1.02e-08 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.08 V             ; 6.03e-06 V         ; 0.224 V                             ; 0.111 V                             ; 9.78e-09 s                 ; 1.02e-08 s                 ; Yes                       ; Yes                       ;
; McuData[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.08 V              ; 6.03e-06 V          ; 0.224 V                              ; 0.111 V                              ; 9.78e-09 s                  ; 1.02e-08 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.08 V             ; 6.03e-06 V         ; 0.224 V                             ; 0.111 V                             ; 9.78e-09 s                 ; 1.02e-08 s                 ; Yes                       ; Yes                       ;
; McuData[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.298 V                              ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.298 V                             ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.298 V                              ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.298 V                             ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.3 V                                ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.3 V                               ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; McuData[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.03e-06 V                   ; 3.11 V              ; -0.0202 V           ; 0.298 V                              ; 0.218 V                              ; 9.13e-10 s                  ; 1.02e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 6.03e-06 V                  ; 3.11 V             ; -0.0202 V          ; 0.298 V                             ; 0.218 V                             ; 9.13e-10 s                 ; 1.02e-09 s                 ; Yes                       ; Yes                       ;
; altera_reserved_tdo ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.41e-06 V                   ; 3.16 V              ; -0.0688 V           ; 0.26 V                               ; 0.209 V                              ; 4.69e-10 s                  ; 6.21e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.41e-06 V                  ; 3.16 V             ; -0.0688 V          ; 0.26 V                              ; 0.209 V                             ; 4.69e-10 s                 ; 6.21e-10 s                 ; No                        ; No                        ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DacClk              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; nRfOutEn            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; TP1                 ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 9.95e-08 V                   ; 2.78 V              ; -0.0452 V           ; 0.248 V                              ; 0.108 V                              ; 2.67e-10 s                  ; 2.75e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 9.95e-08 V                  ; 2.78 V             ; -0.0452 V          ; 0.248 V                             ; 0.108 V                             ; 2.67e-10 s                 ; 2.75e-10 s                 ; No                        ; Yes                       ;
; TP2                 ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 9.94e-08 V                   ; 2.78 V              ; -0.0444 V           ; 0.25 V                               ; 0.107 V                              ; 2.67e-10 s                  ; 2.75e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 9.94e-08 V                  ; 2.78 V             ; -0.0444 V          ; 0.25 V                              ; 0.107 V                             ; 2.67e-10 s                 ; 2.75e-10 s                 ; No                        ; Yes                       ;
; nAdcCnvst           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; TtlOut10MHz         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.52 V              ; -0.0321 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.52 V             ; -0.0321 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; TtlOut              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[15]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[14]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[13]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.52 V              ; -0.0321 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.52 V             ; -0.0321 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[12]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[11]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.52 V              ; -0.0321 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.52 V             ; -0.0321 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[10]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.47 V              ; -0.00243 V          ; 0.341 V                              ; 0.276 V                              ; 6.73e-09 s                  ; 7.16e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.47 V             ; -0.00243 V         ; 0.341 V                             ; 0.276 V                             ; 6.73e-09 s                 ; 7.16e-09 s                 ; No                        ; Yes                       ;
; DacDat[9]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.52 V              ; -0.0321 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.52 V             ; -0.0321 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[8]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[7]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.52 V              ; -0.0321 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.52 V             ; -0.0321 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[6]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[5]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.52 V              ; -0.0321 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.52 V             ; -0.0321 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[4]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[3]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0325 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0325 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[2]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.52 V              ; -0.0321 V           ; 0.324 V                              ; 0.176 V                              ; 6.87e-10 s                  ; 8.14e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.52 V             ; -0.0321 V          ; 0.324 V                             ; 0.176 V                             ; 6.87e-10 s                 ; 8.14e-10 s                 ; No                        ; Yes                       ;
; DacDat[1]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.252 V                              ; 6.55e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.252 V                             ; 6.55e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; DacDat[0]           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[15]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[14]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[13]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.252 V                              ; 6.55e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.252 V                             ; 6.55e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.252 V                              ; 6.55e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.252 V                             ; 6.55e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.252 V                              ; 6.55e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.252 V                             ; 6.55e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.47 V              ; -0.00243 V          ; 0.341 V                              ; 0.276 V                              ; 6.73e-09 s                  ; 7.16e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.47 V             ; -0.00243 V         ; 0.341 V                             ; 0.276 V                             ; 6.73e-09 s                 ; 7.16e-09 s                 ; No                        ; Yes                       ;
; McuData[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.47 V              ; -0.00243 V          ; 0.341 V                              ; 0.276 V                              ; 6.73e-09 s                  ; 7.16e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.47 V             ; -0.00243 V         ; 0.341 V                             ; 0.276 V                             ; 6.73e-09 s                 ; 7.16e-09 s                 ; No                        ; Yes                       ;
; McuData[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.252 V                              ; 6.55e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.252 V                             ; 6.55e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.252 V                              ; 6.55e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.252 V                             ; 6.55e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.251 V                              ; 6.54e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.251 V                             ; 6.54e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; McuData[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 8.93e-07 V                   ; 3.53 V              ; -0.0306 V           ; 0.247 V                              ; 0.252 V                              ; 6.55e-10 s                  ; 6.68e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 8.93e-07 V                  ; 3.53 V             ; -0.0306 V          ; 0.247 V                             ; 0.252 V                             ; 6.55e-10 s                 ; 6.68e-10 s                 ; No                        ; Yes                       ;
; altera_reserved_tdo ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------+
; Setup Transfers                                                                       ;
+---------------------+---------------------+----------+----------+----------+----------+
; From Clock          ; To Clock            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------+---------------------+----------+----------+----------+----------+
; altera_reserved_tck ; altera_reserved_tck ; 6844     ; 0        ; 64       ; 0        ;
+---------------------+---------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------+
; Hold Transfers                                                                        ;
+---------------------+---------------------+----------+----------+----------+----------+
; From Clock          ; To Clock            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------+---------------------+----------+----------+----------+----------+
; altera_reserved_tck ; altera_reserved_tck ; 6844     ; 0        ; 64       ; 0        ;
+---------------------+---------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------+
; Recovery Transfers                                                                    ;
+---------------------+---------------------+----------+----------+----------+----------+
; From Clock          ; To Clock            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------+---------------------+----------+----------+----------+----------+
; altera_reserved_tck ; altera_reserved_tck ; 405      ; 0        ; 0        ; 0        ;
+---------------------+---------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------+
; Removal Transfers                                                                     ;
+---------------------+---------------------+----------+----------+----------+----------+
; From Clock          ; To Clock            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------+---------------------+----------+----------+----------+----------+
; altera_reserved_tck ; altera_reserved_tck ; 405      ; 0        ; 0        ; 0        ;
+---------------------+---------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths Summary                    ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 7     ; 7    ;
; Unconstrained Input Ports       ; 43    ; 43   ;
; Unconstrained Input Port Paths  ; 2025  ; 2025 ;
; Unconstrained Output Ports      ; 40    ; 40   ;
; Unconstrained Output Port Paths ; 57    ; 57   ;
+---------------------------------+-------+------+


+----------------------------------------------------------------------+
; Clock Status Summary                                                 ;
+-------------------------+---------------------+------+---------------+
; Target                  ; Clock               ; Type ; Status        ;
+-------------------------+---------------------+------+---------------+
; AdcBusy                 ;                     ; Base ; Unconstrained ;
; Clk24                   ;                     ; Base ; Unconstrained ;
; McuRD                   ;                     ; Base ; Unconstrained ;
; McuWR                   ;                     ; Base ; Unconstrained ;
; TtlIn                   ;                     ; Base ; Unconstrained ;
; UberDigiPid:inst|DacClk ;                     ; Base ; Unconstrained ;
; VcoMon                  ;                     ; Base ; Unconstrained ;
; altera_reserved_tck     ; altera_reserved_tck ; Base ; Constrained   ;
+-------------------------+---------------------+------+---------------+


+------------------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports                                                                                  ;
+---------------------+--------------------------------------------------------------------------------------+
; Input Port          ; Comment                                                                              ;
+---------------------+--------------------------------------------------------------------------------------+
; AdcDat[0]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[1]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[2]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[3]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[4]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[5]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[6]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[7]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[8]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[9]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[10]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[11]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[12]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[13]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[14]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[15]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Clk24               ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[0]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[1]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[2]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[3]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[4]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[0]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[1]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[2]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[3]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[4]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[5]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[6]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[7]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[8]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[9]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[10]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[11]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[12]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[13]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[14]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[15]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuRD               ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; StopIn              ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TtlIn               ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; altera_reserved_tdi ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; altera_reserved_tms ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+---------------------+--------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                                  ;
+---------------------+---------------------------------------------------------------------------------------+
; Output Port         ; Comment                                                                               ;
+---------------------+---------------------------------------------------------------------------------------+
; DacClk              ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[0]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[1]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[2]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[3]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[4]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[5]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[6]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[7]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[8]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[9]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[10]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[11]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[12]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[13]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[14]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[15]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[0]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[1]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[2]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[3]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[4]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[5]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[6]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[7]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[8]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[9]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[10]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[11]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[12]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[13]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[14]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[15]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TP1                 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TP2                 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TtlOut              ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TtlOut10MHz         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; altera_reserved_tdo ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nAdcCnvst           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRfOutEn            ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+---------------------+---------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports                                                                                  ;
+---------------------+--------------------------------------------------------------------------------------+
; Input Port          ; Comment                                                                              ;
+---------------------+--------------------------------------------------------------------------------------+
; AdcDat[0]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[1]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[2]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[3]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[4]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[5]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[6]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[7]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[8]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[9]           ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[10]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[11]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[12]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[13]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[14]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AdcDat[15]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Clk24               ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[0]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[1]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[2]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[3]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuAddr[4]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[0]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[1]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[2]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[3]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[4]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[5]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[6]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[7]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[8]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[9]          ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[10]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[11]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[12]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[13]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[14]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[15]         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuRD               ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; StopIn              ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TtlIn               ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; altera_reserved_tdi ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; altera_reserved_tms ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+---------------------+--------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                                  ;
+---------------------+---------------------------------------------------------------------------------------+
; Output Port         ; Comment                                                                               ;
+---------------------+---------------------------------------------------------------------------------------+
; DacClk              ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[0]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[1]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[2]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[3]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[4]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[5]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[6]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[7]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[8]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[9]           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[10]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[11]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[12]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[13]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[14]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DacDat[15]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[0]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[1]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[2]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[3]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[4]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[5]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[6]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[7]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[8]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[9]          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[10]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[11]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[12]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[13]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[14]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; McuData[15]         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TP1                 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TP2                 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TtlOut              ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; TtlOut10MHz         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; altera_reserved_tdo ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nAdcCnvst           ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRfOutEn            ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+---------------------+---------------------------------------------------------------------------------------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
    Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition
    Info: Processing started: Tue Jan 23 16:50:30 2018
Info: Command: quartus_sta DigiPid -c DigiPid
Info: qsta_default_script.tcl version: #3
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Warning (335093): TimeQuest Timing Analyzer is analyzing 26 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis &amp; Synthesis report.
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity sld_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz   
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Critical Warning (332012): Synopsys Design Constraints File file not found: 'DigiPid.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Warning (332125): Found combinational loop of 2 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 82
    Warning (332126): Node "inst|StatusRead~0|combout"
    Warning (332126): Node "inst|StatusRead~0|datac"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[0]~2|combout"
    Warning (332126): Node "inst|XferOutWrAddr~60|datad"
    Warning (332126): Node "inst|XferOutWrAddr~60|combout"
    Warning (332126): Node "inst|XferOutWrAddr[0]~2|datad"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[1]~6|combout"
    Warning (332126): Node "inst|XferOutWrAddr~61|datac"
    Warning (332126): Node "inst|XferOutWrAddr~61|combout"
    Warning (332126): Node "inst|XferOutWrAddr[1]~6|datad"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[2]~10|combout"
    Warning (332126): Node "inst|XferOutWrAddr~62|datad"
    Warning (332126): Node "inst|XferOutWrAddr~62|combout"
    Warning (332126): Node "inst|XferOutWrAddr[2]~10|datac"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[3]~14|combout"
    Warning (332126): Node "inst|XferOutWrAddr~63|datad"
    Warning (332126): Node "inst|XferOutWrAddr~63|combout"
    Warning (332126): Node "inst|XferOutWrAddr[3]~14|datad"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[4]~18|combout"
    Warning (332126): Node "inst|XferOutWrAddr~64|datad"
    Warning (332126): Node "inst|XferOutWrAddr~64|combout"
    Warning (332126): Node "inst|XferOutWrAddr[4]~18|datad"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[5]~22|combout"
    Warning (332126): Node "inst|XferOutWrAddr~65|datac"
    Warning (332126): Node "inst|XferOutWrAddr~65|combout"
    Warning (332126): Node "inst|XferOutWrAddr[5]~22|datad"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[6]~26|combout"
    Warning (332126): Node "inst|XferOutWrAddr~66|datad"
    Warning (332126): Node "inst|XferOutWrAddr~66|combout"
    Warning (332126): Node "inst|XferOutWrAddr[6]~26|datad"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[7]~30|combout"
    Warning (332126): Node "inst|XferOutWrAddr~67|datad"
    Warning (332126): Node "inst|XferOutWrAddr~67|combout"
    Warning (332126): Node "inst|XferOutWrAddr[7]~30|datad"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[8]~34|combout"
    Warning (332126): Node "inst|XferOutWrAddr~68|datac"
    Warning (332126): Node "inst|XferOutWrAddr~68|combout"
    Warning (332126): Node "inst|XferOutWrAddr[8]~34|datad"
Warning (332125): Found combinational loop of 4 nodes File: D:/Projects/2016_DigiPid/Altera/DigiPid.sv Line: 142
    Warning (332126): Node "inst|XferOutWrAddr[9]~38|combout"
    Warning (332126): Node "inst|XferOutWrAddr~69|datad"
    Warning (332126): Node "inst|XferOutWrAddr~69|combout"
    Warning (332126): Node "inst|XferOutWrAddr[9]~38|datad"
Warning (332060): Node: Clk24 was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register UberDigiPid:inst|DacData[15] is being clocked by Clk24
Warning (332060): Node: McuWR was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register UberDigiPid:inst|LocalReg[6][0] is being clocked by McuWR
Warning (332060): Node: McuRD was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Latch UberDigiPid:inst|XferOutWrAddr[1]~5 is being clocked by McuRD
Warning (332060): Node: AdcBusy was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register DP_RAM:HistoryADC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated|ram_block1a7~porta_we_reg is being clocked by AdcBusy
Warning (332060): Node: UberDigiPid:inst|DacClk was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register DP_RAM:HistoryDAC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated|ram_block1a7~porta_we_reg is being clocked by UberDigiPid:inst|DacClk
Warning (332060): Node: VcoMon was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register FreqCounter:VCO|lpm_counter:LPM_COUNTER_component|cntr_a8i:auto_generated|counter_reg_bit[0] is being clocked by VcoMon
Warning (332060): Node: TtlIn was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0] is being clocked by TtlIn
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: altera_internal_jtag  from: tck  to: tckutap
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
    Warning (332056): Node: inst3|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666
    Warning (332056): Node: inst3|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Info (332146): Worst-case setup slack is 47.030
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    47.030               0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.320
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.320               0.000 altera_reserved_tck 
Info (332146): Worst-case recovery slack is 96.855
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    96.855               0.000 altera_reserved_tck 
Info (332146): Worst-case removal slack is 0.914
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.914               0.000 altera_reserved_tck 
Info (332146): Worst-case minimum pulse width slack is 49.461
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    49.461               0.000 altera_reserved_tck 
Info (332114): Report Metastability: Found 2 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 2
    Info (332114): Shortest Synchronizer Chain: 4 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 343.873 ns
    Info (332114): 
Info (332115): Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 47.030
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -setup
    Info (332115): -stdout
Info (332115): Path #1: Setup slack is 47.030 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][9]
    Info (332115): To Node      : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck (INVERTED)
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      2.468      2.468  R        clock network delay
    Info (332115):      2.675      0.207     uTco  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][9]
    Info (332115):      2.675      0.000 FF  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][9]|q
    Info (332115):      3.076      0.401 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~2|datab
    Info (332115):      3.493      0.417 FR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~2|combout
    Info (332115):      4.222      0.729 RR    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~6|datad
    Info (332115):      4.388      0.166 RR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~6|combout
    Info (332115):      4.629      0.241 RR    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~7|dataa
    Info (332115):      5.038      0.409 RR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~7|combout
    Info (332115):      5.437      0.399 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~12|datad
    Info (332115):      5.603      0.166 RR  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~12|combout
    Info (332115):      5.805      0.202 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~11|datad
    Info (332115):      5.971      0.166 RR  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~11|combout
    Info (332115):      5.971      0.000 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo|d
    Info (332115):      6.060      0.089 RR  CELL  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):     50.000     50.000           latch edge time
    Info (332115):     53.061      3.061  F        clock network delay
    Info (332115):     53.077      0.016           clock pessimism removed
    Info (332115):     53.090      0.013     uTsu  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): 
    Info (332115): Data Arrival Time  :     6.060
    Info (332115): Data Required Time :    53.090
    Info (332115): Slack              :    47.030 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.320
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -hold
    Info (332115): -stdout
Info (332115): Path #1: Hold slack is 0.320 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_mfi:auto_generated|counter_reg_bit[2]
    Info (332115): To Node      : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      2.393      2.393  R        clock network delay
    Info (332115):      2.600      0.207     uTco  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_mfi:auto_generated|counter_reg_bit[2]
    Info (332115):      2.600      0.000 RR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_reg_bit[2]|q
    Info (332115):      3.356      0.756 RR    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a72|portbaddr[2]
    Info (332115):      3.403      0.047 RR  CELL  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           latch edge time
    Info (332115):      2.934      2.934  R        clock network delay
    Info (332115):      2.918     -0.016           clock pessimism removed
    Info (332115):      3.083      0.165      uTh  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): 
    Info (332115): Data Arrival Time  :     3.403
    Info (332115): Data Required Time :     3.083
    Info (332115): Slack              :     0.320 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 recovery paths (0 violated).  Worst case slack is 96.855
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -recovery
    Info (332115): -stdout
Info (332115): Path #1: Recovery slack is 96.855 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all
    Info (332115): To Node      : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      2.475      2.475  R        clock network delay
    Info (332115):      2.682      0.207     uTco  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all
    Info (332115):      2.682      0.000 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all|q
    Info (332115):      3.936      1.254 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all~clkctrl|inclk[0]
    Info (332115):      3.936      0.000 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all~clkctrl|outclk
    Info (332115):      4.855      0.919 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|segment_offset_config_deserialize|dffs[1]|clrn
    Info (332115):      5.553      0.698 FR  CELL  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):    100.000    100.000           latch edge time
    Info (332115):    102.379      2.379  R        clock network delay
    Info (332115):    102.395      0.016           clock pessimism removed
    Info (332115):    102.408      0.013     uTsu  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): 
    Info (332115): Data Arrival Time  :     5.553
    Info (332115): Data Required Time :   102.408
    Info (332115): Slack              :    96.855 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 removal paths (0 violated).  Worst case slack is 0.914
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -removal
    Info (332115): -stdout
Info (332115): Path #1: Removal slack is 0.914 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg
    Info (332115): To Node      : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      2.394      2.394  R        clock network delay
    Info (332115):      2.601      0.207     uTco  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg
    Info (332115):      2.601      0.000 RR  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|clr_reg|q
    Info (332115):      2.895      0.294 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|splitter_nodes_receive_0[3]|clrn
    Info (332115):      3.546      0.651 RF  CELL  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           latch edge time
    Info (332115):      2.474      2.474  R        clock network delay
    Info (332115):      2.458     -0.016           clock pessimism removed
    Info (332115):      2.632      0.174      uTh  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): 
    Info (332115): Data Arrival Time  :     3.546
    Info (332115): Data Required Time :     2.632
    Info (332115): Slack              :     0.914 
    Info (332115): ===================================================================
    Info (332115): 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: Clk24 was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register UberDigiPid:inst|DacData[15] is being clocked by Clk24
Warning (332060): Node: McuWR was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register UberDigiPid:inst|LocalReg[6][0] is being clocked by McuWR
Warning (332060): Node: McuRD was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Latch UberDigiPid:inst|XferOutWrAddr[1]~5 is being clocked by McuRD
Warning (332060): Node: AdcBusy was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register DP_RAM:HistoryADC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated|ram_block1a7~porta_we_reg is being clocked by AdcBusy
Warning (332060): Node: UberDigiPid:inst|DacClk was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register DP_RAM:HistoryDAC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated|ram_block1a7~porta_we_reg is being clocked by UberDigiPid:inst|DacClk
Warning (332060): Node: VcoMon was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register FreqCounter:VCO|lpm_counter:LPM_COUNTER_component|cntr_a8i:auto_generated|counter_reg_bit[0] is being clocked by VcoMon
Warning (332060): Node: TtlIn was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0] is being clocked by TtlIn
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: altera_internal_jtag  from: tck  to: tckutap
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
    Warning (332056): Node: inst3|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666
    Warning (332056): Node: inst3|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Info (332146): Worst-case setup slack is 47.221
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    47.221               0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.310
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.310               0.000 altera_reserved_tck 
Info (332146): Worst-case recovery slack is 97.148
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    97.148               0.000 altera_reserved_tck 
Info (332146): Worst-case removal slack is 0.837
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.837               0.000 altera_reserved_tck 
Info (332146): Worst-case minimum pulse width slack is 49.467
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    49.467               0.000 altera_reserved_tck 
Info (332114): Report Metastability: Found 2 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 2
    Info (332114): Shortest Synchronizer Chain: 4 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 344.414 ns
    Info (332114): 
Info (332115): Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 47.221
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -setup
    Info (332115): -stdout
Info (332115): Path #1: Setup slack is 47.221 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][9]
    Info (332115): To Node      : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck (INVERTED)
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      2.283      2.283  R        clock network delay
    Info (332115):      2.474      0.191     uTco  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][9]
    Info (332115):      2.474      0.000 FF  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][9]|q
    Info (332115):      2.840      0.366 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~2|datab
    Info (332115):      3.221      0.381 FR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~2|combout
    Info (332115):      3.906      0.685 RR    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~6|datad
    Info (332115):      4.060      0.154 RR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~6|combout
    Info (332115):      4.284      0.224 RR    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~7|dataa
    Info (332115):      4.666      0.382 RR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~7|combout
    Info (332115):      5.047      0.381 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~12|datad
    Info (332115):      5.201      0.154 RR  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~12|combout
    Info (332115):      5.386      0.185 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~11|datad
    Info (332115):      5.540      0.154 RR  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~11|combout
    Info (332115):      5.540      0.000 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo|d
    Info (332115):      5.622      0.082 RR  CELL  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):     50.000     50.000           latch edge time
    Info (332115):     52.816      2.816  F        clock network delay
    Info (332115):     52.831      0.015           clock pessimism removed
    Info (332115):     52.843      0.012     uTsu  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): 
    Info (332115): Data Arrival Time  :     5.622
    Info (332115): Data Required Time :    52.843
    Info (332115): Slack              :    47.221 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.310
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -hold
    Info (332115): -stdout
Info (332115): Path #1: Hold slack is 0.310 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_mfi:auto_generated|counter_reg_bit[2]
    Info (332115): To Node      : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      2.215      2.215  R        clock network delay
    Info (332115):      2.406      0.191     uTco  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_mfi:auto_generated|counter_reg_bit[2]
    Info (332115):      2.406      0.000 RR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_reg_bit[2]|q
    Info (332115):      3.111      0.705 RR    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a72|portbaddr[2]
    Info (332115):      3.155      0.044 RR  CELL  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           latch edge time
    Info (332115):      2.711      2.711  R        clock network delay
    Info (332115):      2.696     -0.015           clock pessimism removed
    Info (332115):      2.845      0.149      uTh  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): 
    Info (332115): Data Arrival Time  :     3.155
    Info (332115): Data Required Time :     2.845
    Info (332115): Slack              :     0.310 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 recovery paths (0 violated).  Worst case slack is 97.148
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -recovery
    Info (332115): -stdout
Info (332115): Path #1: Recovery slack is 97.148 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all
    Info (332115): To Node      : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      2.291      2.291  R        clock network delay
    Info (332115):      2.482      0.191     uTco  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all
    Info (332115):      2.482      0.000 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all|q
    Info (332115):      3.623      1.141 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all~clkctrl|inclk[0]
    Info (332115):      3.623      0.000 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all~clkctrl|outclk
    Info (332115):      4.444      0.821 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|segment_offset_config_deserialize|dffs[1]|clrn
    Info (332115):      5.079      0.635 FR  CELL  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):    100.000    100.000           latch edge time
    Info (332115):    102.200      2.200  R        clock network delay
    Info (332115):    102.215      0.015           clock pessimism removed
    Info (332115):    102.227      0.012     uTsu  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): 
    Info (332115): Data Arrival Time  :     5.079
    Info (332115): Data Required Time :   102.227
    Info (332115): Slack              :    97.148 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 removal paths (0 violated).  Worst case slack is 0.837
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -removal
    Info (332115): -stdout
Info (332115): Path #1: Removal slack is 0.837 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg
    Info (332115): To Node      : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      2.215      2.215  R        clock network delay
    Info (332115):      2.406      0.191     uTco  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg
    Info (332115):      2.406      0.000 RR  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|clr_reg|q
    Info (332115):      2.677      0.271 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|splitter_nodes_receive_0[3]|clrn
    Info (332115):      3.271      0.594 RF  CELL  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           latch edge time
    Info (332115):      2.289      2.289  R        clock network delay
    Info (332115):      2.274     -0.015           clock pessimism removed
    Info (332115):      2.434      0.160      uTh  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): 
    Info (332115): Data Arrival Time  :     3.271
    Info (332115): Data Required Time :     2.434
    Info (332115): Slack              :     0.837 
    Info (332115): ===================================================================
    Info (332115): 
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: Clk24 was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register UberDigiPid:inst|DacData[15] is being clocked by Clk24
Warning (332060): Node: McuWR was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register UberDigiPid:inst|LocalReg[6][0] is being clocked by McuWR
Warning (332060): Node: McuRD was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Latch UberDigiPid:inst|XferOutWrAddr[1]~5 is being clocked by McuRD
Warning (332060): Node: AdcBusy was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register DP_RAM:HistoryADC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated|ram_block1a7~porta_we_reg is being clocked by AdcBusy
Warning (332060): Node: UberDigiPid:inst|DacClk was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register DP_RAM:HistoryDAC|altsyncram:altsyncram_component|altsyncram_82j1:auto_generated|ram_block1a7~porta_we_reg is being clocked by UberDigiPid:inst|DacClk
Warning (332060): Node: VcoMon was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register FreqCounter:VCO|lpm_counter:LPM_COUNTER_component|cntr_a8i:auto_generated|counter_reg_bit[0] is being clocked by VcoMon
Warning (332060): Node: TtlIn was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0] is being clocked by TtlIn
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: altera_internal_jtag  from: tck  to: tckutap
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
    Warning (332056): Node: inst3|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666
    Warning (332056): Node: inst3|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Info (332146): Worst-case setup slack is 49.129
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    49.129               0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.118
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.118               0.000 altera_reserved_tck 
Info (332146): Worst-case recovery slack is 98.485
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    98.485               0.000 altera_reserved_tck 
Info (332146): Worst-case removal slack is 0.410
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.410               0.000 altera_reserved_tck 
Info (332146): Worst-case minimum pulse width slack is 49.253
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    49.253               0.000 altera_reserved_tck 
Info (332114): Report Metastability: Found 2 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 2
    Info (332114): Shortest Synchronizer Chain: 4 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 347.804 ns
    Info (332114): 
Info (332115): Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 49.129
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -setup
    Info (332115): -stdout
Info (332115): Path #1: Setup slack is 49.129 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register|dffs[0]
    Info (332115): To Node      : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck (INVERTED)
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      1.083      1.083  R        clock network delay
    Info (332115):      1.169      0.086     uTco  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register|dffs[0]
    Info (332115):      1.169      0.000 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|status_register|dffs[0]|q
    Info (332115):      1.871      0.702 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~5|dataa
    Info (332115):      2.011      0.140 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~5|combout
    Info (332115):      2.113      0.102 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~7|datac
    Info (332115):      2.217      0.104 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|tdo_internal~7|combout
    Info (332115):      2.403      0.186 FF    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~12|datad
    Info (332115):      2.452      0.049 FF  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~12|combout
    Info (332115):      2.551      0.099 FF    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~11|datad
    Info (332115):      2.600      0.049 FF  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo_mux_out~11|combout
    Info (332115):      2.600      0.000 FF    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|tdo|d
    Info (332115):      2.643      0.043 FF  CELL  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):     50.000     50.000           latch edge time
    Info (332115):     51.757      1.757  F        clock network delay
    Info (332115):     51.766      0.009           clock pessimism removed
    Info (332115):     51.772      0.006     uTsu  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo
    Info (332115): 
    Info (332115): Data Arrival Time  :     2.643
    Info (332115): Data Required Time :    51.772
    Info (332115): Slack              :    49.129 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.118
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -hold
    Info (332115): -stdout
Info (332115): Path #1: Hold slack is 0.118 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_mfi:auto_generated|counter_reg_bit[2]
    Info (332115): To Node      : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      1.052      1.052  R        clock network delay
    Info (332115):      1.138      0.086     uTco  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_mfi:auto_generated|counter_reg_bit[2]
    Info (332115):      1.138      0.000 RR  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_reg_bit[2]|q
    Info (332115):      1.456      0.318 RR    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a72|portbaddr[2]
    Info (332115):      1.482      0.026 RR  CELL  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           latch edge time
    Info (332115):      1.304      1.304  R        clock network delay
    Info (332115):      1.295     -0.009           clock pessimism removed
    Info (332115):      1.364      0.069      uTh  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_oc14:auto_generated|ram_block1a72~portb_address_reg0
    Info (332115): 
    Info (332115): Data Arrival Time  :     1.482
    Info (332115): Data Required Time :     1.364
    Info (332115): Slack              :     0.118 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 recovery paths (0 violated).  Worst case slack is 98.485
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -recovery
    Info (332115): -stdout
Info (332115): Path #1: Recovery slack is 98.485 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all
    Info (332115): To Node      : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      1.095      1.095  R        clock network delay
    Info (332115):      1.181      0.086     uTco  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all
    Info (332115):      1.181      0.000 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all|q
    Info (332115):      1.775      0.594 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all~clkctrl|inclk[0]
    Info (332115):      1.775      0.000 FF  CELL  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|reset_all~clkctrl|outclk
    Info (332115):      2.249      0.474 FF    IC  auto_signaltap_0|sld_signaltap_body|sld_signaltap_body|segment_offset_config_deserialize|dffs[1]|clrn
    Info (332115):      2.571      0.322 FR  CELL  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):    100.000    100.000           latch edge time
    Info (332115):    101.041      1.041  R        clock network delay
    Info (332115):    101.050      0.009           clock pessimism removed
    Info (332115):    101.056      0.006     uTsu  sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]
    Info (332115): 
    Info (332115): Data Arrival Time  :     2.571
    Info (332115): Data Required Time :   101.056
    Info (332115): Slack              :    98.485 
    Info (332115): ===================================================================
    Info (332115): 
Info (332115): Report Timing: Found 1 removal paths (0 violated).  Worst case slack is 0.410
    Info (332115): -to_clock [get_clocks {altera_reserved_tck}]
    Info (332115): -removal
    Info (332115): -stdout
Info (332115): Path #1: Removal slack is 0.410 
    Info (332115): ===================================================================
    Info (332115): From Node    : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg
    Info (332115): To Node      : sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): Launch Clock : altera_reserved_tck
    Info (332115): Latch Clock  : altera_reserved_tck
    Info (332115): 
    Info (332115): Data Arrival Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           launch edge time
    Info (332115):      1.052      1.052  R        clock network delay
    Info (332115):      1.138      0.086     uTco  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg
    Info (332115):      1.138      0.000 RR  CELL  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|clr_reg|q
    Info (332115):      1.263      0.125 RR    IC  auto_hub|\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|instrumentation_fabric|alt_sld_fab|splitter_nodes_receive_0[3]|clrn
    Info (332115):      1.565      0.302 RF  CELL  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): 
    Info (332115): Data Required Path:
    Info (332115): 
    Info (332115): Total (ns)  Incr (ns)     Type  Element
    Info (332115): ==========  ========= ==  ====  ===================================
    Info (332115):      0.000      0.000           latch edge time
    Info (332115):      1.093      1.093  R        clock network delay
    Info (332115):      1.084     -0.009           clock pessimism removed
    Info (332115):      1.155      0.071      uTh  sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|splitter_nodes_receive_0[3]
    Info (332115): 
    Info (332115): Data Arrival Time  :     1.565
    Info (332115): Data Required Time :     1.155
    Info (332115): Slack              :     0.410 
    Info (332115): ===================================================================
    Info (332115): 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 95 warnings
    Info: Peak virtual memory: 663 megabytes
    Info: Processing ended: Tue Jan 23 16:50:36 2018
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:07


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