INTERNAL PROTOCOLS AND MAPPING
==============================
Started 2016-12-08  Alan Stummer
Version 2017-12-06  A.S.


FPGA REGISTERS
All registers are 16-bit. All registers can be read back by MCU
===============================================================
REG  WR?  DESCRIPTION
---  ---  ---  -----------
 0   yes  DAC maximum output value: DC (±10V) or RF (0-100%)
 1   yes  DAC minimum output value: DC (±10V) or RF (0-100%)
 2   no   VCO frequency measured, MS
 3   no   VCO frequency measured, LS
 4   
 5   
 6   yes  Control:
          [2:0] 0 = op mode stop
                1 = op mode pulse
                2 = op mode manual
                3 = op mode run
                4 = triangle
                5-7 = not used, ignored
          [3] 0 = DC mode, 1 = RF mode
          [4] 1 = reading frequency counters (so freeze counting)
          [5] TTL output as set by client
          [6] 1=freeze ADC and DAC history while sending to host
          [7] 0=read ADC history, 1=read DAC history
          [15:8] don't care
 7   no   Status: (read resets Output Xfer curve table write address)
          [0] DAC overflow (was stopped at max value)
          [1] DAC underflow (was stopped at min value)
          [2] Integral accumulator overflow (was stopped at max value)
          [3] Integral accumulator underflow (was stopped at min value)
					[4] TTL Input, for client
					[5] not used
					[6] always 1 (to ensure byte is printable ASCII)
					[7] always 0 (to ensure byte is printable ASCII)
					[13:8] not used
					[14] always 1 (to ensure byte is printable ASCII)
					[15] always 0 (to ensure byte is printable ASCII)
 8   yes  DAC value when stopped: DC (±10V) or RF (0-100%)
 9   
10   yes  Pulse frequency, number of 24.414KHz clock cycles per period (0.01-100Hz), e.g. 2Hz = 12207
11   yes  Pulse duty cycle, number of 24.414KHz clock cycles when on (0.01-99.99%), e.g. 10% @ 2Hz = 1221
12   yes  DAC value when manually set in DC or RF modes (0-65535)
13   yes  Gain, Main (8-LSB only, representing 0-100%)
14   yes  PID clock (divisor for 100MHz clk)
15   yes  ADC target value for PID, DC V (±5)
16   yes  Gain, Proportional (8-LSB only, representing 0-100%)
17   yes  Gain, Integral (8-LSB only, representing 0-100%)
18   yes  Gain, Derivative (8-LSB only, representing 0-100%)
19   no   History read, an unsigned 16-bit ADC or DAC sample
20   yes  Output transfer curve value, one entry (1,024 required)
21   no   Verilog version
22   no   Current ADC output data
23   no   Current DAC output data
24   
25   
26   
27   
28   
29   
30   
31

NOTES:
  1) Reading Status resets pointers for reading back monitors and for writing transfer curves