NOTICE: This webpage and associated files is provided for reference only. This is not a kit site! It is a collection of my work here at the University of Toronto in the Physics department. If you are considering using any schematics, designs, or anything else from here then be warned that you had better know something of what you are about to do. No design is guaranteed in any way, including workable schematic, board layout, HDL code, embedded software, user software, component selection, documentation, webpages, or anything.
All that said, if it says here it works then for me it worked. To make the project work may have involved undocumented additions, changes, deletions, tweaks, tunings, alterations, modifications, adjustments, waving of a wand while wearing a pointy black hat, appeals to electron deities and just plain doing whatever it takes to make the project work.
The core of the project is the power supply for the Analog Device's
(Direct Digital Synthesis) development board (
schematic) and associated frequency multipliers and amplifiers. A DDS is a digital IC that can generate any frequency
up to the reference clock oscillator's Nyquist frequency. In the AD9858, a clock frequency of 1GHz can generate
from 0.233Hz to 400MHz. The output frequency is set by:
f o = FW * f sam / 2 32 where f o is the output frequency, FW is the 32-bit frequency word and f sam is the 983.04MHz sample clock frequency.
The desired frequency is mapped out in a LUT (lookup table). On every f sam cycle, the DDS looks in the lookup table for the instantaneous amplitude of f o and sets the output DAC (Digital to Analog Converter) accordingly. Whereas a 1Hz f o would have 1e9 points defining it, a 400MHz f o would have only 2.5 defining points per cycle. In the latter high frequency case, a low pass filter set between the fundamental and second harmonic will clean up the output.
The DDS reference clock is generated by the VCO (Voltage Controlled Oscillator) on the development board. It has been replaced by a 992MHZ VCO from Sirenza (now part of RFMW) capable of running at closer to the maximum 1GHz. An on-board divider cuts the 983.040000MHz down by 16 to 61.440000MHz. The VCO is part of an on-board PLL (Phase Lock Loop). The PLL compares this 61.440000MHz to a very stable reference 61.440000MHz oscillator. This latter reference oscillator is an OCXO (Oven Controlled Crystal Oscillator).
|Daily aging||<±1 PPB|
|Monthly aging||<±20 PPB|
|Annual aging||<±100 PPB|
|10 year aging||<±250PPB|
At any given time, the stability depends not only on aging but also ambient temperature, supply and load. These additional errors can be added to the aging. The cumulative holdover daily stability becomes ±30PPB and is split as follows:
|Temperature stability (0° to 70°)||<±25 PPB|
|Supply variation (±5%)||<±2 PPB|
|Load variation (0-100%)||<±2 PPB|
|Daily aging||<±1 PPB|
Because the OCXO is in an environmentally controlled room, the temperature effect is minimized. The OCXO supply and load too are stable. This resultant stability allows approaching the 40K ground state transition frequency of about 1.28GHz to within 1KHz with quarterly or semi-annual calibration. Calibration is to be done against the local Stratum 3 RF sources - A.K.A. FM radio stations - by using the DDS to generate the carrier frequency and then beating against the FM RF carrier. A 1Hz beat frequency corresponds to 10PPB.
The only power source is a regulated 9V/1.5A adaptor hard-wired into the DDS box. The 9V goes through a power switch. There are four supplies, in the table below. The three regulated supplies use National Semiconductor's LM1086 family of LDO (Low Drop-Out) regulators. Because a large amount of the current goes to the +3.3V DDS core, the power dissipation is equally split between the main +5V and the +3.3V regulators. Two diodes are used before each +5V regulator to reduce the regulators' power dissipation by lower their input voltage.
|Raw +9V||Cooling fan||175mA||75mA|
|Main +5V||Development board dividers||175mA|
|DDS charge pump||105mA|
|Stable +5V||Development board VCO||15mA|
The 321.5MHz DDS output is frequency quadrupled in the RF section. All components are from Mini-Circuits. Attenuators are added as required. The sequence is:
|Sorry, no more chance for asking direct questions, queries, broken links, problems, flak, slings, arrows, kudos, criticism, comments, brickbats, corrections or suggestions.|