NOTICE: This webpage and associated files is provided for reference only. This is not a kit site! It is a collection of my work here at the University of Toronto in the Physics department. If you are considering using any schematics, designs, or anything else from here then be warned that you had better know something of what you are about to do. No design is guaranteed in any way, including workable schematic, board layout, HDL code, embedded software, user software, component selection, documentation, webpages, or anything.
All that said, if it says here it works then for me it worked. To make the project work may have involved undocumented additions, changes, deletions, tweaks, tunings, alterations, modifications, adjustments, waving of a wand while wearing a pointy black hat, appeals to electron deities and just plain doing whatever it takes to make the project work.
Initially this was the n-Pulse Selector project for Robin Marjoribank's lab, started Nov'05. In Dec'05, added the Piezo Driver project for Krister Shalm in Aephraim's lab. The same circuit and board is used in both projects, parts stuffed as required. The Piezo Driver variant is described below.
As the core of a scanning spectrometer, a Fabrey-Perot (FP) junction is adjusted by pressure from a piezo crystal. The differential voltage across the piezo determines the FP resonant wavelength. Two DACs set two supplies: 0-10V trim voltage and a 0-200V offset voltage. As both voltages are computer controlled, the board becomes an automated spectrometer.
At the core of the board is an Altera Cyclone EP1C3T100C6 FPGA. The same Verilog source code is used for both the n-Pulse Selector and Piezo Driver variants, although the latter ignores all of the HV stack triggering section of the former. A USB interface connects the board to the outside world. Dirvers are available for windows Visual Basic, C, and Labview. The USB sends a 16-bit control word to the board, the structure is 12 data bits, 3 command bits and one load bit. The sequence is to present the data and command with the load bit low, then toggle the load bit high then low. The command is executed on the rising edge of the load bit. There are no minimum or maximum timing requirements. For details of the commands, refer to the nPulseSelector.v Verilog file.
|Sorry, no more chance for asking direct questions, queries, broken links, problems, flak, slings, arrows, kudos, criticism, comments, brickbats, corrections or suggestions.|