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Electrical Double-Layer Transistors – A Platform for Examining Surface Conduction at Carrier Densities Near 1014 cm-2

Transistors with electrolyte gates are termed ‘electrical double-layer transistors’ (EDLTs) and are proving to be very interesting structures for transport measurements because of the very large 2D carrier densities that can be achieved. When a liquid electrolyte is sandwiched between metal plates, application of a voltage to the plates results in motion of the ions to screen the electrical field. To first order, this sets up double layers at both plate/electrolyte interfaces in which a sheet of electronic charge in the metal is balanced by a sheet of oppositely charged ions in the electrolyte. The capacitance of these very thin (~1 nm) double layers is enormous, >10 mF/cm 2 . In a similar fashion, the large capacitance of electrolytes may be exploited in an EDLT to induce very large hole or electron densities at the surface of a semiconductor in contact with electrolyte. With an EDLT it is possible to study transport in a variety of materials at gate-tunable carrier densities ranging from 10 12 to >10 14 cm -2 ; these densities are large enough in principle to examine the metal-insulator transition and the onset of superconductivity in specific systems. In this talk I will describe a fascinating and relatively new class of electrolytes termed room temperature ionic liquids and discuss their application in EDLTs, especially EDLTs based on organic semiconductors.